2 * Copyright 2014 Freescale Semiconductor, Inc.
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
9 #include <dt-bindings/clock/imx6sx-clock.h>
10 #include <dt-bindings/gpio/gpio.h>
11 #include <dt-bindings/input/input.h>
12 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #include "imx6sx-pinfunc.h"
19 * The decompressor and also some bootloaders rely on a
20 * pre-existing /chosen node to be available to insert the
21 * command line and merge other ATAGS info.
22 * Also for U-Boot there must be a pre-existing /memory node.
25 memory { device_type = "memory"; reg = <0 0>; };
67 compatible = "arm,cortex-a9";
70 next-level-cache = <&L2>;
78 fsl,soc-operating-points = <
85 clock-latency = <61036>; /* two CLK32 periods */
86 clocks = <&clks IMX6SX_CLK_ARM>,
87 <&clks IMX6SX_CLK_PLL2_PFD2>,
88 <&clks IMX6SX_CLK_STEP>,
89 <&clks IMX6SX_CLK_PLL1_SW>,
90 <&clks IMX6SX_CLK_PLL1_SYS>;
91 clock-names = "arm", "pll2_pfd2_396m", "step",
92 "pll1_sw", "pll1_sys";
93 arm-supply = <®_arm>;
94 soc-supply = <®_soc>;
98 intc: interrupt-controller@00a01000 {
99 compatible = "arm,cortex-a9-gic";
100 #interrupt-cells = <3>;
101 interrupt-controller;
102 reg = <0x00a01000 0x1000>,
104 interrupt-parent = <&intc>;
108 #address-cells = <1>;
112 compatible = "fixed-clock";
115 clock-frequency = <32768>;
116 clock-output-names = "ckil";
120 compatible = "fixed-clock";
123 clock-frequency = <24000000>;
124 clock-output-names = "osc";
128 compatible = "fixed-clock";
131 clock-frequency = <0>;
132 clock-output-names = "ipp_di0";
136 compatible = "fixed-clock";
139 clock-frequency = <0>;
140 clock-output-names = "ipp_di1";
145 #address-cells = <1>;
147 compatible = "simple-bus";
148 interrupt-parent = <&gpc>;
152 compatible = "arm,cortex-a9-pmu";
153 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
156 ocram: sram@00900000 {
157 compatible = "mmio-sram";
158 reg = <0x00900000 0x20000>;
159 clocks = <&clks IMX6SX_CLK_OCRAM>;
162 L2: l2-cache@00a02000 {
163 compatible = "arm,pl310-cache";
164 reg = <0x00a02000 0x1000>;
165 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
168 arm,tag-latency = <4 2 3>;
169 arm,data-latency = <4 2 3>;
173 compatible = "vivante,gc";
174 reg = <0x01800000 0x4000>;
175 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
176 clocks = <&clks IMX6SX_CLK_GPU>,
177 <&clks IMX6SX_CLK_GPU>,
178 <&clks IMX6SX_CLK_GPU>;
179 clock-names = "bus", "core", "shader";
182 dma_apbh: dma-apbh@01804000 {
183 compatible = "fsl,imx6sx-dma-apbh", "fsl,imx28-dma-apbh";
184 reg = <0x01804000 0x2000>;
185 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
186 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
187 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
188 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
189 interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3";
192 clocks = <&clks IMX6SX_CLK_APBH_DMA>;
195 gpmi: gpmi-nand@01806000{
196 compatible = "fsl,imx6sx-gpmi-nand";
197 #address-cells = <1>;
199 reg = <0x01806000 0x2000>, <0x01808000 0x4000>;
200 reg-names = "gpmi-nand", "bch";
201 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
202 interrupt-names = "bch";
203 clocks = <&clks IMX6SX_CLK_GPMI_IO>,
204 <&clks IMX6SX_CLK_GPMI_APB>,
205 <&clks IMX6SX_CLK_GPMI_BCH>,
206 <&clks IMX6SX_CLK_GPMI_BCH_APB>,
207 <&clks IMX6SX_CLK_PER1_BCH>;
208 clock-names = "gpmi_io", "gpmi_apb", "gpmi_bch",
209 "gpmi_bch_apb", "per1_bch";
210 dmas = <&dma_apbh 0>;
215 aips1: aips-bus@02000000 {
216 compatible = "fsl,aips-bus", "simple-bus";
217 #address-cells = <1>;
219 reg = <0x02000000 0x100000>;
223 compatible = "fsl,spba-bus", "simple-bus";
224 #address-cells = <1>;
226 reg = <0x02000000 0x40000>;
229 spdif: spdif@02004000 {
230 compatible = "fsl,imx6sx-spdif", "fsl,imx35-spdif";
231 reg = <0x02004000 0x4000>;
232 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
233 dmas = <&sdma 14 18 0>,
235 dma-names = "rx", "tx";
236 clocks = <&clks IMX6SX_CLK_SPDIF_GCLK>,
237 <&clks IMX6SX_CLK_OSC>,
238 <&clks IMX6SX_CLK_SPDIF>,
239 <&clks 0>, <&clks 0>, <&clks 0>,
240 <&clks IMX6SX_CLK_IPG>,
241 <&clks 0>, <&clks 0>,
242 <&clks IMX6SX_CLK_SPBA>;
243 clock-names = "core", "rxtx0",
251 ecspi1: ecspi@02008000 {
252 #address-cells = <1>;
254 compatible = "fsl,imx6sx-ecspi", "fsl,imx51-ecspi";
255 reg = <0x02008000 0x4000>;
256 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
257 clocks = <&clks IMX6SX_CLK_ECSPI1>,
258 <&clks IMX6SX_CLK_ECSPI1>;
259 clock-names = "ipg", "per";
263 ecspi2: ecspi@0200c000 {
264 #address-cells = <1>;
266 compatible = "fsl,imx6sx-ecspi", "fsl,imx51-ecspi";
267 reg = <0x0200c000 0x4000>;
268 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
269 clocks = <&clks IMX6SX_CLK_ECSPI2>,
270 <&clks IMX6SX_CLK_ECSPI2>;
271 clock-names = "ipg", "per";
275 ecspi3: ecspi@02010000 {
276 #address-cells = <1>;
278 compatible = "fsl,imx6sx-ecspi", "fsl,imx51-ecspi";
279 reg = <0x02010000 0x4000>;
280 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
281 clocks = <&clks IMX6SX_CLK_ECSPI3>,
282 <&clks IMX6SX_CLK_ECSPI3>;
283 clock-names = "ipg", "per";
287 ecspi4: ecspi@02014000 {
288 #address-cells = <1>;
290 compatible = "fsl,imx6sx-ecspi", "fsl,imx51-ecspi";
291 reg = <0x02014000 0x4000>;
292 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
293 clocks = <&clks IMX6SX_CLK_ECSPI4>,
294 <&clks IMX6SX_CLK_ECSPI4>;
295 clock-names = "ipg", "per";
299 uart1: serial@02020000 {
300 compatible = "fsl,imx6sx-uart",
301 "fsl,imx6q-uart", "fsl,imx21-uart";
302 reg = <0x02020000 0x4000>;
303 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
304 clocks = <&clks IMX6SX_CLK_UART_IPG>,
305 <&clks IMX6SX_CLK_UART_SERIAL>;
306 clock-names = "ipg", "per";
307 dmas = <&sdma 25 4 0>, <&sdma 26 4 0>;
308 dma-names = "rx", "tx";
312 esai: esai@02024000 {
313 reg = <0x02024000 0x4000>;
314 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
315 clocks = <&clks IMX6SX_CLK_ESAI_IPG>,
316 <&clks IMX6SX_CLK_ESAI_MEM>,
317 <&clks IMX6SX_CLK_ESAI_EXTAL>,
318 <&clks IMX6SX_CLK_ESAI_IPG>,
319 <&clks IMX6SX_CLK_SPBA>;
320 clock-names = "core", "mem", "extal",
326 #sound-dai-cells = <0>;
327 compatible = "fsl,imx6sx-ssi", "fsl,imx51-ssi";
328 reg = <0x02028000 0x4000>;
329 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
330 clocks = <&clks IMX6SX_CLK_SSI1_IPG>,
331 <&clks IMX6SX_CLK_SSI1>;
332 clock-names = "ipg", "baud";
333 dmas = <&sdma 37 1 0>, <&sdma 38 1 0>;
334 dma-names = "rx", "tx";
335 fsl,fifo-depth = <15>;
340 #sound-dai-cells = <0>;
341 compatible = "fsl,imx6sx-ssi", "fsl,imx51-ssi";
342 reg = <0x0202c000 0x4000>;
343 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
344 clocks = <&clks IMX6SX_CLK_SSI2_IPG>,
345 <&clks IMX6SX_CLK_SSI2>;
346 clock-names = "ipg", "baud";
347 dmas = <&sdma 41 1 0>, <&sdma 42 1 0>;
348 dma-names = "rx", "tx";
349 fsl,fifo-depth = <15>;
354 #sound-dai-cells = <0>;
355 compatible = "fsl,imx6sx-ssi", "fsl,imx51-ssi";
356 reg = <0x02030000 0x4000>;
357 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
358 clocks = <&clks IMX6SX_CLK_SSI3_IPG>,
359 <&clks IMX6SX_CLK_SSI3>;
360 clock-names = "ipg", "baud";
361 dmas = <&sdma 45 1 0>, <&sdma 46 1 0>;
362 dma-names = "rx", "tx";
363 fsl,fifo-depth = <15>;
367 asrc: asrc@02034000 {
368 reg = <0x02034000 0x4000>;
369 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
370 clocks = <&clks IMX6SX_CLK_ASRC_MEM>,
371 <&clks IMX6SX_CLK_ASRC_IPG>,
372 <&clks IMX6SX_CLK_SPDIF>,
373 <&clks IMX6SX_CLK_SPBA>;
374 clock-names = "mem", "ipg", "asrck", "spba";
375 dmas = <&sdma 17 20 1>, <&sdma 18 20 1>,
376 <&sdma 19 20 1>, <&sdma 20 20 1>,
377 <&sdma 21 20 1>, <&sdma 22 20 1>;
378 dma-names = "rxa", "rxb", "rxc",
385 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
386 reg = <0x02080000 0x4000>;
387 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
388 clocks = <&clks IMX6SX_CLK_PWM1>,
389 <&clks IMX6SX_CLK_PWM1>;
390 clock-names = "ipg", "per";
395 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
396 reg = <0x02084000 0x4000>;
397 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
398 clocks = <&clks IMX6SX_CLK_PWM2>,
399 <&clks IMX6SX_CLK_PWM2>;
400 clock-names = "ipg", "per";
405 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
406 reg = <0x02088000 0x4000>;
407 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
408 clocks = <&clks IMX6SX_CLK_PWM3>,
409 <&clks IMX6SX_CLK_PWM3>;
410 clock-names = "ipg", "per";
415 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
416 reg = <0x0208c000 0x4000>;
417 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
418 clocks = <&clks IMX6SX_CLK_PWM4>,
419 <&clks IMX6SX_CLK_PWM4>;
420 clock-names = "ipg", "per";
424 flexcan1: can@02090000 {
425 compatible = "fsl,imx6sx-flexcan", "fsl,imx6q-flexcan";
426 reg = <0x02090000 0x4000>;
427 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
428 clocks = <&clks IMX6SX_CLK_CAN1_IPG>,
429 <&clks IMX6SX_CLK_CAN1_SERIAL>;
430 clock-names = "ipg", "per";
434 flexcan2: can@02094000 {
435 compatible = "fsl,imx6sx-flexcan", "fsl,imx6q-flexcan";
436 reg = <0x02094000 0x4000>;
437 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
438 clocks = <&clks IMX6SX_CLK_CAN2_IPG>,
439 <&clks IMX6SX_CLK_CAN2_SERIAL>;
440 clock-names = "ipg", "per";
445 compatible = "fsl,imx6sx-gpt", "fsl,imx31-gpt";
446 reg = <0x02098000 0x4000>;
447 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
448 clocks = <&clks IMX6SX_CLK_GPT_BUS>,
449 <&clks IMX6SX_CLK_GPT_3M>;
450 clock-names = "ipg", "per";
453 gpio1: gpio@0209c000 {
454 compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio";
455 reg = <0x0209c000 0x4000>;
456 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
457 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
460 interrupt-controller;
461 #interrupt-cells = <2>;
462 gpio-ranges = <&iomuxc 0 5 26>;
465 gpio2: gpio@020a0000 {
466 compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio";
467 reg = <0x020a0000 0x4000>;
468 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
469 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
472 interrupt-controller;
473 #interrupt-cells = <2>;
474 gpio-ranges = <&iomuxc 0 31 20>;
477 gpio3: gpio@020a4000 {
478 compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio";
479 reg = <0x020a4000 0x4000>;
480 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
481 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
484 interrupt-controller;
485 #interrupt-cells = <2>;
486 gpio-ranges = <&iomuxc 0 51 29>;
489 gpio4: gpio@020a8000 {
490 compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio";
491 reg = <0x020a8000 0x4000>;
492 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
493 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
496 interrupt-controller;
497 #interrupt-cells = <2>;
498 gpio-ranges = <&iomuxc 0 80 32>;
501 gpio5: gpio@020ac000 {
502 compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio";
503 reg = <0x020ac000 0x4000>;
504 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
505 <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
508 interrupt-controller;
509 #interrupt-cells = <2>;
510 gpio-ranges = <&iomuxc 0 112 24>;
513 gpio6: gpio@020b0000 {
514 compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio";
515 reg = <0x020b0000 0x4000>;
516 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
517 <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
520 interrupt-controller;
521 #interrupt-cells = <2>;
522 gpio-ranges = <&iomuxc 0 136 12>, <&iomuxc 12 158 11>;
525 gpio7: gpio@020b4000 {
526 compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio";
527 reg = <0x020b4000 0x4000>;
528 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>,
529 <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
532 interrupt-controller;
533 #interrupt-cells = <2>;
534 gpio-ranges = <&iomuxc 0 148 10>, <&iomuxc 10 169 2>;
538 compatible = "fsl,imx6sx-kpp", "fsl,imx21-kpp";
539 reg = <0x020b8000 0x4000>;
540 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
541 clocks = <&clks IMX6SX_CLK_DUMMY>;
545 wdog1: wdog@020bc000 {
546 compatible = "fsl,imx6sx-wdt", "fsl,imx21-wdt";
547 reg = <0x020bc000 0x4000>;
548 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
549 clocks = <&clks IMX6SX_CLK_DUMMY>;
552 wdog2: wdog@020c0000 {
553 compatible = "fsl,imx6sx-wdt", "fsl,imx21-wdt";
554 reg = <0x020c0000 0x4000>;
555 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
556 clocks = <&clks IMX6SX_CLK_DUMMY>;
561 compatible = "fsl,imx6sx-ccm";
562 reg = <0x020c4000 0x4000>;
563 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
564 <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
566 clocks = <&ckil>, <&osc>, <&ipp_di0>, <&ipp_di1>;
567 clock-names = "ckil", "osc", "ipp_di0", "ipp_di1";
570 anatop: anatop@020c8000 {
571 compatible = "fsl,imx6sx-anatop", "fsl,imx6q-anatop",
572 "syscon", "simple-bus";
573 reg = <0x020c8000 0x1000>;
574 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
575 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
576 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
579 compatible = "fsl,anatop-regulator";
580 regulator-name = "vdd1p1";
581 regulator-min-microvolt = <800000>;
582 regulator-max-microvolt = <1375000>;
584 anatop-reg-offset = <0x110>;
585 anatop-vol-bit-shift = <8>;
586 anatop-vol-bit-width = <5>;
587 anatop-min-bit-val = <4>;
588 anatop-min-voltage = <800000>;
589 anatop-max-voltage = <1375000>;
593 compatible = "fsl,anatop-regulator";
594 regulator-name = "vdd3p0";
595 regulator-min-microvolt = <2800000>;
596 regulator-max-microvolt = <3150000>;
598 anatop-reg-offset = <0x120>;
599 anatop-vol-bit-shift = <8>;
600 anatop-vol-bit-width = <5>;
601 anatop-min-bit-val = <0>;
602 anatop-min-voltage = <2625000>;
603 anatop-max-voltage = <3400000>;
607 compatible = "fsl,anatop-regulator";
608 regulator-name = "vdd2p5";
609 regulator-min-microvolt = <2100000>;
610 regulator-max-microvolt = <2875000>;
612 anatop-reg-offset = <0x130>;
613 anatop-vol-bit-shift = <8>;
614 anatop-vol-bit-width = <5>;
615 anatop-min-bit-val = <0>;
616 anatop-min-voltage = <2100000>;
617 anatop-max-voltage = <2875000>;
620 reg_arm: regulator-vddcore {
621 compatible = "fsl,anatop-regulator";
622 regulator-name = "vddarm";
623 regulator-min-microvolt = <725000>;
624 regulator-max-microvolt = <1450000>;
626 anatop-reg-offset = <0x140>;
627 anatop-vol-bit-shift = <0>;
628 anatop-vol-bit-width = <5>;
629 anatop-delay-reg-offset = <0x170>;
630 anatop-delay-bit-shift = <24>;
631 anatop-delay-bit-width = <2>;
632 anatop-min-bit-val = <1>;
633 anatop-min-voltage = <725000>;
634 anatop-max-voltage = <1450000>;
637 reg_pcie: regulator-vddpcie {
638 compatible = "fsl,anatop-regulator";
639 regulator-name = "vddpcie";
640 regulator-min-microvolt = <725000>;
641 regulator-max-microvolt = <1450000>;
642 anatop-reg-offset = <0x140>;
643 anatop-vol-bit-shift = <9>;
644 anatop-vol-bit-width = <5>;
645 anatop-delay-reg-offset = <0x170>;
646 anatop-delay-bit-shift = <26>;
647 anatop-delay-bit-width = <2>;
648 anatop-min-bit-val = <1>;
649 anatop-min-voltage = <725000>;
650 anatop-max-voltage = <1450000>;
653 reg_soc: regulator-vddsoc {
654 compatible = "fsl,anatop-regulator";
655 regulator-name = "vddsoc";
656 regulator-min-microvolt = <725000>;
657 regulator-max-microvolt = <1450000>;
659 anatop-reg-offset = <0x140>;
660 anatop-vol-bit-shift = <18>;
661 anatop-vol-bit-width = <5>;
662 anatop-delay-reg-offset = <0x170>;
663 anatop-delay-bit-shift = <28>;
664 anatop-delay-bit-width = <2>;
665 anatop-min-bit-val = <1>;
666 anatop-min-voltage = <725000>;
667 anatop-max-voltage = <1450000>;
672 compatible = "fsl,imx6sx-tempmon", "fsl,imx6q-tempmon";
673 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
674 fsl,tempmon = <&anatop>;
675 fsl,tempmon-data = <&ocotp>;
676 clocks = <&clks IMX6SX_CLK_PLL3_USB_OTG>;
679 usbphy1: usbphy@020c9000 {
680 compatible = "fsl,imx6sx-usbphy", "fsl,imx23-usbphy";
681 reg = <0x020c9000 0x1000>;
682 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
683 clocks = <&clks IMX6SX_CLK_USBPHY1>;
684 fsl,anatop = <&anatop>;
687 usbphy2: usbphy@020ca000 {
688 compatible = "fsl,imx6sx-usbphy", "fsl,imx23-usbphy";
689 reg = <0x020ca000 0x1000>;
690 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
691 clocks = <&clks IMX6SX_CLK_USBPHY2>;
692 fsl,anatop = <&anatop>;
695 snvs: snvs@020cc000 {
696 compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd";
697 reg = <0x020cc000 0x4000>;
699 snvs_rtc: snvs-rtc-lp {
700 compatible = "fsl,sec-v4.0-mon-rtc-lp";
703 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
706 snvs_poweroff: snvs-poweroff {
707 compatible = "syscon-poweroff";
714 snvs_pwrkey: snvs-powerkey {
715 compatible = "fsl,sec-v4.0-pwrkey";
717 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
718 linux,keycode = <KEY_POWER>;
723 epit1: epit@020d0000 {
724 reg = <0x020d0000 0x4000>;
725 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
728 epit2: epit@020d4000 {
729 reg = <0x020d4000 0x4000>;
730 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
734 compatible = "fsl,imx6sx-src", "fsl,imx51-src";
735 reg = <0x020d8000 0x4000>;
736 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,
737 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
742 compatible = "fsl,imx6sx-gpc", "fsl,imx6q-gpc";
743 reg = <0x020dc000 0x4000>;
744 interrupt-controller;
745 #interrupt-cells = <3>;
746 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
747 interrupt-parent = <&intc>;
750 iomuxc: iomuxc@020e0000 {
751 compatible = "fsl,imx6sx-iomuxc";
752 reg = <0x020e0000 0x4000>;
755 gpr: iomuxc-gpr@020e4000 {
756 compatible = "fsl,imx6sx-iomuxc-gpr",
757 "fsl,imx6q-iomuxc-gpr", "syscon";
758 reg = <0x020e4000 0x4000>;
761 sdma: sdma@020ec000 {
762 compatible = "fsl,imx6sx-sdma", "fsl,imx6q-sdma";
763 reg = <0x020ec000 0x4000>;
764 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
765 clocks = <&clks IMX6SX_CLK_SDMA>,
766 <&clks IMX6SX_CLK_SDMA>;
767 clock-names = "ipg", "ahb";
769 /* imx6sx reuses imx6q sdma firmware */
770 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin";
774 aips2: aips-bus@02100000 {
775 compatible = "fsl,aips-bus", "simple-bus";
776 #address-cells = <1>;
778 reg = <0x02100000 0x100000>;
781 crypto: caam@2100000 {
782 compatible = "fsl,sec-v4.0";
784 #address-cells = <1>;
786 reg = <0x2100000 0x10000>;
787 ranges = <0 0x2100000 0x10000>;
788 interrupt-parent = <&intc>;
789 clocks = <&clks IMX6SX_CLK_CAAM_MEM>,
790 <&clks IMX6SX_CLK_CAAM_ACLK>,
791 <&clks IMX6SX_CLK_CAAM_IPG>,
792 <&clks IMX6SX_CLK_EIM_SLOW>;
793 clock-names = "mem", "aclk", "ipg", "emi_slow";
796 compatible = "fsl,sec-v4.0-job-ring";
797 reg = <0x1000 0x1000>;
798 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
802 compatible = "fsl,sec-v4.0-job-ring";
803 reg = <0x2000 0x1000>;
804 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
808 usbotg1: usb@02184000 {
809 compatible = "fsl,imx6sx-usb", "fsl,imx27-usb";
810 reg = <0x02184000 0x200>;
811 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
812 clocks = <&clks IMX6SX_CLK_USBOH3>;
813 fsl,usbphy = <&usbphy1>;
814 fsl,usbmisc = <&usbmisc 0>;
815 fsl,anatop = <&anatop>;
816 ahb-burst-config = <0x0>;
817 tx-burst-size-dword = <0x10>;
818 rx-burst-size-dword = <0x10>;
822 usbotg2: usb@02184200 {
823 compatible = "fsl,imx6sx-usb", "fsl,imx27-usb";
824 reg = <0x02184200 0x200>;
825 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
826 clocks = <&clks IMX6SX_CLK_USBOH3>;
827 fsl,usbphy = <&usbphy2>;
828 fsl,usbmisc = <&usbmisc 1>;
829 ahb-burst-config = <0x0>;
830 tx-burst-size-dword = <0x10>;
831 rx-burst-size-dword = <0x10>;
836 compatible = "fsl,imx6sx-usb", "fsl,imx27-usb";
837 reg = <0x02184400 0x200>;
838 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
839 clocks = <&clks IMX6SX_CLK_USBOH3>;
840 fsl,usbmisc = <&usbmisc 2>;
842 fsl,anatop = <&anatop>;
844 ahb-burst-config = <0x0>;
845 tx-burst-size-dword = <0x10>;
846 rx-burst-size-dword = <0x10>;
850 usbmisc: usbmisc@02184800 {
852 compatible = "fsl,imx6sx-usbmisc", "fsl,imx6q-usbmisc";
853 reg = <0x02184800 0x200>;
854 clocks = <&clks IMX6SX_CLK_USBOH3>;
857 fec1: ethernet@02188000 {
858 compatible = "fsl,imx6sx-fec", "fsl,imx6q-fec";
859 reg = <0x02188000 0x4000>;
860 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
861 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
862 clocks = <&clks IMX6SX_CLK_ENET>,
863 <&clks IMX6SX_CLK_ENET_AHB>,
864 <&clks IMX6SX_CLK_ENET_PTP>,
865 <&clks IMX6SX_CLK_ENET_REF>,
866 <&clks IMX6SX_CLK_ENET_PTP>;
867 clock-names = "ipg", "ahb", "ptp",
868 "enet_clk_ref", "enet_out";
869 fsl,num-tx-queues=<3>;
870 fsl,num-rx-queues=<3>;
875 reg = <0x0218c000 0x4000>;
876 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
877 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
878 <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
879 clocks = <&clks IMX6SX_CLK_MLB>;
883 usdhc1: usdhc@02190000 {
884 compatible = "fsl,imx6sx-usdhc", "fsl,imx6sl-usdhc";
885 reg = <0x02190000 0x4000>;
886 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
887 clocks = <&clks IMX6SX_CLK_USDHC1>,
888 <&clks IMX6SX_CLK_USDHC1>,
889 <&clks IMX6SX_CLK_USDHC1>;
890 clock-names = "ipg", "ahb", "per";
895 usdhc2: usdhc@02194000 {
896 compatible = "fsl,imx6sx-usdhc", "fsl,imx6sl-usdhc";
897 reg = <0x02194000 0x4000>;
898 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
899 clocks = <&clks IMX6SX_CLK_USDHC2>,
900 <&clks IMX6SX_CLK_USDHC2>,
901 <&clks IMX6SX_CLK_USDHC2>;
902 clock-names = "ipg", "ahb", "per";
907 usdhc3: usdhc@02198000 {
908 compatible = "fsl,imx6sx-usdhc", "fsl,imx6sl-usdhc";
909 reg = <0x02198000 0x4000>;
910 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
911 clocks = <&clks IMX6SX_CLK_USDHC3>,
912 <&clks IMX6SX_CLK_USDHC3>,
913 <&clks IMX6SX_CLK_USDHC3>;
914 clock-names = "ipg", "ahb", "per";
919 usdhc4: usdhc@0219c000 {
920 compatible = "fsl,imx6sx-usdhc", "fsl,imx6sl-usdhc";
921 reg = <0x0219c000 0x4000>;
922 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
923 clocks = <&clks IMX6SX_CLK_USDHC4>,
924 <&clks IMX6SX_CLK_USDHC4>,
925 <&clks IMX6SX_CLK_USDHC4>;
926 clock-names = "ipg", "ahb", "per";
932 #address-cells = <1>;
934 compatible = "fsl,imx6sx-i2c", "fsl,imx21-i2c";
935 reg = <0x021a0000 0x4000>;
936 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
937 clocks = <&clks IMX6SX_CLK_I2C1>;
942 #address-cells = <1>;
944 compatible = "fsl,imx6sx-i2c", "fsl,imx21-i2c";
945 reg = <0x021a4000 0x4000>;
946 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
947 clocks = <&clks IMX6SX_CLK_I2C2>;
952 #address-cells = <1>;
954 compatible = "fsl,imx6sx-i2c", "fsl,imx21-i2c";
955 reg = <0x021a8000 0x4000>;
956 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
957 clocks = <&clks IMX6SX_CLK_I2C3>;
961 mmdc: mmdc@021b0000 {
962 compatible = "fsl,imx6sx-mmdc", "fsl,imx6q-mmdc";
963 reg = <0x021b0000 0x4000>;
966 fec2: ethernet@021b4000 {
967 compatible = "fsl,imx6sx-fec", "fsl,imx6q-fec";
968 reg = <0x021b4000 0x4000>;
969 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
970 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
971 clocks = <&clks IMX6SX_CLK_ENET>,
972 <&clks IMX6SX_CLK_ENET_AHB>,
973 <&clks IMX6SX_CLK_ENET_PTP>,
974 <&clks IMX6SX_CLK_ENET2_REF_125M>,
975 <&clks IMX6SX_CLK_ENET_PTP>;
976 clock-names = "ipg", "ahb", "ptp",
977 "enet_clk_ref", "enet_out";
981 weim: weim@021b8000 {
982 #address-cells = <2>;
984 compatible = "fsl,imx6sx-weim", "fsl,imx6q-weim";
985 reg = <0x021b8000 0x4000>;
986 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
987 clocks = <&clks IMX6SX_CLK_EIM_SLOW>;
988 fsl,weim-cs-gpr = <&gpr>;
992 ocotp: ocotp@021bc000 {
993 compatible = "fsl,imx6sx-ocotp", "syscon";
994 reg = <0x021bc000 0x4000>;
995 clocks = <&clks IMX6SX_CLK_OCOTP>;
999 compatible = "fsl,imx6sx-sai";
1000 reg = <0x021d4000 0x4000>;
1001 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
1002 clocks = <&clks IMX6SX_CLK_SAI1_IPG>,
1003 <&clks IMX6SX_CLK_SAI1>,
1004 <&clks 0>, <&clks 0>;
1005 clock-names = "bus", "mclk1", "mclk2", "mclk3";
1006 dma-names = "rx", "tx";
1007 dmas = <&sdma 31 24 0>, <&sdma 32 24 0>;
1008 status = "disabled";
1011 audmux: audmux@021d8000 {
1012 compatible = "fsl,imx6sx-audmux", "fsl,imx31-audmux";
1013 reg = <0x021d8000 0x4000>;
1014 status = "disabled";
1017 sai2: sai@021dc000 {
1018 compatible = "fsl,imx6sx-sai";
1019 reg = <0x021dc000 0x4000>;
1020 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
1021 clocks = <&clks IMX6SX_CLK_SAI2_IPG>,
1022 <&clks IMX6SX_CLK_SAI2>,
1023 <&clks 0>, <&clks 0>;
1024 clock-names = "bus", "mclk1", "mclk2", "mclk3";
1025 dma-names = "rx", "tx";
1026 dmas = <&sdma 33 24 0>, <&sdma 34 24 0>;
1027 status = "disabled";
1030 qspi1: qspi@021e0000 {
1031 #address-cells = <1>;
1033 compatible = "fsl,imx6sx-qspi";
1034 reg = <0x021e0000 0x4000>, <0x60000000 0x10000000>;
1035 reg-names = "QuadSPI", "QuadSPI-memory";
1036 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
1037 clocks = <&clks IMX6SX_CLK_QSPI1>,
1038 <&clks IMX6SX_CLK_QSPI1>;
1039 clock-names = "qspi_en", "qspi";
1040 status = "disabled";
1043 qspi2: qspi@021e4000 {
1044 #address-cells = <1>;
1046 compatible = "fsl,imx6sx-qspi";
1047 reg = <0x021e4000 0x4000>, <0x70000000 0x10000000>;
1048 reg-names = "QuadSPI", "QuadSPI-memory";
1049 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
1050 clocks = <&clks IMX6SX_CLK_QSPI2>,
1051 <&clks IMX6SX_CLK_QSPI2>;
1052 clock-names = "qspi_en", "qspi";
1053 status = "disabled";
1056 uart2: serial@021e8000 {
1057 compatible = "fsl,imx6sx-uart",
1058 "fsl,imx6q-uart", "fsl,imx21-uart";
1059 reg = <0x021e8000 0x4000>;
1060 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
1061 clocks = <&clks IMX6SX_CLK_UART_IPG>,
1062 <&clks IMX6SX_CLK_UART_SERIAL>;
1063 clock-names = "ipg", "per";
1064 dmas = <&sdma 27 4 0>, <&sdma 28 4 0>;
1065 dma-names = "rx", "tx";
1066 status = "disabled";
1069 uart3: serial@021ec000 {
1070 compatible = "fsl,imx6sx-uart",
1071 "fsl,imx6q-uart", "fsl,imx21-uart";
1072 reg = <0x021ec000 0x4000>;
1073 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
1074 clocks = <&clks IMX6SX_CLK_UART_IPG>,
1075 <&clks IMX6SX_CLK_UART_SERIAL>;
1076 clock-names = "ipg", "per";
1077 dmas = <&sdma 29 4 0>, <&sdma 30 4 0>;
1078 dma-names = "rx", "tx";
1079 status = "disabled";
1082 uart4: serial@021f0000 {
1083 compatible = "fsl,imx6sx-uart",
1084 "fsl,imx6q-uart", "fsl,imx21-uart";
1085 reg = <0x021f0000 0x4000>;
1086 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
1087 clocks = <&clks IMX6SX_CLK_UART_IPG>,
1088 <&clks IMX6SX_CLK_UART_SERIAL>;
1089 clock-names = "ipg", "per";
1090 dmas = <&sdma 31 4 0>, <&sdma 32 4 0>;
1091 dma-names = "rx", "tx";
1092 status = "disabled";
1095 uart5: serial@021f4000 {
1096 compatible = "fsl,imx6sx-uart",
1097 "fsl,imx6q-uart", "fsl,imx21-uart";
1098 reg = <0x021f4000 0x4000>;
1099 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
1100 clocks = <&clks IMX6SX_CLK_UART_IPG>,
1101 <&clks IMX6SX_CLK_UART_SERIAL>;
1102 clock-names = "ipg", "per";
1103 dmas = <&sdma 33 4 0>, <&sdma 34 4 0>;
1104 dma-names = "rx", "tx";
1105 status = "disabled";
1108 i2c4: i2c@021f8000 {
1109 #address-cells = <1>;
1111 compatible = "fsl,imx6sx-i2c", "fsl,imx21-i2c";
1112 reg = <0x021f8000 0x4000>;
1113 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
1114 clocks = <&clks IMX6SX_CLK_I2C4>;
1115 status = "disabled";
1119 aips3: aips-bus@02200000 {
1120 compatible = "fsl,aips-bus", "simple-bus";
1121 #address-cells = <1>;
1123 reg = <0x02200000 0x100000>;
1127 compatible = "fsl,spba-bus", "simple-bus";
1128 #address-cells = <1>;
1130 reg = <0x02240000 0x40000>;
1133 csi1: csi@02214000 {
1134 reg = <0x02214000 0x4000>;
1135 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
1136 clocks = <&clks IMX6SX_CLK_DISPLAY_AXI>,
1137 <&clks IMX6SX_CLK_CSI>,
1138 <&clks IMX6SX_CLK_DCIC1>;
1139 clock-names = "disp-axi", "csi_mclk", "dcic";
1140 status = "disabled";
1144 reg = <0x02218000 0x4000>;
1145 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
1146 clocks = <&clks IMX6SX_CLK_PXP_AXI>,
1147 <&clks IMX6SX_CLK_DISPLAY_AXI>;
1148 clock-names = "pxp-axi", "disp-axi";
1149 status = "disabled";
1152 csi2: csi@0221c000 {
1153 reg = <0x0221c000 0x4000>;
1154 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
1155 clocks = <&clks IMX6SX_CLK_DISPLAY_AXI>,
1156 <&clks IMX6SX_CLK_CSI>,
1157 <&clks IMX6SX_CLK_DCIC2>;
1158 clock-names = "disp-axi", "csi_mclk", "dcic";
1159 status = "disabled";
1162 lcdif1: lcdif@02220000 {
1163 compatible = "fsl,imx6sx-lcdif", "fsl,imx28-lcdif";
1164 reg = <0x02220000 0x4000>;
1165 interrupts = <GIC_SPI 5 IRQ_TYPE_EDGE_RISING>;
1166 clocks = <&clks IMX6SX_CLK_LCDIF1_PIX>,
1167 <&clks IMX6SX_CLK_LCDIF_APB>,
1168 <&clks IMX6SX_CLK_DISPLAY_AXI>;
1169 clock-names = "pix", "axi", "disp_axi";
1170 status = "disabled";
1173 lcdif2: lcdif@02224000 {
1174 compatible = "fsl,imx6sx-lcdif", "fsl,imx28-lcdif";
1175 reg = <0x02224000 0x4000>;
1176 interrupts = <GIC_SPI 6 IRQ_TYPE_EDGE_RISING>;
1177 clocks = <&clks IMX6SX_CLK_LCDIF2_PIX>,
1178 <&clks IMX6SX_CLK_LCDIF_APB>,
1179 <&clks IMX6SX_CLK_DISPLAY_AXI>;
1180 clock-names = "pix", "axi", "disp_axi";
1181 status = "disabled";
1184 vadc: vadc@02228000 {
1185 reg = <0x02228000 0x4000>, <0x0222c000 0x4000>;
1186 reg-names = "vadc-vafe", "vadc-vdec";
1187 clocks = <&clks IMX6SX_CLK_VADC>,
1188 <&clks IMX6SX_CLK_CSI>;
1189 clock-names = "vadc", "csi";
1190 status = "disabled";
1194 adc1: adc@02280000 {
1195 compatible = "fsl,imx6sx-adc", "fsl,vf610-adc";
1196 reg = <0x02280000 0x4000>;
1197 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
1198 clocks = <&clks IMX6SX_CLK_IPG>;
1199 clock-names = "adc";
1200 fsl,adck-max-frequency = <30000000>, <40000000>,
1202 status = "disabled";
1205 adc2: adc@02284000 {
1206 compatible = "fsl,imx6sx-adc", "fsl,vf610-adc";
1207 reg = <0x02284000 0x4000>;
1208 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
1209 clocks = <&clks IMX6SX_CLK_IPG>;
1210 clock-names = "adc";
1211 fsl,adck-max-frequency = <30000000>, <40000000>,
1213 status = "disabled";
1216 wdog3: wdog@02288000 {
1217 compatible = "fsl,imx6sx-wdt", "fsl,imx21-wdt";
1218 reg = <0x02288000 0x4000>;
1219 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
1220 clocks = <&clks IMX6SX_CLK_DUMMY>;
1221 status = "disabled";
1224 ecspi5: ecspi@0228c000 {
1225 #address-cells = <1>;
1227 compatible = "fsl,imx6sx-ecspi", "fsl,imx51-ecspi";
1228 reg = <0x0228c000 0x4000>;
1229 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
1230 clocks = <&clks IMX6SX_CLK_ECSPI5>,
1231 <&clks IMX6SX_CLK_ECSPI5>;
1232 clock-names = "ipg", "per";
1233 status = "disabled";
1236 uart6: serial@022a0000 {
1237 compatible = "fsl,imx6sx-uart",
1238 "fsl,imx6q-uart", "fsl,imx21-uart";
1239 reg = <0x022a0000 0x4000>;
1240 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
1241 clocks = <&clks IMX6SX_CLK_UART_IPG>,
1242 <&clks IMX6SX_CLK_UART_SERIAL>;
1243 clock-names = "ipg", "per";
1244 dmas = <&sdma 0 4 0>, <&sdma 47 4 0>;
1245 dma-names = "rx", "tx";
1246 status = "disabled";
1249 pwm5: pwm@022a4000 {
1250 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
1251 reg = <0x022a4000 0x4000>;
1252 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
1253 clocks = <&clks IMX6SX_CLK_PWM5>,
1254 <&clks IMX6SX_CLK_PWM5>;
1255 clock-names = "ipg", "per";
1259 pwm6: pwm@022a8000 {
1260 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
1261 reg = <0x022a8000 0x4000>;
1262 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
1263 clocks = <&clks IMX6SX_CLK_PWM6>,
1264 <&clks IMX6SX_CLK_PWM6>;
1265 clock-names = "ipg", "per";
1269 pwm7: pwm@022ac000 {
1270 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
1271 reg = <0x022ac000 0x4000>;
1272 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
1273 clocks = <&clks IMX6SX_CLK_PWM7>,
1274 <&clks IMX6SX_CLK_PWM7>;
1275 clock-names = "ipg", "per";
1279 pwm8: pwm@0022b0000 {
1280 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
1281 reg = <0x0022b0000 0x4000>;
1282 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
1283 clocks = <&clks IMX6SX_CLK_PWM8>,
1284 <&clks IMX6SX_CLK_PWM8>;
1285 clock-names = "ipg", "per";
1290 pcie: pcie@8ffc000 {
1291 compatible = "fsl,imx6sx-pcie", "snps,dw-pcie";
1292 reg = <0x08ffc000 0x4000>; /* DBI */
1293 #address-cells = <3>;
1295 device_type = "pci";
1296 /* configuration space */
1297 ranges = <0x00000800 0 0x08f00000 0x08f00000 0 0x00080000
1298 /* downstream I/O */
1299 0x81000000 0 0 0x08f80000 0 0x00010000
1300 /* non-prefetchable memory */
1301 0x82000000 0 0x08000000 0x08000000 0 0x00f00000>;
1302 bus-range = <0x00 0xff>;
1304 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
1305 clocks = <&clks IMX6SX_CLK_PCIE_REF_125M>,
1306 <&clks IMX6SX_CLK_PCIE_AXI>,
1307 <&clks IMX6SX_CLK_LVDS1_OUT>,
1308 <&clks IMX6SX_CLK_DISPLAY_AXI>;
1309 clock-names = "pcie_ref_125m", "pcie_axi",
1310 "lvds_gate", "display_axi";
1311 status = "disabled";
1316 compatible = "fsl,imx-gpu-subsystem";