2 * Copyright (C) 2015 Freescale Semiconductor, Inc.
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
11 #include "imx6ul.dtsi"
14 model = "Freescale i.MX6 UltraLite 14x14 EVK Board";
15 compatible = "fsl,imx6ul-14x14-evk", "fsl,imx6ul";
22 reg = <0x80000000 0x20000000>;
25 backlight_display: backlight-display {
26 compatible = "pwm-backlight";
27 pwms = <&pwm1 0 5000000>;
28 brightness-levels = <0 4 8 16 32 64 128 255>;
29 default-brightness-level = <6>;
34 compatible = "simple-bus";
38 reg_sd1_vmmc: sd1_regulator {
39 compatible = "regulator-fixed";
40 regulator-name = "VSD_3V3";
41 regulator-min-microvolt = <3300000>;
42 regulator-max-microvolt = <3300000>;
43 gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>;
49 compatible = "simple-audio-card";
50 simple-audio-card,name = "mx6ul-wm8960";
51 simple-audio-card,format = "i2s";
52 simple-audio-card,bitclock-master = <&dailink_master>;
53 simple-audio-card,frame-master = <&dailink_master>;
54 simple-audio-card,widgets =
55 "Microphone", "Mic Jack",
59 "Headphone", "Headphone Jack";
60 simple-audio-card,routing =
61 "Headphone Jack", "HP_L",
62 "Headphone Jack", "HP_R",
67 "LINPUT1", "Mic Jack",
68 "LINPUT3", "Mic Jack",
69 "RINPUT1", "Mic Jack",
70 "RINPUT2", "Mic Jack";
72 simple-audio-card,cpu {
76 dailink_master: simple-audio-card,codec {
78 clocks = <&clks IMX6UL_CLK_SAI2>;
83 compatible = "innolux,at043tn24";
84 backlight = <&backlight_display>;
88 remote-endpoint = <&display_out>;
95 assigned-clocks = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>;
96 assigned-clock-rates = <786432000>;
100 clock_frequency = <100000>;
101 pinctrl-names = "default";
102 pinctrl-0 = <&pinctrl_i2c2>;
106 #sound-dai-cells = <0>;
107 compatible = "wlf,wm8960";
114 pinctrl-names = "default";
115 pinctrl-0 = <&pinctrl_enet1>;
117 phy-handle = <ðphy0>;
122 pinctrl-names = "default";
123 pinctrl-0 = <&pinctrl_enet2>;
125 phy-handle = <ðphy1>;
129 #address-cells = <1>;
132 ethphy0: ethernet-phy@2 {
134 micrel,led-mode = <1>;
135 clocks = <&clks IMX6UL_CLK_ENET_REF>;
136 clock-names = "rmii-ref";
139 ethphy1: ethernet-phy@1 {
141 micrel,led-mode = <1>;
142 clocks = <&clks IMX6UL_CLK_ENET2_REF>;
143 clock-names = "rmii-ref";
150 pinctrl-names = "default";
151 pinctrl-0 = <&pinctrl_lcdif_dat
152 &pinctrl_lcdif_ctrl>;
156 display_out: endpoint {
157 remote-endpoint = <&panel_in>;
163 pinctrl-names = "default";
164 pinctrl-0 = <&pinctrl_pwm1>;
169 pinctrl-names = "default";
170 pinctrl-0 = <&pinctrl_qspi>;
174 #address-cells = <1>;
176 compatible = "micron,n25q256a";
177 spi-max-frequency = <29000000>;
183 pinctrl-names = "default";
184 pinctrl-0 = <&pinctrl_sai2>;
185 assigned-clocks = <&clks IMX6UL_CLK_SAI2_SEL>,
186 <&clks IMX6UL_CLK_SAI2>;
187 assigned-clock-parents = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>;
188 assigned-clock-rates = <0>, <12288000>;
189 fsl,sai-mclk-direction-output;
198 pinctrl-names = "default";
199 pinctrl-0 = <&pinctrl_tsc>;
200 xnur-gpio = <&gpio1 3 GPIO_ACTIVE_LOW>;
201 measure-delay-time = <0xffff>;
202 pre-charge-time = <0xfff>;
207 pinctrl-names = "default";
208 pinctrl-0 = <&pinctrl_uart1>;
213 pinctrl-names = "default";
214 pinctrl-0 = <&pinctrl_uart2>;
226 disable-over-current;
231 fsl,tx-d-cal = <106>;
235 fsl,tx-d-cal = <106>;
239 pinctrl-names = "default", "state_100mhz", "state_200mhz";
240 pinctrl-0 = <&pinctrl_usdhc1>;
241 pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
242 pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
243 cd-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>;
244 keep-power-in-suspend;
246 vmmc-supply = <®_sd1_vmmc>;
251 pinctrl-names = "default";
252 pinctrl-0 = <&pinctrl_usdhc2>;
254 keep-power-in-suspend;
260 pinctrl-names = "default";
261 pinctrl-0 = <&pinctrl_wdog>;
262 fsl,ext-reset-output;
266 pinctrl-names = "default";
268 pinctrl_csi1: csi1grp {
270 MX6UL_PAD_CSI_MCLK__CSI_MCLK 0x1b088
271 MX6UL_PAD_CSI_PIXCLK__CSI_PIXCLK 0x1b088
272 MX6UL_PAD_CSI_VSYNC__CSI_VSYNC 0x1b088
273 MX6UL_PAD_CSI_HSYNC__CSI_HSYNC 0x1b088
274 MX6UL_PAD_CSI_DATA00__CSI_DATA02 0x1b088
275 MX6UL_PAD_CSI_DATA01__CSI_DATA03 0x1b088
276 MX6UL_PAD_CSI_DATA02__CSI_DATA04 0x1b088
277 MX6UL_PAD_CSI_DATA03__CSI_DATA05 0x1b088
278 MX6UL_PAD_CSI_DATA04__CSI_DATA06 0x1b088
279 MX6UL_PAD_CSI_DATA05__CSI_DATA07 0x1b088
280 MX6UL_PAD_CSI_DATA06__CSI_DATA08 0x1b088
281 MX6UL_PAD_CSI_DATA07__CSI_DATA09 0x1b088
285 pinctrl_enet1: enet1grp {
287 MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0
288 MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x1b0b0
289 MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0
290 MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0
291 MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0
292 MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0
293 MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0
294 MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4001b031
298 pinctrl_enet2: enet2grp {
300 MX6UL_PAD_GPIO1_IO07__ENET2_MDC 0x1b0b0
301 MX6UL_PAD_GPIO1_IO06__ENET2_MDIO 0x1b0b0
302 MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x1b0b0
303 MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER 0x1b0b0
304 MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0
305 MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0
306 MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x1b0b0
307 MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b0b0
308 MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b0b0
309 MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x4001b031
313 pinctrl_flexcan1: flexcan1grp{
315 MX6UL_PAD_UART3_RTS_B__FLEXCAN1_RX 0x1b020
316 MX6UL_PAD_UART3_CTS_B__FLEXCAN1_TX 0x1b020
320 pinctrl_flexcan2: flexcan2grp{
322 MX6UL_PAD_UART2_RTS_B__FLEXCAN2_RX 0x1b020
323 MX6UL_PAD_UART2_CTS_B__FLEXCAN2_TX 0x1b020
327 pinctrl_i2c1: i2c1grp {
329 MX6UL_PAD_UART4_TX_DATA__I2C1_SCL 0x4001b8b0
330 MX6UL_PAD_UART4_RX_DATA__I2C1_SDA 0x4001b8b0
334 pinctrl_i2c2: i2c2grp {
336 MX6UL_PAD_UART5_TX_DATA__I2C2_SCL 0x4001b8b0
337 MX6UL_PAD_UART5_RX_DATA__I2C2_SDA 0x4001b8b0
341 pinctrl_lcdif_dat: lcdifdatgrp {
343 MX6UL_PAD_LCD_DATA00__LCDIF_DATA00 0x79
344 MX6UL_PAD_LCD_DATA01__LCDIF_DATA01 0x79
345 MX6UL_PAD_LCD_DATA02__LCDIF_DATA02 0x79
346 MX6UL_PAD_LCD_DATA03__LCDIF_DATA03 0x79
347 MX6UL_PAD_LCD_DATA04__LCDIF_DATA04 0x79
348 MX6UL_PAD_LCD_DATA05__LCDIF_DATA05 0x79
349 MX6UL_PAD_LCD_DATA06__LCDIF_DATA06 0x79
350 MX6UL_PAD_LCD_DATA07__LCDIF_DATA07 0x79
351 MX6UL_PAD_LCD_DATA08__LCDIF_DATA08 0x79
352 MX6UL_PAD_LCD_DATA09__LCDIF_DATA09 0x79
353 MX6UL_PAD_LCD_DATA10__LCDIF_DATA10 0x79
354 MX6UL_PAD_LCD_DATA11__LCDIF_DATA11 0x79
355 MX6UL_PAD_LCD_DATA12__LCDIF_DATA12 0x79
356 MX6UL_PAD_LCD_DATA13__LCDIF_DATA13 0x79
357 MX6UL_PAD_LCD_DATA14__LCDIF_DATA14 0x79
358 MX6UL_PAD_LCD_DATA15__LCDIF_DATA15 0x79
359 MX6UL_PAD_LCD_DATA16__LCDIF_DATA16 0x79
360 MX6UL_PAD_LCD_DATA17__LCDIF_DATA17 0x79
361 MX6UL_PAD_LCD_DATA18__LCDIF_DATA18 0x79
362 MX6UL_PAD_LCD_DATA19__LCDIF_DATA19 0x79
363 MX6UL_PAD_LCD_DATA20__LCDIF_DATA20 0x79
364 MX6UL_PAD_LCD_DATA21__LCDIF_DATA21 0x79
365 MX6UL_PAD_LCD_DATA22__LCDIF_DATA22 0x79
366 MX6UL_PAD_LCD_DATA23__LCDIF_DATA23 0x79
370 pinctrl_lcdif_ctrl: lcdifctrlgrp {
372 MX6UL_PAD_LCD_CLK__LCDIF_CLK 0x79
373 MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE 0x79
374 MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC 0x79
375 MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC 0x79
376 /* used for lcd reset */
377 MX6UL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x79
381 pinctrl_qspi: qspigrp {
383 MX6UL_PAD_NAND_WP_B__QSPI_A_SCLK 0x70a1
384 MX6UL_PAD_NAND_READY_B__QSPI_A_DATA00 0x70a1
385 MX6UL_PAD_NAND_CE0_B__QSPI_A_DATA01 0x70a1
386 MX6UL_PAD_NAND_CE1_B__QSPI_A_DATA02 0x70a1
387 MX6UL_PAD_NAND_CLE__QSPI_A_DATA03 0x70a1
388 MX6UL_PAD_NAND_DQS__QSPI_A_SS0_B 0x70a1
392 pinctrl_sai2: sai2grp {
394 MX6UL_PAD_JTAG_TDI__SAI2_TX_BCLK 0x17088
395 MX6UL_PAD_JTAG_TDO__SAI2_TX_SYNC 0x17088
396 MX6UL_PAD_JTAG_TRST_B__SAI2_TX_DATA 0x11088
397 MX6UL_PAD_JTAG_TCK__SAI2_RX_DATA 0x11088
398 MX6UL_PAD_JTAG_TMS__SAI2_MCLK 0x17088
399 MX6UL_PAD_SNVS_TAMPER4__GPIO5_IO04 0x17059
403 pinctrl_pwm1: pwm1grp {
405 MX6UL_PAD_GPIO1_IO08__PWM1_OUT 0x110b0
409 pinctrl_sim2: sim2grp {
411 MX6UL_PAD_CSI_DATA03__SIM2_PORT1_PD 0xb808
412 MX6UL_PAD_CSI_DATA04__SIM2_PORT1_CLK 0x31
413 MX6UL_PAD_CSI_DATA05__SIM2_PORT1_RST_B 0xb808
414 MX6UL_PAD_CSI_DATA06__SIM2_PORT1_SVEN 0xb808
415 MX6UL_PAD_CSI_DATA07__SIM2_PORT1_TRXD 0xb809
416 MX6UL_PAD_CSI_DATA02__GPIO4_IO23 0x3008
420 pinctrl_tsc: tscgrp {
422 MX6UL_PAD_GPIO1_IO01__GPIO1_IO01 0xb0
423 MX6UL_PAD_GPIO1_IO02__GPIO1_IO02 0xb0
424 MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0xb0
425 MX6UL_PAD_GPIO1_IO04__GPIO1_IO04 0xb0
429 pinctrl_uart1: uart1grp {
431 MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1
432 MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1
436 pinctrl_uart2: uart2grp {
438 MX6UL_PAD_UART2_TX_DATA__UART2_DCE_TX 0x1b0b1
439 MX6UL_PAD_UART2_RX_DATA__UART2_DCE_RX 0x1b0b1
440 MX6UL_PAD_UART3_RX_DATA__UART2_DCE_RTS 0x1b0b1
441 MX6UL_PAD_UART3_TX_DATA__UART2_DCE_CTS 0x1b0b1
445 pinctrl_usdhc1: usdhc1grp {
447 MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059
448 MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10059
449 MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059
450 MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059
451 MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059
452 MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059
453 MX6UL_PAD_UART1_RTS_B__GPIO1_IO19 0x17059 /* SD1 CD */
454 MX6UL_PAD_GPIO1_IO05__USDHC1_VSELECT 0x17059 /* SD1 VSELECT */
455 MX6UL_PAD_GPIO1_IO09__GPIO1_IO09 0x17059 /* SD1 RESET */
459 pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
461 MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170b9
462 MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100b9
463 MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170b9
464 MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170b9
465 MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170b9
466 MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170b9
471 pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
473 MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170f9
474 MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100f9
475 MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170f9
476 MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170f9
477 MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170f9
478 MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170f9
482 pinctrl_usdhc2: usdhc2grp {
484 MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x17059
485 MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x17059
486 MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x17059
487 MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17059
488 MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17059
489 MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17059
493 pinctrl_wdog: wdoggrp {
495 MX6UL_PAD_LCD_RESET__WDOG1_WDOG_ANY 0x30b0