2 * Copyright 2015 Freescale Semiconductor, Inc.
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
9 #include <dt-bindings/clock/imx6ul-clock.h>
10 #include <dt-bindings/gpio/gpio.h>
11 #include <dt-bindings/input/input.h>
12 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #include "imx6ul-pinfunc.h"
19 * The decompressor and also some bootloaders rely on a
20 * pre-existing /chosen node to be available to insert the
21 * command line and merge other ATAGS info.
22 * Also for U-Boot there must be a pre-existing /memory node.
25 memory { device_type = "memory"; };
65 compatible = "arm,cortex-a7";
68 clock-latency = <61036>; /* two CLK32 periods */
76 fsl,soc-operating-points = <
83 clocks = <&clks IMX6UL_CLK_ARM>,
84 <&clks IMX6UL_CLK_PLL2_BUS>,
85 <&clks IMX6UL_CLK_PLL2_PFD2>,
86 <&clks IMX6UL_CA7_SECONDARY_SEL>,
87 <&clks IMX6UL_CLK_STEP>,
88 <&clks IMX6UL_CLK_PLL1_SW>,
89 <&clks IMX6UL_CLK_PLL1_SYS>;
90 clock-names = "arm", "pll2_bus", "pll2_pfd2_396m",
91 "secondary_sel", "step", "pll1_sw",
93 arm-supply = <®_arm>;
94 soc-supply = <®_soc>;
98 intc: interrupt-controller@a01000 {
99 compatible = "arm,gic-400", "arm,cortex-a7-gic";
100 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
101 #interrupt-cells = <3>;
102 interrupt-controller;
103 interrupt-parent = <&intc>;
104 reg = <0x00a01000 0x1000>,
111 compatible = "arm,armv7-timer";
112 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
113 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
114 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
115 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
116 interrupt-parent = <&intc>;
121 compatible = "fixed-clock";
123 clock-frequency = <32768>;
124 clock-output-names = "ckil";
128 compatible = "fixed-clock";
130 clock-frequency = <24000000>;
131 clock-output-names = "osc";
135 compatible = "fixed-clock";
137 clock-frequency = <0>;
138 clock-output-names = "ipp_di0";
142 compatible = "fixed-clock";
144 clock-frequency = <0>;
145 clock-output-names = "ipp_di1";
149 compatible = "fsl,imx6ul-tempmon", "fsl,imx6sx-tempmon";
150 interrupt-parent = <&gpc>;
151 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
152 fsl,tempmon = <&anatop>;
153 nvmem-cells = <&tempmon_calib>, <&tempmon_temp_grade>;
154 nvmem-cell-names = "calib", "temp_grade";
155 clocks = <&clks IMX6UL_CLK_PLL3_USB_OTG>;
159 compatible = "arm,cortex-a7-pmu";
160 interrupt-parent = <&gpc>;
161 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
166 #address-cells = <1>;
168 compatible = "simple-bus";
169 interrupt-parent = <&gpc>;
173 compatible = "mmio-sram";
174 reg = <0x00900000 0x20000>;
177 dma_apbh: dma-apbh@1804000 {
178 compatible = "fsl,imx6q-dma-apbh", "fsl,imx28-dma-apbh";
179 reg = <0x01804000 0x2000>;
180 interrupts = <0 13 IRQ_TYPE_LEVEL_HIGH>,
181 <0 13 IRQ_TYPE_LEVEL_HIGH>,
182 <0 13 IRQ_TYPE_LEVEL_HIGH>,
183 <0 13 IRQ_TYPE_LEVEL_HIGH>;
184 interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3";
187 clocks = <&clks IMX6UL_CLK_APBHDMA>;
190 gpmi: gpmi-nand@1806000 {
191 compatible = "fsl,imx6q-gpmi-nand";
192 #address-cells = <1>;
194 reg = <0x01806000 0x2000>, <0x01808000 0x2000>;
195 reg-names = "gpmi-nand", "bch";
196 interrupts = <0 15 IRQ_TYPE_LEVEL_HIGH>;
197 interrupt-names = "bch";
198 clocks = <&clks IMX6UL_CLK_GPMI_IO>,
199 <&clks IMX6UL_CLK_GPMI_APB>,
200 <&clks IMX6UL_CLK_GPMI_BCH>,
201 <&clks IMX6UL_CLK_GPMI_BCH_APB>,
202 <&clks IMX6UL_CLK_PER_BCH>;
203 clock-names = "gpmi_io", "gpmi_apb", "gpmi_bch",
204 "gpmi_bch_apb", "per1_bch";
205 dmas = <&dma_apbh 0>;
210 aips1: aips-bus@2000000 {
211 compatible = "fsl,aips-bus", "simple-bus";
212 #address-cells = <1>;
214 reg = <0x02000000 0x100000>;
218 compatible = "fsl,spba-bus", "simple-bus";
219 #address-cells = <1>;
221 reg = <0x02000000 0x40000>;
224 ecspi1: ecspi@2008000 {
225 #address-cells = <1>;
227 compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi";
228 reg = <0x02008000 0x4000>;
229 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
230 clocks = <&clks IMX6UL_CLK_ECSPI1>,
231 <&clks IMX6UL_CLK_ECSPI1>;
232 clock-names = "ipg", "per";
236 ecspi2: ecspi@200c000 {
237 #address-cells = <1>;
239 compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi";
240 reg = <0x0200c000 0x4000>;
241 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
242 clocks = <&clks IMX6UL_CLK_ECSPI2>,
243 <&clks IMX6UL_CLK_ECSPI2>;
244 clock-names = "ipg", "per";
248 ecspi3: ecspi@2010000 {
249 #address-cells = <1>;
251 compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi";
252 reg = <0x02010000 0x4000>;
253 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
254 clocks = <&clks IMX6UL_CLK_ECSPI3>,
255 <&clks IMX6UL_CLK_ECSPI3>;
256 clock-names = "ipg", "per";
260 ecspi4: ecspi@2014000 {
261 #address-cells = <1>;
263 compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi";
264 reg = <0x02014000 0x4000>;
265 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
266 clocks = <&clks IMX6UL_CLK_ECSPI4>,
267 <&clks IMX6UL_CLK_ECSPI4>;
268 clock-names = "ipg", "per";
272 uart7: serial@2018000 {
273 compatible = "fsl,imx6ul-uart",
275 reg = <0x02018000 0x4000>;
276 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
277 clocks = <&clks IMX6UL_CLK_UART7_IPG>,
278 <&clks IMX6UL_CLK_UART7_SERIAL>;
279 clock-names = "ipg", "per";
283 uart1: serial@2020000 {
284 compatible = "fsl,imx6ul-uart",
286 reg = <0x02020000 0x4000>;
287 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
288 clocks = <&clks IMX6UL_CLK_UART1_IPG>,
289 <&clks IMX6UL_CLK_UART1_SERIAL>;
290 clock-names = "ipg", "per";
294 uart8: serial@2024000 {
295 compatible = "fsl,imx6ul-uart",
297 reg = <0x02024000 0x4000>;
298 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
299 clocks = <&clks IMX6UL_CLK_UART8_IPG>,
300 <&clks IMX6UL_CLK_UART8_SERIAL>;
301 clock-names = "ipg", "per";
306 #sound-dai-cells = <0>;
307 compatible = "fsl,imx6ul-sai", "fsl,imx6sx-sai";
308 reg = <0x02028000 0x4000>;
309 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
310 clocks = <&clks IMX6UL_CLK_SAI1_IPG>,
311 <&clks IMX6UL_CLK_SAI1>,
312 <&clks IMX6UL_CLK_DUMMY>, <&clks IMX6UL_CLK_DUMMY>;
313 clock-names = "bus", "mclk1", "mclk2", "mclk3";
314 dmas = <&sdma 35 24 0>,
316 dma-names = "rx", "tx";
321 #sound-dai-cells = <0>;
322 compatible = "fsl,imx6ul-sai", "fsl,imx6sx-sai";
323 reg = <0x0202c000 0x4000>;
324 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
325 clocks = <&clks IMX6UL_CLK_SAI2_IPG>,
326 <&clks IMX6UL_CLK_SAI2>,
327 <&clks IMX6UL_CLK_DUMMY>, <&clks IMX6UL_CLK_DUMMY>;
328 clock-names = "bus", "mclk1", "mclk2", "mclk3";
329 dmas = <&sdma 37 24 0>,
331 dma-names = "rx", "tx";
336 #sound-dai-cells = <0>;
337 compatible = "fsl,imx6ul-sai", "fsl,imx6sx-sai";
338 reg = <0x02030000 0x4000>;
339 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
340 clocks = <&clks IMX6UL_CLK_SAI3_IPG>,
341 <&clks IMX6UL_CLK_SAI3>,
342 <&clks IMX6UL_CLK_DUMMY>, <&clks IMX6UL_CLK_DUMMY>;
343 clock-names = "bus", "mclk1", "mclk2", "mclk3";
344 dmas = <&sdma 39 24 0>,
346 dma-names = "rx", "tx";
352 compatible = "fsl,imx6ul-tsc";
353 reg = <0x02040000 0x4000>, <0x0219c000 0x4000>;
354 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
355 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
356 clocks = <&clks IMX6UL_CLK_IPG>,
357 <&clks IMX6UL_CLK_ADC2>;
358 clock-names = "tsc", "adc";
363 compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
364 reg = <0x02080000 0x4000>;
365 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
366 clocks = <&clks IMX6UL_CLK_PWM1>,
367 <&clks IMX6UL_CLK_PWM1>;
368 clock-names = "ipg", "per";
374 compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
375 reg = <0x02084000 0x4000>;
376 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
377 clocks = <&clks IMX6UL_CLK_PWM2>,
378 <&clks IMX6UL_CLK_PWM2>;
379 clock-names = "ipg", "per";
385 compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
386 reg = <0x02088000 0x4000>;
387 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
388 clocks = <&clks IMX6UL_CLK_PWM3>,
389 <&clks IMX6UL_CLK_PWM3>;
390 clock-names = "ipg", "per";
396 compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
397 reg = <0x0208c000 0x4000>;
398 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
399 clocks = <&clks IMX6UL_CLK_PWM4>,
400 <&clks IMX6UL_CLK_PWM4>;
401 clock-names = "ipg", "per";
406 can1: flexcan@2090000 {
407 compatible = "fsl,imx6ul-flexcan", "fsl,imx6q-flexcan";
408 reg = <0x02090000 0x4000>;
409 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
410 clocks = <&clks IMX6UL_CLK_CAN1_IPG>,
411 <&clks IMX6UL_CLK_CAN1_SERIAL>;
412 clock-names = "ipg", "per";
416 can2: flexcan@2094000 {
417 compatible = "fsl,imx6ul-flexcan", "fsl,imx6q-flexcan";
418 reg = <0x02094000 0x4000>;
419 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
420 clocks = <&clks IMX6UL_CLK_CAN2_IPG>,
421 <&clks IMX6UL_CLK_CAN2_SERIAL>;
422 clock-names = "ipg", "per";
427 compatible = "fsl,imx6ul-gpt", "fsl,imx6sx-gpt";
428 reg = <0x02098000 0x4000>;
429 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
430 clocks = <&clks IMX6UL_CLK_GPT1_BUS>,
431 <&clks IMX6UL_CLK_GPT1_SERIAL>;
432 clock-names = "ipg", "per";
435 gpio1: gpio@209c000 {
436 compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio";
437 reg = <0x0209c000 0x4000>;
438 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
439 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
442 interrupt-controller;
443 #interrupt-cells = <2>;
444 gpio-ranges = <&iomuxc 0 23 10>, <&iomuxc 10 17 6>,
448 gpio2: gpio@20a0000 {
449 compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio";
450 reg = <0x020a0000 0x4000>;
451 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
452 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
455 interrupt-controller;
456 #interrupt-cells = <2>;
457 gpio-ranges = <&iomuxc 0 49 16>, <&iomuxc 16 111 6>;
460 gpio3: gpio@20a4000 {
461 compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio";
462 reg = <0x020a4000 0x4000>;
463 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
464 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
467 interrupt-controller;
468 #interrupt-cells = <2>;
469 gpio-ranges = <&iomuxc 0 65 29>;
472 gpio4: gpio@20a8000 {
473 compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio";
474 reg = <0x020a8000 0x4000>;
475 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
476 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
479 interrupt-controller;
480 #interrupt-cells = <2>;
481 gpio-ranges = <&iomuxc 0 94 17>, <&iomuxc 17 117 12>;
484 gpio5: gpio@20ac000 {
485 compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio";
486 reg = <0x020ac000 0x4000>;
487 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
488 <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
491 interrupt-controller;
492 #interrupt-cells = <2>;
493 gpio-ranges = <&iomuxc 0 7 10>, <&iomuxc 10 5 2>;
496 fec2: ethernet@20b4000 {
497 compatible = "fsl,imx6ul-fec", "fsl,imx6q-fec";
498 reg = <0x020b4000 0x4000>;
499 interrupt-names = "int0", "pps";
500 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
501 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
502 clocks = <&clks IMX6UL_CLK_ENET>,
503 <&clks IMX6UL_CLK_ENET_AHB>,
504 <&clks IMX6UL_CLK_ENET_PTP>,
505 <&clks IMX6UL_CLK_ENET2_REF_125M>,
506 <&clks IMX6UL_CLK_ENET2_REF_125M>;
507 clock-names = "ipg", "ahb", "ptp",
508 "enet_clk_ref", "enet_out";
509 fsl,num-tx-queues=<1>;
510 fsl,num-rx-queues=<1>;
515 compatible = "fsl,imx6ul-kpp", "fsl,imx6q-kpp", "fsl,imx21-kpp";
516 reg = <0x020b8000 0x4000>;
517 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
518 clocks = <&clks IMX6UL_CLK_KPP>;
522 wdog1: wdog@20bc000 {
523 compatible = "fsl,imx6ul-wdt", "fsl,imx21-wdt";
524 reg = <0x020bc000 0x4000>;
525 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
526 clocks = <&clks IMX6UL_CLK_WDOG1>;
529 wdog2: wdog@20c0000 {
530 compatible = "fsl,imx6ul-wdt", "fsl,imx21-wdt";
531 reg = <0x020c0000 0x4000>;
532 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
533 clocks = <&clks IMX6UL_CLK_WDOG2>;
538 compatible = "fsl,imx6ul-ccm";
539 reg = <0x020c4000 0x4000>;
540 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
541 <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
543 clocks = <&ckil>, <&osc>, <&ipp_di0>, <&ipp_di1>;
544 clock-names = "ckil", "osc", "ipp_di0", "ipp_di1";
547 anatop: anatop@20c8000 {
548 compatible = "fsl,imx6ul-anatop", "fsl,imx6q-anatop",
549 "syscon", "simple-bus";
550 reg = <0x020c8000 0x1000>;
551 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
552 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
553 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
554 #address-cells = <1>;
557 reg_3p0: regulator-3p0@20c8110 {
559 compatible = "fsl,anatop-regulator";
560 regulator-name = "vdd3p0";
561 regulator-min-microvolt = <2625000>;
562 regulator-max-microvolt = <3400000>;
563 anatop-reg-offset = <0x120>;
564 anatop-vol-bit-shift = <8>;
565 anatop-vol-bit-width = <5>;
566 anatop-min-bit-val = <0>;
567 anatop-min-voltage = <2625000>;
568 anatop-max-voltage = <3400000>;
569 anatop-enable-bit = <0>;
572 reg_arm: regulator-vddcore@20c8140 {
574 compatible = "fsl,anatop-regulator";
575 regulator-name = "cpu";
576 regulator-min-microvolt = <725000>;
577 regulator-max-microvolt = <1450000>;
579 anatop-reg-offset = <0x140>;
580 anatop-vol-bit-shift = <0>;
581 anatop-vol-bit-width = <5>;
582 anatop-delay-reg-offset = <0x170>;
583 anatop-delay-bit-shift = <24>;
584 anatop-delay-bit-width = <2>;
585 anatop-min-bit-val = <1>;
586 anatop-min-voltage = <725000>;
587 anatop-max-voltage = <1450000>;
590 reg_soc: regulator-vddsoc@20c8140 {
592 compatible = "fsl,anatop-regulator";
593 regulator-name = "vddsoc";
594 regulator-min-microvolt = <725000>;
595 regulator-max-microvolt = <1450000>;
597 anatop-reg-offset = <0x140>;
598 anatop-vol-bit-shift = <18>;
599 anatop-vol-bit-width = <5>;
600 anatop-delay-reg-offset = <0x170>;
601 anatop-delay-bit-shift = <28>;
602 anatop-delay-bit-width = <2>;
603 anatop-min-bit-val = <1>;
604 anatop-min-voltage = <725000>;
605 anatop-max-voltage = <1450000>;
609 usbphy1: usbphy@20c9000 {
610 compatible = "fsl,imx6ul-usbphy", "fsl,imx23-usbphy";
611 reg = <0x020c9000 0x1000>;
612 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
613 clocks = <&clks IMX6UL_CLK_USBPHY1>;
614 phy-3p0-supply = <®_3p0>;
615 fsl,anatop = <&anatop>;
618 usbphy2: usbphy@20ca000 {
619 compatible = "fsl,imx6ul-usbphy", "fsl,imx23-usbphy";
620 reg = <0x020ca000 0x1000>;
621 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
622 clocks = <&clks IMX6UL_CLK_USBPHY2>;
623 phy-3p0-supply = <®_3p0>;
624 fsl,anatop = <&anatop>;
628 compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd";
629 reg = <0x020cc000 0x4000>;
631 snvs_rtc: snvs-rtc-lp {
632 compatible = "fsl,sec-v4.0-mon-rtc-lp";
635 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
636 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
639 snvs_poweroff: snvs-poweroff {
640 compatible = "syscon-poweroff";
648 snvs_pwrkey: snvs-powerkey {
649 compatible = "fsl,sec-v4.0-pwrkey";
651 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
652 linux,keycode = <KEY_POWER>;
656 snvs_lpgpr: snvs-lpgpr {
657 compatible = "fsl,imx6ul-snvs-lpgpr";
661 epit1: epit@20d0000 {
662 reg = <0x020d0000 0x4000>;
663 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
666 epit2: epit@20d4000 {
667 reg = <0x020d4000 0x4000>;
668 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
672 compatible = "fsl,imx6ul-src", "fsl,imx51-src";
673 reg = <0x020d8000 0x4000>;
674 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,
675 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
680 compatible = "fsl,imx6ul-gpc", "fsl,imx6q-gpc";
681 reg = <0x020dc000 0x4000>;
682 interrupt-controller;
683 #interrupt-cells = <3>;
684 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
685 interrupt-parent = <&intc>;
688 iomuxc: iomuxc@20e0000 {
689 compatible = "fsl,imx6ul-iomuxc";
690 reg = <0x020e0000 0x4000>;
693 gpr: iomuxc-gpr@20e4000 {
694 compatible = "fsl,imx6ul-iomuxc-gpr",
695 "fsl,imx6q-iomuxc-gpr", "syscon";
696 reg = <0x020e4000 0x4000>;
700 compatible = "fsl,imx6ul-gpt", "fsl,imx6sx-gpt";
701 reg = <0x020e8000 0x4000>;
702 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
703 clocks = <&clks IMX6UL_CLK_GPT2_BUS>,
704 <&clks IMX6UL_CLK_GPT2_SERIAL>;
705 clock-names = "ipg", "per";
709 compatible = "fsl,imx6ul-sdma", "fsl,imx6q-sdma",
711 reg = <0x020ec000 0x4000>;
712 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
713 clocks = <&clks IMX6UL_CLK_SDMA>,
714 <&clks IMX6UL_CLK_SDMA>;
715 clock-names = "ipg", "ahb";
717 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin";
721 compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
722 reg = <0x020f0000 0x4000>;
723 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
724 clocks = <&clks IMX6UL_CLK_PWM5>,
725 <&clks IMX6UL_CLK_PWM5>;
726 clock-names = "ipg", "per";
732 compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
733 reg = <0x020f4000 0x4000>;
734 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
735 clocks = <&clks IMX6UL_CLK_PWM6>,
736 <&clks IMX6UL_CLK_PWM6>;
737 clock-names = "ipg", "per";
743 compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
744 reg = <0x020f8000 0x4000>;
745 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
746 clocks = <&clks IMX6UL_CLK_PWM7>,
747 <&clks IMX6UL_CLK_PWM7>;
748 clock-names = "ipg", "per";
754 compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
755 reg = <0x020fc000 0x4000>;
756 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
757 clocks = <&clks IMX6UL_CLK_PWM8>,
758 <&clks IMX6UL_CLK_PWM8>;
759 clock-names = "ipg", "per";
765 aips2: aips-bus@2100000 {
766 compatible = "fsl,aips-bus", "simple-bus";
767 #address-cells = <1>;
769 reg = <0x02100000 0x100000>;
772 usbotg1: usb@2184000 {
773 compatible = "fsl,imx6ul-usb", "fsl,imx27-usb";
774 reg = <0x02184000 0x200>;
775 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
776 clocks = <&clks IMX6UL_CLK_USBOH3>;
777 fsl,usbphy = <&usbphy1>;
778 fsl,usbmisc = <&usbmisc 0>;
779 fsl,anatop = <&anatop>;
780 ahb-burst-config = <0x0>;
781 tx-burst-size-dword = <0x10>;
782 rx-burst-size-dword = <0x10>;
786 usbotg2: usb@2184200 {
787 compatible = "fsl,imx6ul-usb", "fsl,imx27-usb";
788 reg = <0x02184200 0x200>;
789 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
790 clocks = <&clks IMX6UL_CLK_USBOH3>;
791 fsl,usbphy = <&usbphy2>;
792 fsl,usbmisc = <&usbmisc 1>;
793 ahb-burst-config = <0x0>;
794 tx-burst-size-dword = <0x10>;
795 rx-burst-size-dword = <0x10>;
799 usbmisc: usbmisc@2184800 {
801 compatible = "fsl,imx6ul-usbmisc", "fsl,imx6q-usbmisc";
802 reg = <0x02184800 0x200>;
805 fec1: ethernet@2188000 {
806 compatible = "fsl,imx6ul-fec", "fsl,imx6q-fec";
807 reg = <0x02188000 0x4000>;
808 interrupt-names = "int0", "pps";
809 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
810 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
811 clocks = <&clks IMX6UL_CLK_ENET>,
812 <&clks IMX6UL_CLK_ENET_AHB>,
813 <&clks IMX6UL_CLK_ENET_PTP>,
814 <&clks IMX6UL_CLK_ENET_REF>,
815 <&clks IMX6UL_CLK_ENET_REF>;
816 clock-names = "ipg", "ahb", "ptp",
817 "enet_clk_ref", "enet_out";
818 fsl,num-tx-queues=<1>;
819 fsl,num-rx-queues=<1>;
823 usdhc1: usdhc@2190000 {
824 compatible = "fsl,imx6ul-usdhc", "fsl,imx6sx-usdhc";
825 reg = <0x02190000 0x4000>;
826 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
827 clocks = <&clks IMX6UL_CLK_USDHC1>,
828 <&clks IMX6UL_CLK_USDHC1>,
829 <&clks IMX6UL_CLK_USDHC1>;
830 clock-names = "ipg", "ahb", "per";
835 usdhc2: usdhc@2194000 {
836 compatible = "fsl,imx6ul-usdhc", "fsl,imx6sx-usdhc";
837 reg = <0x02194000 0x4000>;
838 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
839 clocks = <&clks IMX6UL_CLK_USDHC2>,
840 <&clks IMX6UL_CLK_USDHC2>,
841 <&clks IMX6UL_CLK_USDHC2>;
842 clock-names = "ipg", "ahb", "per";
848 compatible = "fsl,imx6ul-adc", "fsl,vf610-adc";
849 reg = <0x02198000 0x4000>;
850 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
851 clocks = <&clks IMX6UL_CLK_ADC1>;
854 fsl,adck-max-frequency = <30000000>, <40000000>,
860 #address-cells = <1>;
862 compatible = "fsl,imx6ul-i2c", "fsl,imx21-i2c";
863 reg = <0x021a0000 0x4000>;
864 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
865 clocks = <&clks IMX6UL_CLK_I2C1>;
870 #address-cells = <1>;
872 compatible = "fsl,imx6ul-i2c", "fsl,imx21-i2c";
873 reg = <0x021a4000 0x4000>;
874 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
875 clocks = <&clks IMX6UL_CLK_I2C2>;
880 #address-cells = <1>;
882 compatible = "fsl,imx6ul-i2c", "fsl,imx21-i2c";
883 reg = <0x021a8000 0x4000>;
884 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
885 clocks = <&clks IMX6UL_CLK_I2C3>;
890 compatible = "fsl,imx6ul-mmdc", "fsl,imx6q-mmdc";
891 reg = <0x021b0000 0x4000>;
894 ocotp: ocotp-ctrl@21bc000 {
895 #address-cells = <1>;
897 compatible = "fsl,imx6ul-ocotp", "syscon";
898 reg = <0x021bc000 0x4000>;
899 clocks = <&clks IMX6UL_CLK_OCOTP>;
901 tempmon_calib: calib@38 {
905 tempmon_temp_grade: temp-grade@20 {
910 lcdif: lcdif@21c8000 {
911 compatible = "fsl,imx6ul-lcdif", "fsl,imx28-lcdif";
912 reg = <0x021c8000 0x4000>;
913 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
914 clocks = <&clks IMX6UL_CLK_LCDIF_PIX>,
915 <&clks IMX6UL_CLK_LCDIF_APB>,
916 <&clks IMX6UL_CLK_DUMMY>;
917 clock-names = "pix", "axi", "disp_axi";
922 #address-cells = <1>;
924 compatible = "fsl,imx6ul-qspi", "fsl,imx6sx-qspi";
925 reg = <0x021e0000 0x4000>, <0x60000000 0x10000000>;
926 reg-names = "QuadSPI", "QuadSPI-memory";
927 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
928 clocks = <&clks IMX6UL_CLK_QSPI>,
929 <&clks IMX6UL_CLK_QSPI>;
930 clock-names = "qspi_en", "qspi";
934 wdog3: wdog@21e4000 {
935 compatible = "fsl,imx6ul-wdt", "fsl,imx21-wdt";
936 reg = <0x021e4000 0x4000>;
937 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
938 clocks = <&clks IMX6UL_CLK_WDOG3>;
942 uart2: serial@21e8000 {
943 compatible = "fsl,imx6ul-uart",
945 reg = <0x021e8000 0x4000>;
946 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
947 clocks = <&clks IMX6UL_CLK_UART2_IPG>,
948 <&clks IMX6UL_CLK_UART2_SERIAL>;
949 clock-names = "ipg", "per";
953 uart3: serial@21ec000 {
954 compatible = "fsl,imx6ul-uart",
956 reg = <0x021ec000 0x4000>;
957 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
958 clocks = <&clks IMX6UL_CLK_UART3_IPG>,
959 <&clks IMX6UL_CLK_UART3_SERIAL>;
960 clock-names = "ipg", "per";
964 uart4: serial@21f0000 {
965 compatible = "fsl,imx6ul-uart",
967 reg = <0x021f0000 0x4000>;
968 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
969 clocks = <&clks IMX6UL_CLK_UART4_IPG>,
970 <&clks IMX6UL_CLK_UART4_SERIAL>;
971 clock-names = "ipg", "per";
975 uart5: serial@21f4000 {
976 compatible = "fsl,imx6ul-uart",
978 reg = <0x021f4000 0x4000>;
979 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
980 clocks = <&clks IMX6UL_CLK_UART5_IPG>,
981 <&clks IMX6UL_CLK_UART5_SERIAL>;
982 clock-names = "ipg", "per";
987 #address-cells = <1>;
989 compatible = "fsl,imx6ul-i2c", "fsl,imx21-i2c";
990 reg = <0x021f8000 0x4000>;
991 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
992 clocks = <&clks IMX6UL_CLK_I2C4>;
996 uart6: serial@21fc000 {
997 compatible = "fsl,imx6ul-uart",
999 reg = <0x021fc000 0x4000>;
1000 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
1001 clocks = <&clks IMX6UL_CLK_UART6_IPG>,
1002 <&clks IMX6UL_CLK_UART6_SERIAL>;
1003 clock-names = "ipg", "per";
1004 status = "disabled";