sys/gnu/dts/arm/imx7d-nitrogen7.dts

   1 // SPDX-License-Identifier: GPL-2.0 OR X11
   2 /*
   3  * Copyright 2016 Boundary Devices, Inc.
   4  */
   5
   6 /dts-v1/;
   7
   8 #include "imx7d.dtsi"
   9
  10 / {
  11         model = "Boundary Devices i.MX7 Nitrogen7 Board";
  12         compatible = "boundary,imx7d-nitrogen7", "fsl,imx7d";
  13
  14         memory@80000000 {
  15                 reg = <0x80000000 0x40000000>;
  16         };
  17
  18         backlight-j9 {
  19                 compatible = "gpio-backlight";
  20                 pinctrl-names = "default";
  21                 pinctrl-0 = <&pinctrl_backlight_j9>;
  22                 gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>;
  23                 default-on;
  24         };
  25
  26         backlight_lcd: backlight-j20 {
  27                 compatible = "pwm-backlight";
  28                 pwms = <&pwm1 0 5000000 0>;
  29                 brightness-levels = <0 4 8 16 32 64 128 255>;
  30                 default-brightness-level = <6>;
  31                 status = "okay";
  32         };
  33
  34         panel-lcd {
  35                 compatible = "okaya,rs800480t-7x0gp";
  36                 backlight = <&backlight_lcd>;
  37
  38                 port {
  39                         panel_in: endpoint {
  40                                 remote-endpoint = <&lcdif_out>;
  41                         };
  42                 };
  43         };
  44
  45         reg_usb_otg1_vbus: regulator-usb-otg1-vbus {
  46                 compatible = "regulator-fixed";
  47                 regulator-name = "usb_otg1_vbus";
  48                 regulator-min-microvolt = <5000000>;
  49                 regulator-max-microvolt = <5000000>;
  50                 gpio = <&gpio1 5 GPIO_ACTIVE_HIGH>;
  51                 enable-active-high;
  52         };
  53
  54         reg_usb_otg2_vbus: regulator-usb-otg2-vbus {
  55                 compatible = "regulator-fixed";
  56                 regulator-name = "usb_otg2_vbus";
  57                 regulator-min-microvolt = <5000000>;
  58                 regulator-max-microvolt = <5000000>;
  59                 gpio = <&gpio4 7 GPIO_ACTIVE_HIGH>;
  60                 enable-active-high;
  61         };
  62
  63         reg_can2_3v3: regulator-can2-3v3 {
  64                 compatible = "regulator-fixed";
  65                 regulator-name = "can2-3v3";
  66                 regulator-min-microvolt = <3300000>;
  67                 regulator-max-microvolt = <3300000>;
  68                 gpio = <&gpio2 14 GPIO_ACTIVE_LOW>;
  69         };
  70
  71         reg_vref_1v8: regulator-vref-1v8 {
  72                 compatible = "regulator-fixed";
  73                 regulator-name = "vref-1v8";
  74                 regulator-min-microvolt = <1800000>;
  75                 regulator-max-microvolt = <1800000>;
  76         };
  77
  78         reg_vref_3v3: regulator-vref-3v3 {
  79                 compatible = "regulator-fixed";
  80                 regulator-name = "vref-3v3";
  81                 regulator-min-microvolt = <3300000>;
  82                 regulator-max-microvolt = <3300000>;
  83         };
  84
  85         reg_wlan: regulator-wlan {
  86                 compatible = "regulator-fixed";
  87                 regulator-min-microvolt = <3300000>;
  88                 regulator-max-microvolt = <3300000>;
  89                 regulator-name = "reg_wlan";
  90                 startup-delay-us = <70000>;
  91                 gpio = <&gpio4 21 GPIO_ACTIVE_HIGH>;
  92                 enable-active-high;
  93         };
  94
  95         usdhc2_pwrseq: usdhc2_pwrseq {
  96                 compatible = "mmc-pwrseq-simple";
  97                 clocks = <&clks IMX7D_CLKO2_ROOT_DIV>;
  98                 clock-names = "ext_clock";
  99         };
 100 };
 101
 102 &adc1 {
 103         vref-supply = <&reg_vref_1v8>;
 104         status = "okay";
 105 };
 106
 107 &adc2 {
 108         vref-supply = <&reg_vref_1v8>;
 109         status = "okay";
 110 };
 111
 112 &clks {
 113         assigned-clocks = <&clks IMX7D_CLKO2_ROOT_SRC>,
 114                           <&clks IMX7D_CLKO2_ROOT_DIV>;
 115         assigned-clock-parents = <&clks IMX7D_CKIL>;
 116         assigned-clock-rates = <0>, <32768>;
 117 };
 118
 119 &cpu0 {
 120         cpu-supply = <&sw1a_reg>;
 121 };
 122
 123 &fec1 {
 124         pinctrl-names = "default";
 125         pinctrl-0 = <&pinctrl_enet1>;
 126         assigned-clocks = <&clks IMX7D_ENET1_TIME_ROOT_SRC>,
 127                           <&clks IMX7D_ENET1_TIME_ROOT_CLK>;
 128         assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
 129         assigned-clock-rates = <0>, <100000000>;
 130         phy-mode = "rgmii";
 131         phy-handle = <&ethphy0>;
 132         fsl,magic-packet;
 133         status = "okay";
 134
 135         mdio {
 136                 #address-cells = <1>;
 137                 #size-cells = <0>;
 138
 139                 ethphy0: ethernet-phy@4 {
 140                         reg = <4>;
 141                 };
 142         };
 143 };
 144
 145 &flexcan2 {
 146         pinctrl-names = "default";
 147         pinctrl-0 = <&pinctrl_flexcan2>;
 148         xceiver-supply = <&reg_can2_3v3>;
 149         status = "okay";
 150 };
 151
 152 &i2c1 {
 153         pinctrl-names = "default";
 154         pinctrl-0 = <&pinctrl_i2c1>;
 155         status = "okay";
 156
 157         pmic: pfuze3000@8 {
 158                 compatible = "fsl,pfuze3000";
 159                 reg = <0x08>;
 160
 161                 regulators {
 162                         sw1a_reg: sw1a {
 163                                 regulator-min-microvolt = <700000>;
 164                                 regulator-max-microvolt = <1475000>;
 165                                 regulator-boot-on;
 166                                 regulator-always-on;
 167                                 regulator-ramp-delay = <6250>;
 168                         };
 169
 170                         /* use sw1c_reg to align with pfuze100/pfuze200 */
 171                         sw1c_reg: sw1b {
 172                                 regulator-min-microvolt = <700000>;
 173                                 regulator-max-microvolt = <1475000>;
 174                                 regulator-boot-on;
 175                                 regulator-always-on;
 176                                 regulator-ramp-delay = <6250>;
 177                         };
 178
 179                         sw2_reg: sw2 {
 180                                 regulator-min-microvolt = <1500000>;
 181                                 regulator-max-microvolt = <1850000>;
 182                                 regulator-boot-on;
 183                                 regulator-always-on;
 184                         };
 185
 186                         sw3a_reg: sw3 {
 187                                 regulator-min-microvolt = <900000>;
 188                                 regulator-max-microvolt = <1650000>;
 189                                 regulator-boot-on;
 190                                 regulator-always-on;
 191                         };
 192
 193                         swbst_reg: swbst {
 194                                 regulator-min-microvolt = <5000000>;
 195                                 regulator-max-microvolt = <5150000>;
 196                         };
 197
 198                         snvs_reg: vsnvs {
 199                                 regulator-min-microvolt = <1000000>;
 200                                 regulator-max-microvolt = <3000000>;
 201                                 regulator-boot-on;
 202                                 regulator-always-on;
 203                         };
 204
 205                         vref_reg: vrefddr {
 206                                 regulator-boot-on;
 207                                 regulator-always-on;
 208                         };
 209
 210                         vgen1_reg: vldo1 {
 211                                 regulator-min-microvolt = <1800000>;
 212                                 regulator-max-microvolt = <3300000>;
 213                                 regulator-always-on;
 214                         };
 215
 216                         vgen2_reg: vldo2 {
 217                                 regulator-min-microvolt = <800000>;
 218                                 regulator-max-microvolt = <1550000>;
 219                                 regulator-always-on;
 220                         };
 221
 222                         vgen3_reg: vccsd {
 223                                 regulator-min-microvolt = <2850000>;
 224                                 regulator-max-microvolt = <3300000>;
 225                                 regulator-always-on;
 226                         };
 227
 228                         vgen4_reg: v33 {
 229                                 regulator-min-microvolt = <2850000>;
 230                                 regulator-max-microvolt = <3300000>;
 231                                 regulator-always-on;
 232                         };
 233
 234                         vgen5_reg: vldo3 {
 235                                 regulator-min-microvolt = <1800000>;
 236                                 regulator-max-microvolt = <3300000>;
 237                                 regulator-always-on;
 238                         };
 239
 240                         vgen6_reg: vldo4 {
 241                                 regulator-min-microvolt = <1800000>;
 242                                 regulator-max-microvolt = <3300000>;
 243                                 regulator-always-on;
 244                         };
 245                 };
 246         };
 247 };
 248
 249 &i2c2 {
 250         pinctrl-names = "default";
 251         pinctrl-0 = <&pinctrl_i2c2>;
 252         status = "okay";
 253
 254         rtc@68 {
 255                 compatible = "microcrystal,rv4162";
 256                 pinctrl-names = "default";
 257                 pinctrl-0 = <&pinctrl_i2c2_rv4162>;
 258                 reg = <0x68>;
 259                 interrupts-extended = <&gpio2 15 IRQ_TYPE_LEVEL_LOW>;
 260         };
 261 };
 262
 263 &i2c3 {
 264         pinctrl-names = "default";
 265         pinctrl-0 = <&pinctrl_i2c3>;
 266         status = "okay";
 267
 268         touch@48 {
 269                 compatible = "ti,tsc2004";
 270                 reg = <0x48>;
 271                 pinctrl-names = "default";
 272                 pinctrl-0 = <&pinctrl_i2c3_tsc2004>;
 273                 interrupts-extended = <&gpio3 4 IRQ_TYPE_EDGE_FALLING>;
 274                 wakeup-gpios = <&gpio3 4 GPIO_ACTIVE_LOW>;
 275         };
 276 };
 277
 278 &i2c4 {
 279         pinctrl-names = "default";
 280         pinctrl-0 = <&pinctrl_i2c4>;
 281         status = "okay";
 282
 283         codec: wm8960@1a {
 284                 compatible = "wlf,wm8960";
 285                 reg = <0x1a>;
 286                 clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_CLK>;
 287                 clock-names = "mclk";
 288                 wlf,shared-lrclk;
 289         };
 290 };
 291
 292 &lcdif {
 293         status = "okay";
 294
 295         port {
 296                 lcdif_out: endpoint {
 297                         remote-endpoint = <&panel_in>;
 298                 };
 299         };
 300 };
 301
 302 &pwm1 {
 303         pinctrl-names = "default";
 304         pinctrl-0 = <&pinctrl_pwm1>;
 305         status = "okay";
 306 };
 307
 308 &pwm2 {
 309         pinctrl-names = "default";
 310         pinctrl-0 = <&pinctrl_pwm2>;
 311         status = "okay";
 312 };
 313
 314 &uart1 {
 315         pinctrl-names = "default";
 316         pinctrl-0 = <&pinctrl_uart1>;
 317         assigned-clocks = <&clks IMX7D_UART1_ROOT_SRC>;
 318         assigned-clock-parents = <&clks IMX7D_OSC_24M_CLK>;
 319         status = "okay";
 320 };
 321
 322 &uart2 {
 323         pinctrl-names = "default";
 324         pinctrl-0 = <&pinctrl_uart2>;
 325         assigned-clocks = <&clks IMX7D_UART2_ROOT_SRC>;
 326         assigned-clock-parents = <&clks IMX7D_OSC_24M_CLK>;
 327         status = "okay";
 328 };
 329
 330 &uart3 {
 331         pinctrl-names = "default";
 332         pinctrl-0 = <&pinctrl_uart3>;
 333         assigned-clocks = <&clks IMX7D_UART3_ROOT_SRC>;
 334         assigned-clock-parents = <&clks IMX7D_OSC_24M_CLK>;
 335         status = "okay";
 336 };
 337
 338 &uart6 {
 339         pinctrl-names = "default";
 340         pinctrl-0 = <&pinctrl_uart6>;
 341         assigned-clocks = <&clks IMX7D_UART6_ROOT_SRC>;
 342         assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>;
 343         uart-has-rtscts;
 344         status = "okay";
 345 };
 346
 347 &usbotg1 {
 348         vbus-supply = <&reg_usb_otg1_vbus>;
 349         pinctrl-names = "default";
 350         pinctrl-0 = <&pinctrl_usbotg1>;
 351         status = "okay";
 352 };
 353
 354 &usbotg2 {
 355         vbus-supply = <&reg_usb_otg2_vbus>;
 356         pinctrl-names = "default";
 357         pinctrl-0 = <&pinctrl_usbotg2>;
 358         dr_mode = "host";
 359         status = "okay";
 360 };
 361
 362 &usdhc1 {
 363         pinctrl-names = "default";
 364         pinctrl-0 = <&pinctrl_usdhc1>;
 365         cd-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>;
 366         vmmc-supply = <&vgen3_reg>;
 367         bus-width = <4>;
 368         fsl,tuning-step = <2>;
 369         wakeup-source;
 370         keep-power-in-suspend;
 371         status = "okay";
 372 };
 373
 374 &usdhc2 {
 375         #address-cells = <1>;
 376         #size-cells = <0>;
 377         pinctrl-names = "default";
 378         pinctrl-0 = <&pinctrl_usdhc2>;
 379         bus-width = <4>;
 380         non-removable;
 381         vmmc-supply = <&reg_wlan>;
 382         mmc-pwrseq = <&usdhc2_pwrseq>;
 383         cap-power-off-card;
 384         keep-power-in-suspend;
 385         status = "okay";
 386
 387         wlcore: wlcore@2 {
 388                 compatible = "ti,wl1271";
 389                 reg = <2>;
 390                 interrupt-parent = <&gpio4>;
 391                 interrupts = <20 IRQ_TYPE_LEVEL_HIGH>;
 392                 ref-clock-frequency = <38400000>;
 393         };
 394 };
 395
 396 &usdhc3 {
 397         pinctrl-names = "default";
 398         pinctrl-0 = <&pinctrl_usdhc3>;
 399         assigned-clocks = <&clks IMX7D_USDHC3_ROOT_CLK>;
 400         assigned-clock-rates = <400000000>;
 401         bus-width = <8>;
 402         fsl,tuning-step = <2>;
 403         non-removable;
 404         status = "okay";
 405 };
 406
 407 &wdog1 {
 408         pinctrl-names = "default";
 409         pinctrl-0 = <&pinctrl_wdog1>;
 410         status = "okay";
 411 };
 412
 413 &iomuxc {
 414         pinctrl-names = "default";
 415         pinctrl-0 = <&pinctrl_hog_1 &pinctrl_j2>;
 416
 417         pinctrl_hog_1: hoggrp-1 {
 418                 fsl,pins = <
 419                         MX7D_PAD_SD3_RESET_B__GPIO6_IO11        0x5d
 420                         MX7D_PAD_GPIO1_IO13__GPIO1_IO13         0x7d
 421                         MX7D_PAD_ECSPI2_MISO__GPIO4_IO22        0x7d
 422                 >;
 423         };
 424
 425         pinctrl_enet1: enet1grp {
 426                 fsl,pins = <
 427                         MX7D_PAD_GPIO1_IO10__ENET1_MDIO                 0x3
 428                         MX7D_PAD_GPIO1_IO11__ENET1_MDC                  0x3
 429                         MX7D_PAD_GPIO1_IO12__CCM_ENET_REF_CLK1          0x3
 430                         MX7D_PAD_ENET1_RGMII_TXC__ENET1_RGMII_TXC       0x71
 431                         MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0       0x71
 432                         MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1       0x71
 433                         MX7D_PAD_ENET1_RGMII_TD2__ENET1_RGMII_TD2       0x71
 434                         MX7D_PAD_ENET1_RGMII_TD3__ENET1_RGMII_TD3       0x71
 435                         MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL 0x71
 436                         MX7D_PAD_ENET1_RGMII_RXC__ENET1_RGMII_RXC       0x71
 437                         MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0       0x11
 438                         MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1       0x11
 439                         MX7D_PAD_ENET1_RGMII_RD2__ENET1_RGMII_RD2       0x11
 440                         MX7D_PAD_ENET1_RGMII_RD3__ENET1_RGMII_RD3       0x71
 441                         MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL 0x11
 442                         MX7D_PAD_SD3_STROBE__GPIO6_IO10                 0x75
 443                 >;
 444         };
 445
 446         pinctrl_flexcan2: flexcan2grp {
 447                 fsl,pins = <
 448                         MX7D_PAD_GPIO1_IO14__FLEXCAN2_RX        0x7d
 449                         MX7D_PAD_GPIO1_IO15__FLEXCAN2_TX        0x7d
 450                         MX7D_PAD_EPDC_DATA14__GPIO2_IO14        0x7d
 451                 >;
 452         };
 453
 454         pinctrl_i2c1: i2c1grp {
 455                 fsl,pins = <
 456                         MX7D_PAD_I2C1_SDA__I2C1_SDA             0x4000007f
 457                         MX7D_PAD_I2C1_SCL__I2C1_SCL             0x4000007f
 458                 >;
 459         };
 460
 461         pinctrl_i2c2: i2c2grp {
 462                 fsl,pins = <
 463                         MX7D_PAD_I2C2_SDA__I2C2_SDA             0x4000007f
 464                         MX7D_PAD_I2C2_SCL__I2C2_SCL             0x4000007f
 465                 >;
 466         };
 467
 468         pinctrl_i2c2_rv4162: i2c2-rv4162grp {
 469                 fsl,pins = <
 470                         MX7D_PAD_EPDC_DATA15__GPIO2_IO15        0x7d
 471                 >;
 472         };
 473
 474         pinctrl_i2c3: i2c3grp {
 475                 fsl,pins = <
 476                         MX7D_PAD_I2C3_SDA__I2C3_SDA             0x4000007f
 477                         MX7D_PAD_I2C3_SCL__I2C3_SCL             0x4000007f
 478                 >;
 479         };
 480
 481         pinctrl_i2c3_tsc2004: i2c3tsc2004grp {
 482                 fsl,pins = <
 483                         MX7D_PAD_LCD_RESET__GPIO3_IO4           0x79
 484                         MX7D_PAD_SD2_WP__GPIO5_IO10             0x7d
 485                 >;
 486         };
 487
 488         pinctrl_i2c4: i2c4grp {
 489                 fsl,pins = <
 490                         MX7D_PAD_I2C4_SDA__I2C4_SDA             0x4000007f
 491                         MX7D_PAD_I2C4_SCL__I2C4_SCL             0x4000007f
 492                 >;
 493         };
 494
 495         pinctrl_j2: j2grp {
 496                 fsl,pins = <
 497                         MX7D_PAD_SAI1_TX_DATA__GPIO6_IO15       0x7d
 498                         MX7D_PAD_EPDC_BDR0__GPIO2_IO28          0x7d
 499                         MX7D_PAD_SAI1_RX_DATA__GPIO6_IO12       0x7d
 500                         MX7D_PAD_EPDC_BDR1__GPIO2_IO29          0x7d
 501                         MX7D_PAD_SD1_WP__GPIO5_IO1              0x7d
 502                         MX7D_PAD_EPDC_SDSHR__GPIO2_IO19         0x7d
 503                         MX7D_PAD_SD1_RESET_B__GPIO5_IO2         0x7d
 504                         MX7D_PAD_SD2_RESET_B__GPIO5_IO11        0x7d
 505                         MX7D_PAD_EPDC_DATA07__GPIO2_IO7         0x7d
 506                         MX7D_PAD_EPDC_DATA08__GPIO2_IO8         0x7d
 507                         MX7D_PAD_EPDC_DATA09__GPIO2_IO9         0x7d
 508                         MX7D_PAD_EPDC_DATA10__GPIO2_IO10        0x7d
 509                         MX7D_PAD_EPDC_DATA11__GPIO2_IO11        0x7d
 510                         MX7D_PAD_EPDC_DATA12__GPIO2_IO12        0x7d
 511                         MX7D_PAD_SAI1_TX_SYNC__GPIO6_IO14       0x7d
 512                         MX7D_PAD_EPDC_DATA13__GPIO2_IO13        0x7d
 513                         MX7D_PAD_SAI1_TX_BCLK__GPIO6_IO13       0x7d
 514                         MX7D_PAD_SD2_CD_B__GPIO5_IO9            0x7d
 515                         MX7D_PAD_EPDC_GDCLK__GPIO2_IO24         0x7d
 516                         MX7D_PAD_SAI2_RX_DATA__GPIO6_IO21       0x7d
 517                         MX7D_PAD_EPDC_GDOE__GPIO2_IO25          0x7d
 518                         MX7D_PAD_EPDC_GDRL__GPIO2_IO26          0x7d
 519                         MX7D_PAD_SAI2_TX_DATA__GPIO6_IO22       0x7d
 520                         MX7D_PAD_EPDC_SDCE0__GPIO2_IO20         0x7d
 521                         MX7D_PAD_SAI2_TX_BCLK__GPIO6_IO20       0x7d
 522                         MX7D_PAD_EPDC_SDCE1__GPIO2_IO21         0x7d
 523                         MX7D_PAD_SAI2_TX_SYNC__GPIO6_IO19       0x7d
 524                         MX7D_PAD_EPDC_SDCE2__GPIO2_IO22         0x7d
 525                         MX7D_PAD_EPDC_SDCE3__GPIO2_IO23         0x7d
 526                         MX7D_PAD_EPDC_GDSP__GPIO2_IO27          0x7d
 527                         MX7D_PAD_EPDC_SDCLK__GPIO2_IO16         0x7d
 528                         MX7D_PAD_EPDC_SDLE__GPIO2_IO17          0x7d
 529                         MX7D_PAD_EPDC_SDOE__GPIO2_IO18          0x7d
 530                         MX7D_PAD_EPDC_PWR_COM__GPIO2_IO30       0x7d
 531                         MX7D_PAD_EPDC_PWR_STAT__GPIO2_IO31      0x7d
 532                 >;
 533         };
 534
 535         pinctrl_lcdif_dat: lcdifdatgrp {
 536                 fsl,pins = <
 537                         MX7D_PAD_LCD_DATA00__LCD_DATA0          0x79
 538                         MX7D_PAD_LCD_DATA01__LCD_DATA1          0x79
 539                         MX7D_PAD_LCD_DATA02__LCD_DATA2          0x79
 540                         MX7D_PAD_LCD_DATA03__LCD_DATA3          0x79
 541                         MX7D_PAD_LCD_DATA04__LCD_DATA4          0x79
 542                         MX7D_PAD_LCD_DATA05__LCD_DATA5          0x79
 543                         MX7D_PAD_LCD_DATA06__LCD_DATA6          0x79
 544                         MX7D_PAD_LCD_DATA07__LCD_DATA7          0x79
 545                         MX7D_PAD_LCD_DATA08__LCD_DATA8          0x79
 546                         MX7D_PAD_LCD_DATA09__LCD_DATA9          0x79
 547                         MX7D_PAD_LCD_DATA10__LCD_DATA10         0x79
 548                         MX7D_PAD_LCD_DATA11__LCD_DATA11         0x79
 549                         MX7D_PAD_LCD_DATA12__LCD_DATA12         0x79
 550                         MX7D_PAD_LCD_DATA13__LCD_DATA13         0x79
 551                         MX7D_PAD_LCD_DATA14__LCD_DATA14         0x79
 552                         MX7D_PAD_LCD_DATA15__LCD_DATA15         0x79
 553                         MX7D_PAD_LCD_DATA16__LCD_DATA16         0x79
 554                         MX7D_PAD_LCD_DATA17__LCD_DATA17         0x79
 555                         MX7D_PAD_LCD_DATA18__LCD_DATA18         0x79
 556                         MX7D_PAD_LCD_DATA19__LCD_DATA19         0x79
 557                         MX7D_PAD_LCD_DATA20__LCD_DATA20         0x79
 558                         MX7D_PAD_LCD_DATA21__LCD_DATA21         0x79
 559                         MX7D_PAD_LCD_DATA22__LCD_DATA22         0x79
 560                         MX7D_PAD_LCD_DATA23__LCD_DATA23         0x79
 561                 >;
 562         };
 563
 564         pinctrl_lcdif_ctrl: lcdifctrlgrp {
 565                 fsl,pins = <
 566                         MX7D_PAD_LCD_CLK__LCD_CLK               0x79
 567                         MX7D_PAD_LCD_ENABLE__LCD_ENABLE         0x79
 568                         MX7D_PAD_LCD_VSYNC__LCD_VSYNC           0x79
 569                         MX7D_PAD_LCD_HSYNC__LCD_HSYNC           0x79
 570                 >;
 571         };
 572
 573         pinctrl_pwm2: pwm2grp {
 574                 fsl,pins = <
 575                         MX7D_PAD_GPIO1_IO09__PWM2_OUT           0x7d
 576                 >;
 577         };
 578
 579         pinctrl_uart1: uart1grp {
 580                 fsl,pins = <
 581                         MX7D_PAD_UART1_TX_DATA__UART1_DCE_TX    0x79
 582                         MX7D_PAD_UART1_RX_DATA__UART1_DCE_RX    0x79
 583                 >;
 584         };
 585
 586         pinctrl_uart2: uart2grp {
 587                 fsl,pins = <
 588                         MX7D_PAD_UART2_TX_DATA__UART2_DCE_TX    0x79
 589                         MX7D_PAD_UART2_RX_DATA__UART2_DCE_RX    0x79
 590                 >;
 591         };
 592
 593         pinctrl_uart3: uart3grp {
 594                 fsl,pins = <
 595                         MX7D_PAD_UART3_TX_DATA__UART3_DCE_TX    0x79
 596                         MX7D_PAD_UART3_RX_DATA__UART3_DCE_RX    0x79
 597                         MX7D_PAD_EPDC_DATA04__GPIO2_IO4         0x7d
 598                 >;
 599         };
 600
 601         pinctrl_uart6: uart6grp {
 602                 fsl,pins = <
 603                         MX7D_PAD_ECSPI1_MOSI__UART6_DCE_TX      0x79
 604                         MX7D_PAD_ECSPI1_SCLK__UART6_DCE_RX      0x79
 605                         MX7D_PAD_ECSPI1_SS0__UART6_DCE_CTS      0x79
 606                         MX7D_PAD_ECSPI1_MISO__UART6_DCE_RTS     0x79
 607                 >;
 608         };
 609
 610         pinctrl_usbotg2: usbotg2grp {
 611                 fsl,pins = <
 612                         MX7D_PAD_UART3_RTS_B__USB_OTG2_OC       0x7d
 613                         MX7D_PAD_UART3_CTS_B__GPIO4_IO7         0x14
 614                 >;
 615         };
 616
 617         pinctrl_usdhc1: usdhc1grp {
 618                 fsl,pins = <
 619                         MX7D_PAD_SD1_CMD__SD1_CMD               0x59
 620                         MX7D_PAD_SD1_CLK__SD1_CLK               0x19
 621                         MX7D_PAD_SD1_DATA0__SD1_DATA0           0x59
 622                         MX7D_PAD_SD1_DATA1__SD1_DATA1           0x59
 623                         MX7D_PAD_SD1_DATA2__SD1_DATA2           0x59
 624                         MX7D_PAD_SD1_DATA3__SD1_DATA3           0x59
 625                         MX7D_PAD_GPIO1_IO08__SD1_VSELECT        0x75
 626                         MX7D_PAD_SD1_CD_B__GPIO5_IO0            0x75
 627                 >;
 628         };
 629
 630         pinctrl_usdhc2: usdhc2grp {
 631                 fsl,pins = <
 632                         MX7D_PAD_SD2_CMD__SD2_CMD               0x59
 633                         MX7D_PAD_SD2_CLK__SD2_CLK               0x19
 634                         MX7D_PAD_SD2_DATA0__SD2_DATA0           0x59
 635                         MX7D_PAD_SD2_DATA1__SD2_DATA1           0x59
 636                         MX7D_PAD_SD2_DATA2__SD2_DATA2           0x59
 637                         MX7D_PAD_SD2_DATA3__SD2_DATA3           0x59
 638                         MX7D_PAD_ECSPI2_SCLK__GPIO4_IO20        0x59
 639                         MX7D_PAD_ECSPI2_MOSI__GPIO4_IO21        0x59
 640                 >;
 641         };
 642
 643         pinctrl_usdhc3: usdhc3grp {
 644                 fsl,pins = <
 645                         MX7D_PAD_SD3_CMD__SD3_CMD               0x59
 646                         MX7D_PAD_SD3_CLK__SD3_CLK               0x19
 647                         MX7D_PAD_SD3_DATA0__SD3_DATA0           0x59
 648                         MX7D_PAD_SD3_DATA1__SD3_DATA1           0x59
 649                         MX7D_PAD_SD3_DATA2__SD3_DATA2           0x59
 650                         MX7D_PAD_SD3_DATA3__SD3_DATA3           0x59
 651                         MX7D_PAD_SD3_DATA4__SD3_DATA4           0x59
 652                         MX7D_PAD_SD3_DATA5__SD3_DATA5           0x59
 653                         MX7D_PAD_SD3_DATA6__SD3_DATA6           0x59
 654                         MX7D_PAD_SD3_DATA7__SD3_DATA7           0x59
 655                 >;
 656         };
 657 };
 658
 659 &iomuxc_lpsr {
 660         pinctrl-names = "default";
 661         pinctrl-0 = <&pinctrl_hog_2>;
 662
 663         pinctrl_hog_2: hoggrp-2 {
 664                 fsl,pins = <
 665                         MX7D_PAD_LPSR_GPIO1_IO02__GPIO1_IO2     0x7d
 666                         MX7D_PAD_LPSR_GPIO1_IO03__CCM_CLKO2     0x7d
 667                 >;
 668         };
 669
 670         pinctrl_backlight_j9: backlightj9grp {
 671                 fsl,pins = <
 672                         MX7D_PAD_LPSR_GPIO1_IO07__GPIO1_IO7     0x7d
 673                 >;
 674         };
 675
 676         pinctrl_pwm1: pwm1grp {
 677                 fsl,pins = <
 678                         MX7D_PAD_LPSR_GPIO1_IO01__PWM1_OUT      0x7d
 679                 >;
 680         };
 681
 682         pinctrl_usbotg1: usbotg1grp {
 683                 fsl,pins = <
 684                         MX7D_PAD_LPSR_GPIO1_IO04__USB_OTG1_OC   0x7d
 685                         MX7D_PAD_LPSR_GPIO1_IO05__GPIO1_IO5     0x14
 686                 >;
 687         };
 688
 689         pinctrl_wdog1: wdog1grp {
 690                 fsl,pins = <
 691                         MX7D_PAD_LPSR_GPIO1_IO00__WDOG1_WDOG_B  0x75
 692                 >;
 693         };
 694 };