1 // SPDX-License-Identifier: GPL-2.0
3 * Device Tree for the ARM Integrator/AP platform
7 /include/ "integrator.dtsi"
10 model = "ARM Integrator/AP";
11 compatible = "arm,integrator-ap";
20 * Since the board has pluggable CPU modules, we
21 * cannot define a proper compatible here. Let the
22 * boot loader fill in the apropriate compatible
23 * string if necessary.
25 /* compatible = "arm,arm926ej-s"; */
28 * The documentation in ARM DUI 0138E page 3-12 states
29 * that the maximum frequency for this clock is 200 MHz
30 * but painful trial-and-error has proved to me that it
31 * is actually just hanging the system above 71 MHz.
35 operating-points = <71000 0
44 clock-latency = <1000000>; /* 1 ms */
49 arm,timer-primary = &timer2;
50 arm,timer-secondary = &timer1;
54 bootargs = "root=/dev/ram0 console=ttyAM0,38400n8 earlyprintk";
57 /* 24 MHz chrystal on the Integrator/AP development board */
58 xtal24mhz: xtal24mhz@24M {
60 compatible = "fixed-clock";
61 clock-frequency = <24000000>;
66 compatible = "fixed-factor-clock";
69 clocks = <&xtal24mhz>;
72 /* The UART clock is 14.74 MHz divided by an ICS525 */
73 uartclk: uartclk@14.74M {
75 compatible = "fixed-clock";
76 clock-frequency = <14745600>;
77 clocks = <&xtal24mhz>;
80 core-module@10000000 {
81 /* 24 MHz chrystal on the core module */
82 cm24mhz: cm24mhz@24M {
84 compatible = "fixed-clock";
85 clock-frequency = <24000000>;
88 /* Oscillator on the core module, clocks the CPU core */
90 compatible = "arm,syscon-icst525-integratorap-cm";
97 /* Auxilary oscillator on the core module, 32.369MHz at boot */
99 compatible = "arm,syscon-icst525";
101 lock-offset = <0x14>;
108 compatible = "arm,integrator-ap-syscon", "syscon";
109 reg = <0x11000000 0x100>;
110 interrupt-parent = <&pic>;
111 /* These are the logical module IRQs */
112 interrupts = <9>, <10>, <11>, <12>;
115 * SYSCLK clocks PCIv3 bridge, system controller and the
119 compatible = "arm,syscon-icst525-integratorap-sys";
121 lock-offset = <0x1c>;
123 clocks = <&xtal24mhz>;
126 /* One-bit control for the PCI bus clock (33 or 25 MHz) */
128 compatible = "arm,syscon-icst525-integratorap-pci";
130 lock-offset = <0x1c>;
132 clocks = <&xtal24mhz>;
136 timer0: timer@13000000 {
137 compatible = "arm,integrator-timer";
138 clocks = <&xtal24mhz>;
141 timer1: timer@13000100 {
142 compatible = "arm,integrator-timer";
143 clocks = <&xtal24mhz>;
146 timer2: timer@13000200 {
147 compatible = "arm,integrator-timer";
148 clocks = <&xtal24mhz>;
152 valid-mask = <0x003fffff>;
155 pci: pciv3@62000000 {
156 compatible = "arm,integrator-ap-pci", "v3,v360epc-pci";
157 #interrupt-cells = <1>;
159 #address-cells = <3>;
160 /* Bridge registers and config access space */
161 reg = <0x62000000 0x10000>, <0x61000000 0x01000000>;
162 interrupt-parent = <&pic>;
163 interrupts = <17>; /* Bus error IRQ */
165 bus-range = <0x00 0xff>;
166 ranges = <0x01000000 0 0x0000000 /* I/O space @00000000 */
167 0x60000000 0 0x00010000 /* 64 KB @ LB 60000000 */
168 0x02000000 0 0x40000000 /* non-prefectable memory @40000000 */
169 0x40000000 0 0x10000000 /* 256 MiB @ LB 40000000 1:1 */
170 0x42000000 0 0x50000000 /* prefetchable memory @50000000 */
171 0x50000000 0 0x10000000>; /* 256 MiB @ LB 50000000 1:1 */
172 dma-ranges = <0x02000000 0 0x20000000 /* EBI memory space */
173 0x20000000 0 0x20000000 /* 512 MB @ LB 20000000 1:1 */
174 0x02000000 0 0x80000000 /* Core module alias memory */
175 0x80000000 0 0x40000000>; /* 1GB @ LB 80000000 */
176 interrupt-map-mask = <0xf800 0 0 0x7>;
179 0x4800 0 0 1 &pic 13 /* INT A on slot 9 is irq 13 */
180 0x4800 0 0 2 &pic 14 /* INT B on slot 9 is irq 14 */
181 0x4800 0 0 3 &pic 15 /* INT C on slot 9 is irq 15 */
182 0x4800 0 0 4 &pic 16 /* INT D on slot 9 is irq 16 */
184 0x5000 0 0 1 &pic 14 /* INT A on slot 10 is irq 14 */
185 0x5000 0 0 2 &pic 15 /* INT B on slot 10 is irq 15 */
186 0x5000 0 0 3 &pic 16 /* INT C on slot 10 is irq 16 */
187 0x5000 0 0 4 &pic 13 /* INT D on slot 10 is irq 13 */
189 0x5800 0 0 1 &pic 15 /* INT A on slot 11 is irq 15 */
190 0x5800 0 0 2 &pic 16 /* INT B on slot 11 is irq 16 */
191 0x5800 0 0 3 &pic 13 /* INT C on slot 11 is irq 13 */
192 0x5800 0 0 4 &pic 14 /* INT D on slot 11 is irq 14 */
194 0x6000 0 0 1 &pic 16 /* INT A on slot 12 is irq 16 */
195 0x6000 0 0 2 &pic 13 /* INT B on slot 12 is irq 13 */
196 0x6000 0 0 3 &pic 14 /* INT C on slot 12 is irq 14 */
197 0x6000 0 0 4 &pic 15 /* INT D on slot 12 is irq 15 */
203 * The Integator/AP predates the idea to have magic numbers
204 * identifying the PrimeCell in hardware, thus we have to
205 * supply these from the device tree.
208 compatible = "arm,pl030", "arm,primecell";
209 arm,primecell-periphid = <0x00041030>;
211 clock-names = "apb_pclk";
214 uart0: uart@16000000 {
215 compatible = "arm,pl010", "arm,primecell";
216 arm,primecell-periphid = <0x00041010>;
217 clocks = <&uartclk>, <&pclk>;
218 clock-names = "uartclk", "apb_pclk";
221 uart1: uart@17000000 {
222 compatible = "arm,pl010", "arm,primecell";
223 arm,primecell-periphid = <0x00041010>;
224 clocks = <&uartclk>, <&pclk>;
225 clock-names = "uartclk", "apb_pclk";
229 compatible = "arm,pl050", "arm,primecell";
230 arm,primecell-periphid = <0x00041050>;
231 clocks = <&xtal24mhz>, <&pclk>;
232 clock-names = "KMIREFCLK", "apb_pclk";
236 compatible = "arm,pl050", "arm,primecell";
237 arm,primecell-periphid = <0x00041050>;
238 clocks = <&xtal24mhz>, <&pclk>;
239 clock-names = "KMIREFCLK", "apb_pclk";