1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2013-2017 Texas Instruments Incorporated - http://www.ti.com/
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/gpio/gpio.h>
10 compatible = "ti,keystone";
11 model = "Texas Instruments Keystone 2 SoC";
14 interrupt-parent = <&gic>;
25 memory: memory@80000000 {
26 device_type = "memory";
27 reg = <0x00000000 0x80000000 0x00000000 0x40000000>;
30 gic: interrupt-controller@2561000 {
31 compatible = "arm,gic-400", "arm,cortex-a15-gic";
32 #interrupt-cells = <3>;
34 reg = <0x0 0x02561000 0x0 0x1000>,
35 <0x0 0x02562000 0x0 0x2000>,
36 <0x0 0x02564000 0x0 0x2000>,
37 <0x0 0x02566000 0x0 0x2000>;
38 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) |
39 IRQ_TYPE_LEVEL_HIGH)>;
43 compatible = "arm,armv7-timer";
46 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
48 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
50 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
52 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
56 compatible = "arm,cortex-a15-pmu";
57 interrupts = <GIC_SPI 20 IRQ_TYPE_EDGE_RISING>,
58 <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>,
59 <GIC_SPI 22 IRQ_TYPE_EDGE_RISING>,
60 <GIC_SPI 23 IRQ_TYPE_EDGE_RISING>;
64 compatible = "arm,psci";
66 cpu_suspend = <0x84000001>;
67 cpu_off = <0x84000002>;
68 cpu_on = <0x84000003>;
74 compatible = "ti,keystone","simple-bus";
75 interrupt-parent = <&gic>;
76 ranges = <0x0 0x0 0x0 0xc0000000>;
77 dma-ranges = <0x80000000 0x8 0x00000000 0x80000000>;
79 pllctrl: pll-controller@2310000 {
80 compatible = "ti,keystone-pllctrl", "syscon";
81 reg = <0x02310000 0x200>;
84 psc: power-sleep-controller@2350000 {
85 compatible = "syscon", "simple-mfd";
86 reg = <0x02350000 0x1000>;
89 devctrl: device-state-control@2620000 {
90 compatible = "ti,keystone-devctrl", "syscon";
91 reg = <0x02620000 0x1000>;
94 rstctrl: reset-controller {
95 compatible = "ti,keystone-reset";
96 ti,syscon-pll = <&pllctrl 0xe4>;
97 ti,syscon-dev = <&devctrl 0x328>;
101 /include/ "keystone-clocks.dtsi"
103 uart0: serial@2530c00 {
104 compatible = "ti,da830-uart", "ns16550a";
105 current-speed = <115200>;
108 reg = <0x02530c00 0x100>;
109 clocks = <&clkuart0>;
110 interrupts = <GIC_SPI 277 IRQ_TYPE_EDGE_RISING>;
113 uart1: serial@2531000 {
114 compatible = "ti,da830-uart", "ns16550a";
115 current-speed = <115200>;
118 reg = <0x02531000 0x100>;
119 clocks = <&clkuart1>;
120 interrupts = <GIC_SPI 280 IRQ_TYPE_EDGE_RISING>;
124 compatible = "ti,davinci-i2c";
125 reg = <0x02530000 0x400>;
126 clock-frequency = <100000>;
128 interrupts = <GIC_SPI 283 IRQ_TYPE_EDGE_RISING>;
129 #address-cells = <1>;
134 compatible = "ti,davinci-i2c";
135 reg = <0x02530400 0x400>;
136 clock-frequency = <100000>;
138 interrupts = <GIC_SPI 286 IRQ_TYPE_EDGE_RISING>;
139 #address-cells = <1>;
144 compatible = "ti,davinci-i2c";
145 reg = <0x02530800 0x400>;
146 clock-frequency = <100000>;
148 interrupts = <GIC_SPI 289 IRQ_TYPE_EDGE_RISING>;
149 #address-cells = <1>;
154 compatible = "ti,keystone-spi", "ti,dm6441-spi";
155 reg = <0x21000400 0x200>;
157 ti,davinci-spi-intr-line = <0>;
158 interrupts = <GIC_SPI 292 IRQ_TYPE_EDGE_RISING>;
160 #address-cells = <1>;
165 compatible = "ti,keystone-spi", "ti,dm6441-spi";
166 reg = <0x21000600 0x200>;
168 ti,davinci-spi-intr-line = <0>;
169 interrupts = <GIC_SPI 296 IRQ_TYPE_EDGE_RISING>;
171 #address-cells = <1>;
176 compatible = "ti,keystone-spi", "ti,dm6441-spi";
177 reg = <0x21000800 0x200>;
179 ti,davinci-spi-intr-line = <0>;
180 interrupts = <GIC_SPI 300 IRQ_TYPE_EDGE_RISING>;
182 #address-cells = <1>;
186 usb_phy: usb_phy@2620738 {
187 compatible = "ti,keystone-usbphy";
188 #address-cells = <1>;
190 reg = <0x2620738 24>;
194 keystone_usb0: usb@2680000 {
195 compatible = "ti,keystone-dwc3";
196 #address-cells = <1>;
198 reg = <0x2680000 0x10000>;
201 interrupts = <GIC_SPI 393 IRQ_TYPE_EDGE_RISING>;
208 compatible = "synopsys,dwc3";
209 reg = <0x2690000 0x70000>;
210 interrupts = <GIC_SPI 393 IRQ_TYPE_EDGE_RISING>;
211 usb-phy = <&usb_phy>, <&usb_phy>;
216 compatible = "ti,keystone-wdt","ti,davinci-wdt";
217 reg = <0x022f0080 0x80>;
218 clocks = <&clkwdtimer0>;
221 clock_event: timer@22f0000 {
222 compatible = "ti,keystone-timer";
223 reg = <0x022f0000 0x80>;
224 interrupts = <GIC_SPI 110 IRQ_TYPE_EDGE_RISING>;
225 clocks = <&clktimer15>;
228 gpio0: gpio@260bf00 {
229 compatible = "ti,keystone-gpio";
230 reg = <0x0260bf00 0x100>;
233 /* HW Interrupts mapped to GPIO pins */
234 interrupts = <GIC_SPI 120 IRQ_TYPE_EDGE_RISING>,
235 <GIC_SPI 121 IRQ_TYPE_EDGE_RISING>,
236 <GIC_SPI 122 IRQ_TYPE_EDGE_RISING>,
237 <GIC_SPI 123 IRQ_TYPE_EDGE_RISING>,
238 <GIC_SPI 124 IRQ_TYPE_EDGE_RISING>,
239 <GIC_SPI 125 IRQ_TYPE_EDGE_RISING>,
240 <GIC_SPI 126 IRQ_TYPE_EDGE_RISING>,
241 <GIC_SPI 127 IRQ_TYPE_EDGE_RISING>,
242 <GIC_SPI 128 IRQ_TYPE_EDGE_RISING>,
243 <GIC_SPI 129 IRQ_TYPE_EDGE_RISING>,
244 <GIC_SPI 130 IRQ_TYPE_EDGE_RISING>,
245 <GIC_SPI 131 IRQ_TYPE_EDGE_RISING>,
246 <GIC_SPI 132 IRQ_TYPE_EDGE_RISING>,
247 <GIC_SPI 133 IRQ_TYPE_EDGE_RISING>,
248 <GIC_SPI 134 IRQ_TYPE_EDGE_RISING>,
249 <GIC_SPI 135 IRQ_TYPE_EDGE_RISING>,
250 <GIC_SPI 136 IRQ_TYPE_EDGE_RISING>,
251 <GIC_SPI 137 IRQ_TYPE_EDGE_RISING>,
252 <GIC_SPI 138 IRQ_TYPE_EDGE_RISING>,
253 <GIC_SPI 139 IRQ_TYPE_EDGE_RISING>,
254 <GIC_SPI 140 IRQ_TYPE_EDGE_RISING>,
255 <GIC_SPI 141 IRQ_TYPE_EDGE_RISING>,
256 <GIC_SPI 142 IRQ_TYPE_EDGE_RISING>,
257 <GIC_SPI 143 IRQ_TYPE_EDGE_RISING>,
258 <GIC_SPI 144 IRQ_TYPE_EDGE_RISING>,
259 <GIC_SPI 145 IRQ_TYPE_EDGE_RISING>,
260 <GIC_SPI 146 IRQ_TYPE_EDGE_RISING>,
261 <GIC_SPI 147 IRQ_TYPE_EDGE_RISING>,
262 <GIC_SPI 148 IRQ_TYPE_EDGE_RISING>,
263 <GIC_SPI 149 IRQ_TYPE_EDGE_RISING>,
264 <GIC_SPI 150 IRQ_TYPE_EDGE_RISING>,
265 <GIC_SPI 151 IRQ_TYPE_EDGE_RISING>;
267 clock-names = "gpio";
269 ti,davinci-gpio-unbanked = <32>;
272 aemif: aemif@21000A00 {
273 compatible = "ti,keystone-aemif", "ti,davinci-aemif";
274 #address-cells = <2>;
276 clocks = <&clkaemif>;
277 clock-names = "aemif";
280 reg = <0x21000A00 0x00000100>;
281 ranges = <0 0 0x30000000 0x10000000
282 1 0 0x21000A00 0x00000100>;
285 kirq0: keystone_irq@26202a0 {
286 compatible = "ti,keystone-irq";
287 interrupts = <GIC_SPI 4 IRQ_TYPE_EDGE_RISING>;
288 interrupt-controller;
289 #interrupt-cells = <1>;
290 ti,syscon-dev = <&devctrl 0x2a0>;
293 pcie0: pcie@21800000 {
294 compatible = "ti,keystone-pcie", "snps,dw-pcie";
296 clock-names = "pcie";
297 #address-cells = <3>;
299 reg = <0x21801000 0x2000>, <0x21800000 0x1000>, <0x02620128 4>;
300 ranges = <0x82000000 0 0x50000000 0x50000000
306 bus-range = <0x00 0xff>;
308 /* error interrupt */
309 interrupts = <GIC_SPI 38 IRQ_TYPE_EDGE_RISING>;
310 #interrupt-cells = <1>;
311 interrupt-map-mask = <0 0 0 7>;
312 interrupt-map = <0 0 0 1 &pcie_intc0 0>, /* INT A */
313 <0 0 0 2 &pcie_intc0 1>, /* INT B */
314 <0 0 0 3 &pcie_intc0 2>, /* INT C */
315 <0 0 0 4 &pcie_intc0 3>; /* INT D */
317 pcie_msi_intc0: msi-interrupt-controller {
318 interrupt-controller;
319 #interrupt-cells = <1>;
320 interrupt-parent = <&gic>;
321 interrupts = <GIC_SPI 30 IRQ_TYPE_EDGE_RISING>,
322 <GIC_SPI 31 IRQ_TYPE_EDGE_RISING>,
323 <GIC_SPI 32 IRQ_TYPE_EDGE_RISING>,
324 <GIC_SPI 33 IRQ_TYPE_EDGE_RISING>,
325 <GIC_SPI 34 IRQ_TYPE_EDGE_RISING>,
326 <GIC_SPI 35 IRQ_TYPE_EDGE_RISING>,
327 <GIC_SPI 36 IRQ_TYPE_EDGE_RISING>,
328 <GIC_SPI 37 IRQ_TYPE_EDGE_RISING>;
331 pcie_intc0: legacy-interrupt-controller {
332 interrupt-controller;
333 #interrupt-cells = <1>;
334 interrupt-parent = <&gic>;
335 interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>,
336 <GIC_SPI 27 IRQ_TYPE_EDGE_RISING>,
337 <GIC_SPI 28 IRQ_TYPE_EDGE_RISING>,
338 <GIC_SPI 29 IRQ_TYPE_EDGE_RISING>;