2 * This program is free software; you can redistribute it and/or modify
3 * it under the terms of the GNU General Public License version 2 as
4 * published by the Free Software Foundation.
7 #include <dt-bindings/input/input.h>
17 device_type = "memory";
21 wl12xx_vmmc: wl12xx_vmmc {
22 compatible = "regulator-fixed";
23 regulator-name = "vwl1271";
24 regulator-min-microvolt = <1800000>;
25 regulator-max-microvolt = <1800000>;
26 gpio = <&gpio1 3 0>; /* gpio_3 */
27 startup-delay-us = <70000>;
29 vin-supply = <&vmmc2>;
32 /* HS USB Host PHY on PORT 1 */
33 hsusb2_phy: hsusb2_phy {
34 compatible = "usb-nop-xceiv";
35 reset-gpios = <&gpio1 4 GPIO_ACTIVE_LOW>; /* gpio_4 */
41 ranges = <0 0 0x30000000 0x1000000>; /* CS0: 16MB for NAND */
44 compatible = "ti,omap2-nand";
45 reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
46 interrupt-parent = <&gpmc>;
47 interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
48 <1 IRQ_TYPE_NONE>; /* termcount */
49 linux,mtd-name = "micron,mt29f4g16abbda3w";
50 nand-bus-width = <16>;
51 ti,nand-ecc-opt = "bch8";
52 rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 */
53 gpmc,sync-clk-ps = <0>;
55 gpmc,cs-rd-off-ns = <44>;
56 gpmc,cs-wr-off-ns = <44>;
58 gpmc,adv-rd-off-ns = <34>;
59 gpmc,adv-wr-off-ns = <44>;
60 gpmc,we-off-ns = <40>;
61 gpmc,oe-off-ns = <54>;
62 gpmc,access-ns = <64>;
63 gpmc,rd-cycle-ns = <82>;
64 gpmc,wr-cycle-ns = <82>;
65 gpmc,wr-access-ns = <40>;
66 gpmc,wr-data-mux-bus-ns = <0>;
67 gpmc,device-width = <2>;
74 pinctrl-names = "default";
75 pinctrl-0 = <&i2c1_pins>;
76 clock-frequency = <2600000>;
80 interrupts = <7>; /* SYS_NIRQ cascaded to intc */
81 interrupt-parent = <&intc>;
83 compatible = "ti,twl4030-audio";
91 clock-frequency = <400000>;
95 clock-frequency = <400000>;
99 interrupts-extended = <&intc 94 &omap3_pmx_core2 0x46>;
100 pinctrl-0 = <&mmc3_pins &wl127x_gpio>;
101 pinctrl-names = "default";
102 vmmc-supply = <&wl12xx_vmmc>;
106 #address-cells = <1>;
109 compatible = "ti,wl1273";
111 interrupt-parent = <&gpio1>;
112 interrupts = <2 IRQ_TYPE_LEVEL_HIGH>; /* gpio 2 */
113 ref-clock-frequency = <26000000>;
118 port2-mode = "ehci-phy";
122 phys = <0 &hsusb2_phy>;
127 pinctrl-names = "default";
128 pinctrl-0 = <&hsusb2_pins>;
130 mmc3_pins: pinmux_mm3_pins {
131 pinctrl-single,pins = <
132 OMAP3_CORE1_IOPAD(0x2164, PIN_INPUT_PULLUP | MUX_MODE3) /* sdmmc2_dat4.sdmmc3_dat0 */
133 OMAP3_CORE1_IOPAD(0x2166, PIN_INPUT_PULLUP | MUX_MODE3) /* sdmmc2_dat5.sdmmc3_dat1 */
134 OMAP3_CORE1_IOPAD(0x2168, PIN_INPUT_PULLUP | MUX_MODE3) /* sdmmc2_dat6.sdmmc3_dat2 */
135 OMAP3_CORE1_IOPAD(0x216a, PIN_INPUT_PULLUP | MUX_MODE3) /* sdmmc2_dat6.sdmmc3_dat3 */
136 OMAP3_CORE1_IOPAD(0x21d0, PIN_INPUT_PULLUP | MUX_MODE3) /* mcspi1_cs1.sdmmc3_cmd */
137 OMAP3_CORE1_IOPAD(0x21d2, PIN_INPUT_PULLUP | MUX_MODE3) /* mcspi1_cs2.sdmmc_clk */
140 mcbsp2_pins: pinmux_mcbsp2_pins {
141 pinctrl-single,pins = <
142 OMAP3_CORE1_IOPAD(0x213c, PIN_INPUT | MUX_MODE0) /* mcbsp2_fsx */
143 OMAP3_CORE1_IOPAD(0x213e, PIN_INPUT | MUX_MODE0) /* mcbsp2_clkx */
144 OMAP3_CORE1_IOPAD(0x2140, PIN_INPUT | MUX_MODE0) /* mcbsp2_dr */
145 OMAP3_CORE1_IOPAD(0x2142, PIN_OUTPUT | MUX_MODE0) /* mcbsp2_dx */
148 uart2_pins: pinmux_uart2_pins {
149 pinctrl-single,pins = <
150 OMAP3_CORE1_IOPAD(0x2174, PIN_INPUT | MUX_MODE0) /* uart2_cts.uart2_cts */
151 OMAP3_CORE1_IOPAD(0x2176, PIN_OUTPUT | MUX_MODE0) /* uart2_rts .uart2_rts*/
152 OMAP3_CORE1_IOPAD(0x2178, PIN_OUTPUT | MUX_MODE0) /* uart2_tx.uart2_tx */
153 OMAP3_CORE1_IOPAD(0x217a, PIN_INPUT | MUX_MODE0) /* uart2_rx.uart2_rx */
154 OMAP3_CORE1_IOPAD(0x2198, PIN_OUTPUT | MUX_MODE4) /* GPIO_162,BT_EN */
157 mcspi1_pins: pinmux_mcspi1_pins {
158 pinctrl-single,pins = <
159 OMAP3_CORE1_IOPAD(0x21c8, PIN_INPUT | MUX_MODE0) /* mcspi1_clk.mcspi1_clk */
160 OMAP3_CORE1_IOPAD(0x21ca, PIN_OUTPUT | MUX_MODE0) /* mcspi1_simo.mcspi1_simo */
161 OMAP3_CORE1_IOPAD(0x21cc, PIN_INPUT_PULLUP | MUX_MODE0) /* mcspi1_somi.mcspi1_somi */
162 OMAP3_CORE1_IOPAD(0x21ce, PIN_OUTPUT | MUX_MODE0) /* mcspi1_cs0.mcspi1_cs0 */
166 hsusb2_pins: pinmux_hsusb2_pins {
167 pinctrl-single,pins = <
168 OMAP3_CORE1_IOPAD(0x21d4, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi1_cs3.hsusb2_data2 */
169 OMAP3_CORE1_IOPAD(0x21d6, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_clk.hsusb2_data7 */
170 OMAP3_CORE1_IOPAD(0x21d8, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_simo.hsusb2_data4 */
171 OMAP3_CORE1_IOPAD(0x21da, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_somi.hsusb2_data5 */
172 OMAP3_CORE1_IOPAD(0x21dc, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_cs0.hsusb2_data6 */
173 OMAP3_CORE1_IOPAD(0x21de, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_cs1.hsusb2_data3 */
177 hsusb_otg_pins: pinmux_hsusb_otg_pins {
178 pinctrl-single,pins = <
179 OMAP3_CORE1_IOPAD(0x21a2, PIN_INPUT | MUX_MODE0) /* hsusb0_clk.hsusb0_clk */
180 OMAP3_CORE1_IOPAD(0x21a4, PIN_OUTPUT | MUX_MODE0) /* hsusb0_stp.hsusb0_stp */
181 OMAP3_CORE1_IOPAD(0x21a6, PIN_INPUT | MUX_MODE0) /* hsusb0_dir.hsusb0_dir */
182 OMAP3_CORE1_IOPAD(0x21a8, PIN_INPUT | MUX_MODE0) /* hsusb0_nxt.hsusb0_nxt */
183 OMAP3_CORE1_IOPAD(0x21aa, PIN_INPUT | MUX_MODE0) /* hsusb0_data0.hsusb0_data0 */
184 OMAP3_CORE1_IOPAD(0x21ac, PIN_INPUT | MUX_MODE0) /* hsusb0_data1.hsusb0_data1 */
185 OMAP3_CORE1_IOPAD(0x21ae, PIN_INPUT | MUX_MODE0) /* hsusb0_data2.hsusb0_data2 */
186 OMAP3_CORE1_IOPAD(0x21b0, PIN_INPUT | MUX_MODE0) /* hsusb0_data3.hsusb0_data3 */
187 OMAP3_CORE1_IOPAD(0x21b2, PIN_INPUT | MUX_MODE0) /* hsusb0_data4.hsusb0_data4 */
188 OMAP3_CORE1_IOPAD(0x21b4, PIN_INPUT | MUX_MODE0) /* hsusb0_data5.hsusb0_data5 */
189 OMAP3_CORE1_IOPAD(0x21b6, PIN_INPUT | MUX_MODE0) /* hsusb0_data6.hsusb0_data6 */
190 OMAP3_CORE1_IOPAD(0x21b8, PIN_INPUT | MUX_MODE0) /* hsusb0_data7.hsusb0_data7 */
194 i2c1_pins: pinmux_i2c1_pins {
195 pinctrl-single,pins = <
196 OMAP3_CORE1_IOPAD(0x21ba, PIN_INPUT | MUX_MODE0) /* i2c1_scl.i2c1_scl */
197 OMAP3_CORE1_IOPAD(0x21bc, PIN_INPUT | MUX_MODE0) /* i2c1_sda.i2c1_sda */
203 pinctrl-names = "default";
204 pinctrl-0 = <&hsusb2_reset_pin>;
205 hsusb2_reset_pin: pinmux_hsusb1_reset_pin {
206 pinctrl-single,pins = <
207 OMAP3_WKUP_IOPAD(0x2a0e, PIN_OUTPUT | MUX_MODE4) /* sys_boot2.gpio_4 */
210 wl127x_gpio: pinmux_wl127x_gpio_pin {
211 pinctrl-single,pins = <
212 OMAP3_WKUP_IOPAD(0x2a0c, PIN_INPUT | MUX_MODE4) /* sys_boot0.gpio_2 */
213 OMAP3_WKUP_IOPAD(0x2a0c, PIN_OUTPUT | MUX_MODE4) /* sys_boot1.gpio_3 */
219 pinctrl-names = "default";
220 pinctrl-0 = <&hsusb2_2_pins>;
221 hsusb2_2_pins: pinmux_hsusb2_2_pins {
222 pinctrl-single,pins = <
223 OMAP3630_CORE2_IOPAD(0x25f0, PIN_OUTPUT | MUX_MODE3) /* etk_d10.hsusb2_clk */
224 OMAP3630_CORE2_IOPAD(0x25f2, PIN_OUTPUT | MUX_MODE3) /* etk_d11.hsusb2_stp */
225 OMAP3630_CORE2_IOPAD(0x25f4, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d12.hsusb2_dir */
226 OMAP3630_CORE2_IOPAD(0x25f6, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d13.hsusb2_nxt */
227 OMAP3630_CORE2_IOPAD(0x25f8, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d14.hsusb2_data0 */
228 OMAP3630_CORE2_IOPAD(0x25fa, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d15.hsusb2_data1 */
234 interrupts-extended = <&intc 73 &omap3_pmx_core OMAP3_UART2_RX>;
235 pinctrl-names = "default";
236 pinctrl-0 = <&uart2_pins>;
240 pinctrl-names = "default";
241 pinctrl-0 = <&mcspi1_pins>;
244 #include "twl4030.dtsi"
245 #include "twl4030_omap3.dtsi"
249 compatible = "ti,twl4030-power-idle-osc-off", "ti,twl4030-power-idle";