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50 #include "ls1021a.dtsi"
53 model = "LS1021A QDS Board";
56 enet0_rgmii_phy = &rgmii_phy1;
57 enet1_rgmii_phy = &rgmii_phy2;
58 enet2_rgmii_phy = &rgmii_phy3;
59 enet0_sgmii_phy = &sgmii_phy1c;
60 enet1_sgmii_phy = &sgmii_phy1d;
63 sys_mclk: clock-mclk {
64 compatible = "fixed-clock";
66 clock-frequency = <24576000>;
70 compatible = "simple-bus";
74 reg_3p3v: regulator@0 {
75 compatible = "regulator-fixed";
77 regulator-name = "3P3V";
78 regulator-min-microvolt = <3300000>;
79 regulator-max-microvolt = <3300000>;
85 compatible = "simple-audio-card";
86 simple-audio-card,format = "i2s";
87 simple-audio-card,widgets =
88 "Microphone", "Microphone Jack",
89 "Headphone", "Headphone Jack",
90 "Speaker", "Speaker Ext",
91 "Line", "Line In Jack";
92 simple-audio-card,routing =
93 "MIC_IN", "Microphone Jack",
94 "Microphone Jack", "Mic Bias",
95 "LINE_IN", "Line In Jack",
96 "Headphone Jack", "HP_OUT",
97 "Speaker Ext", "LINE_OUT";
99 simple-audio-card,cpu {
105 simple-audio-card,codec {
106 sound-dai = <&codec>;
117 dspiflash: at45db021d@0 {
118 #address-cells = <1>;
120 compatible = "atmel,at45db021d", "atmel,at45", "atmel,dataflash";
121 spi-max-frequency = <16000000>;
129 tbi-handle = <&tbi0>;
130 phy-handle = <&sgmii_phy1c>;
131 phy-connection-type = "sgmii";
136 tbi-handle = <&tbi0>;
137 phy-handle = <&sgmii_phy1d>;
138 phy-connection-type = "sgmii";
143 phy-handle = <&rgmii_phy3>;
144 phy-connection-type = "rgmii-id";
152 compatible = "nxp,pca9547";
154 #address-cells = <1>;
158 #address-cells = <1>;
163 compatible = "dallas,ds3232";
165 interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
170 #address-cells = <1>;
175 compatible = "ti,ina220";
177 shunt-resistor = <1000>;
181 compatible = "ti,ina220";
183 shunt-resistor = <1000>;
188 #address-cells = <1>;
193 compatible = "atmel,24c512";
198 compatible = "atmel,24c512";
203 compatible = "adi,adt7461a";
209 #address-cells = <1>;
214 #sound-dai-cells = <0>;
215 compatible = "fsl,sgtl5000";
217 VDDA-supply = <®_3p3v>;
218 VDDIO-supply = <®_3p3v>;
219 clocks = <&sys_mclk>;
226 #address-cells = <2>;
228 /* NOR, NAND Flashes and FPGA on board */
229 ranges = <0x0 0x0 0x0 0x60000000 0x08000000
230 0x2 0x0 0x0 0x7e800000 0x00010000
231 0x3 0x0 0x0 0x7fb00000 0x00000100>;
235 #address-cells = <1>;
237 compatible = "cfi-flash";
238 reg = <0x0 0x0 0x8000000>;
245 compatible = "fsl,ifc-nand";
246 reg = <0x2 0x0 0x10000>;
249 fpga: board-control@3,0 {
250 #address-cells = <1>;
252 compatible = "simple-bus";
253 reg = <0x3 0x0 0x0000100>;
256 ranges = <0 3 0 0x100>;
259 compatible = "mdio-mux-mmioreg";
260 mdio-parent-bus = <&mdio0>;
261 #address-cells = <1>;
263 reg = <0x54 1>; /* BRDCFG4 */
264 mux-mask = <0xe0>; /* EMI1[2:0] */
267 ls1021amdio0: mdio@0 {
269 #address-cells = <1>;
271 rgmii_phy1: ethernet-phy@1 {
276 ls1021amdio1: mdio@20 {
278 #address-cells = <1>;
280 rgmii_phy2: ethernet-phy@2 {
285 ls1021amdio2: mdio@40 {
287 #address-cells = <1>;
289 rgmii_phy3: ethernet-phy@3 {
294 ls1021amdio3: mdio@60 {
296 #address-cells = <1>;
298 sgmii_phy1c: ethernet-phy@1c {
303 ls1021amdio4: mdio@80 {
305 #address-cells = <1>;
307 sgmii_phy1d: ethernet-phy@1d {
322 device_type = "tbi-phy";