2 * Copyright 2013-2014 Freescale Semiconductor, Inc.
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50 #include "ls1021a.dtsi"
53 model = "LS1021A QDS Board";
54 compatible = "fsl,ls1021a-qds", "fsl,ls1021a";
57 enet0_rgmii_phy = &rgmii_phy1;
58 enet1_rgmii_phy = &rgmii_phy2;
59 enet2_rgmii_phy = &rgmii_phy3;
60 enet0_sgmii_phy = &sgmii_phy1c;
61 enet1_sgmii_phy = &sgmii_phy1d;
64 sys_mclk: clock-mclk {
65 compatible = "fixed-clock";
67 clock-frequency = <24576000>;
71 compatible = "simple-bus";
75 reg_3p3v: regulator@0 {
76 compatible = "regulator-fixed";
78 regulator-name = "3P3V";
79 regulator-min-microvolt = <3300000>;
80 regulator-max-microvolt = <3300000>;
86 compatible = "simple-audio-card";
87 simple-audio-card,format = "i2s";
88 simple-audio-card,widgets =
89 "Microphone", "Microphone Jack",
90 "Headphone", "Headphone Jack",
91 "Speaker", "Speaker Ext",
92 "Line", "Line In Jack";
93 simple-audio-card,routing =
94 "MIC_IN", "Microphone Jack",
95 "Microphone Jack", "Mic Bias",
96 "LINE_IN", "Line In Jack",
97 "Headphone Jack", "HP_OUT",
98 "Speaker Ext", "LINE_OUT";
100 simple-audio-card,cpu {
106 simple-audio-card,codec {
107 sound-dai = <&codec>;
118 dspiflash: at45db021d@0 {
119 #address-cells = <1>;
121 compatible = "atmel,at45db021d", "atmel,at45", "atmel,dataflash";
122 spi-max-frequency = <16000000>;
130 tbi-handle = <&tbi0>;
131 phy-handle = <&sgmii_phy1c>;
132 phy-connection-type = "sgmii";
137 tbi-handle = <&tbi0>;
138 phy-handle = <&sgmii_phy1d>;
139 phy-connection-type = "sgmii";
144 phy-handle = <&rgmii_phy3>;
145 phy-connection-type = "rgmii-id";
153 compatible = "nxp,pca9547";
155 #address-cells = <1>;
159 #address-cells = <1>;
164 compatible = "dallas,ds3232";
166 interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
171 #address-cells = <1>;
176 compatible = "ti,ina220";
178 shunt-resistor = <1000>;
182 compatible = "ti,ina220";
184 shunt-resistor = <1000>;
189 #address-cells = <1>;
194 compatible = "atmel,24c512";
199 compatible = "atmel,24c512";
204 compatible = "adi,adt7461a";
210 #address-cells = <1>;
215 #sound-dai-cells = <0>;
216 compatible = "fsl,sgtl5000";
218 VDDA-supply = <®_3p3v>;
219 VDDIO-supply = <®_3p3v>;
220 clocks = <&sys_mclk>;
227 #address-cells = <2>;
229 /* NOR, NAND Flashes and FPGA on board */
230 ranges = <0x0 0x0 0x0 0x60000000 0x08000000
231 0x2 0x0 0x0 0x7e800000 0x00010000
232 0x3 0x0 0x0 0x7fb00000 0x00000100>;
236 #address-cells = <1>;
238 compatible = "cfi-flash";
239 reg = <0x0 0x0 0x8000000>;
246 compatible = "fsl,ifc-nand";
247 reg = <0x2 0x0 0x10000>;
250 fpga: board-control@3,0 {
251 #address-cells = <1>;
253 compatible = "simple-bus";
254 reg = <0x3 0x0 0x0000100>;
257 ranges = <0 3 0 0x100>;
260 compatible = "mdio-mux-mmioreg";
261 mdio-parent-bus = <&mdio0>;
262 #address-cells = <1>;
264 reg = <0x54 1>; /* BRDCFG4 */
265 mux-mask = <0xe0>; /* EMI1[2:0] */
268 ls1021amdio0: mdio@0 {
270 #address-cells = <1>;
272 rgmii_phy1: ethernet-phy@1 {
277 ls1021amdio1: mdio@20 {
279 #address-cells = <1>;
281 rgmii_phy2: ethernet-phy@2 {
286 ls1021amdio2: mdio@40 {
288 #address-cells = <1>;
290 rgmii_phy3: ethernet-phy@3 {
295 ls1021amdio3: mdio@60 {
297 #address-cells = <1>;
299 sgmii_phy1c: ethernet-phy@1c {
304 ls1021amdio4: mdio@80 {
306 #address-cells = <1>;
308 sgmii_phy1d: ethernet-phy@1d {
323 device_type = "tbi-phy";