2 * Copyright 2013-2014 Freescale Semiconductor, Inc.
4 * This file is dual-licensed: you can use it either under the terms
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6 * licensing only applies to this file, and not this project as a
9 * a) This file is free software; you can redistribute it and/or
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48 #include "skeleton64.dtsi"
49 #include <dt-bindings/interrupt-controller/arm-gic.h>
50 #include <dt-bindings/thermal/thermal.h>
53 compatible = "fsl,ls1021a";
54 interrupt-parent = <&gic>;
75 compatible = "arm,cortex-a7";
78 clocks = <&clockgen 1 0>;
83 compatible = "arm,cortex-a7";
86 clocks = <&clockgen 1 0>;
92 compatible = "fixed-clock";
94 clock-frequency = <100000000>;
95 clock-output-names = "sysclk";
99 compatible = "arm,armv7-timer";
100 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
101 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
102 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
103 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
107 compatible = "arm,cortex-a7-pmu";
108 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
109 <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
110 interrupt-affinity = <&cpu0>, <&cpu1>;
114 compatible = "syscon-reboot";
121 compatible = "simple-bus";
122 #address-cells = <2>;
125 interrupt-parent = <&gic>;
128 gic: interrupt-controller@1400000 {
129 compatible = "arm,gic-400", "arm,cortex-a7-gic";
130 #interrupt-cells = <3>;
131 interrupt-controller;
132 reg = <0x0 0x1401000 0x0 0x1000>,
133 <0x0 0x1402000 0x0 0x2000>,
134 <0x0 0x1404000 0x0 0x2000>,
135 <0x0 0x1406000 0x0 0x2000>;
136 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
140 msi1: msi-controller@1570e00 {
141 compatible = "fsl,ls1021a-msi";
142 reg = <0x0 0x1570e00 0x0 0x8>;
144 interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>;
147 msi2: msi-controller@1570e08 {
148 compatible = "fsl,ls1021a-msi";
149 reg = <0x0 0x1570e08 0x0 0x8>;
151 interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>;
155 compatible = "fsl,ifc", "simple-bus";
156 reg = <0x0 0x1530000 0x0 0x10000>;
157 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
161 compatible = "fsl,ls1021a-dcfg", "syscon";
162 reg = <0x0 0x1ee0000 0x0 0x10000>;
167 compatible = "fsl,ls1021a-qspi";
168 #address-cells = <1>;
170 reg = <0x0 0x1550000 0x0 0x10000>,
171 <0x0 0x40000000 0x0 0x40000000>;
172 reg-names = "QuadSPI", "QuadSPI-memory";
173 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
174 clock-names = "qspi_en", "qspi";
175 clocks = <&clockgen 4 1>, <&clockgen 4 1>;
180 esdhc: esdhc@1560000 {
181 compatible = "fsl,ls1021a-esdhc", "fsl,esdhc";
182 reg = <0x0 0x1560000 0x0 0x10000>;
183 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
184 clock-frequency = <0>;
185 voltage-ranges = <1800 1800 3300 3300>;
193 compatible = "fsl,ls1021a-ahci";
194 reg = <0x0 0x3200000 0x0 0x10000>,
195 <0x0 0x20220520 0x0 0x4>;
196 reg-names = "ahci", "sata-ecc";
197 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
198 clocks = <&clockgen 4 1>;
204 compatible = "fsl,ls1021a-scfg", "syscon";
205 reg = <0x0 0x1570000 0x0 0x10000>;
209 crypto: crypto@1700000 {
210 compatible = "fsl,sec-v5.0", "fsl,sec-v4.0";
212 #address-cells = <1>;
214 reg = <0x0 0x1700000 0x0 0x100000>;
215 ranges = <0x0 0x0 0x1700000 0x100000>;
216 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
219 compatible = "fsl,sec-v5.0-job-ring",
220 "fsl,sec-v4.0-job-ring";
221 reg = <0x10000 0x10000>;
222 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
226 compatible = "fsl,sec-v5.0-job-ring",
227 "fsl,sec-v4.0-job-ring";
228 reg = <0x20000 0x10000>;
229 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
233 compatible = "fsl,sec-v5.0-job-ring",
234 "fsl,sec-v4.0-job-ring";
235 reg = <0x30000 0x10000>;
236 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
240 compatible = "fsl,sec-v5.0-job-ring",
241 "fsl,sec-v4.0-job-ring";
242 reg = <0x40000 0x10000>;
243 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
248 clockgen: clocking@1ee1000 {
249 compatible = "fsl,ls1021a-clockgen";
250 reg = <0x0 0x1ee1000 0x0 0x1000>;
256 compatible = "fsl,qoriq-tmu";
257 reg = <0x0 0x1f00000 0x0 0x10000>;
258 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
259 fsl,tmu-range = <0xb0000 0xa0026 0x80048 0x30061>;
260 fsl,tmu-calibration = <0x00000000 0x0000000f
261 0x00000001 0x00000017
262 0x00000002 0x0000001e
263 0x00000003 0x00000026
264 0x00000004 0x0000002e
265 0x00000005 0x00000035
266 0x00000006 0x0000003d
267 0x00000007 0x00000044
268 0x00000008 0x0000004c
269 0x00000009 0x00000053
270 0x0000000a 0x0000005b
271 0x0000000b 0x00000064
273 0x00010000 0x00000011
274 0x00010001 0x0000001c
275 0x00010002 0x00000024
276 0x00010003 0x0000002b
277 0x00010004 0x00000034
278 0x00010005 0x00000039
279 0x00010006 0x00000042
280 0x00010007 0x0000004c
281 0x00010008 0x00000051
282 0x00010009 0x0000005a
283 0x0001000a 0x00000063
285 0x00020000 0x00000013
286 0x00020001 0x00000019
287 0x00020002 0x00000024
288 0x00020003 0x0000002c
289 0x00020004 0x00000035
290 0x00020005 0x0000003d
291 0x00020006 0x00000046
292 0x00020007 0x00000050
293 0x00020008 0x00000059
295 0x00030000 0x00000002
296 0x00030001 0x0000000d
297 0x00030002 0x00000019
298 0x00030003 0x00000024>;
299 #thermal-sensor-cells = <1>;
303 cpu_thermal: cpu-thermal {
304 polling-delay-passive = <1000>;
305 polling-delay = <5000>;
307 thermal-sensors = <&tmu 0>;
310 cpu_alert: cpu-alert {
311 temperature = <85000>;
316 temperature = <95000>;
326 <&cpu0 THERMAL_NO_LIMIT
334 compatible = "fsl,ls1021a-v1.0-dspi";
335 #address-cells = <1>;
337 reg = <0x0 0x2100000 0x0 0x10000>;
338 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
339 clock-names = "dspi";
340 clocks = <&clockgen 4 1>;
341 spi-num-chipselects = <6>;
347 compatible = "fsl,ls1021a-v1.0-dspi";
348 #address-cells = <1>;
350 reg = <0x0 0x2110000 0x0 0x10000>;
351 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
352 clock-names = "dspi";
353 clocks = <&clockgen 4 1>;
354 spi-num-chipselects = <6>;
360 compatible = "fsl,vf610-i2c";
361 #address-cells = <1>;
363 reg = <0x0 0x2180000 0x0 0x10000>;
364 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
366 clocks = <&clockgen 4 1>;
367 dma-names = "tx", "rx";
368 dmas = <&edma0 1 39>, <&edma0 1 38>;
373 compatible = "fsl,vf610-i2c";
374 #address-cells = <1>;
376 reg = <0x0 0x2190000 0x0 0x10000>;
377 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
379 clocks = <&clockgen 4 1>;
380 dma-names = "tx", "rx";
381 dmas = <&edma0 1 37>, <&edma0 1 36>;
386 compatible = "fsl,vf610-i2c";
387 #address-cells = <1>;
389 reg = <0x0 0x21a0000 0x0 0x10000>;
390 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
392 clocks = <&clockgen 4 1>;
393 dma-names = "tx", "rx";
394 dmas = <&edma0 1 35>, <&edma0 1 34>;
398 uart0: serial@21c0500 {
399 compatible = "fsl,16550-FIFO64", "ns16550a";
400 reg = <0x0 0x21c0500 0x0 0x100>;
401 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
402 clock-frequency = <0>;
407 uart1: serial@21c0600 {
408 compatible = "fsl,16550-FIFO64", "ns16550a";
409 reg = <0x0 0x21c0600 0x0 0x100>;
410 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
411 clock-frequency = <0>;
416 uart2: serial@21d0500 {
417 compatible = "fsl,16550-FIFO64", "ns16550a";
418 reg = <0x0 0x21d0500 0x0 0x100>;
419 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
420 clock-frequency = <0>;
425 uart3: serial@21d0600 {
426 compatible = "fsl,16550-FIFO64", "ns16550a";
427 reg = <0x0 0x21d0600 0x0 0x100>;
428 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
429 clock-frequency = <0>;
434 gpio0: gpio@2300000 {
435 compatible = "fsl,ls1021a-gpio", "fsl,qoriq-gpio";
436 reg = <0x0 0x2300000 0x0 0x10000>;
437 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
440 interrupt-controller;
441 #interrupt-cells = <2>;
444 gpio1: gpio@2310000 {
445 compatible = "fsl,ls1021a-gpio", "fsl,qoriq-gpio";
446 reg = <0x0 0x2310000 0x0 0x10000>;
447 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
450 interrupt-controller;
451 #interrupt-cells = <2>;
454 gpio2: gpio@2320000 {
455 compatible = "fsl,ls1021a-gpio", "fsl,qoriq-gpio";
456 reg = <0x0 0x2320000 0x0 0x10000>;
457 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
460 interrupt-controller;
461 #interrupt-cells = <2>;
464 gpio3: gpio@2330000 {
465 compatible = "fsl,ls1021a-gpio", "fsl,qoriq-gpio";
466 reg = <0x0 0x2330000 0x0 0x10000>;
467 interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
470 interrupt-controller;
471 #interrupt-cells = <2>;
474 lpuart0: serial@2950000 {
475 compatible = "fsl,ls1021a-lpuart";
476 reg = <0x0 0x2950000 0x0 0x1000>;
477 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
483 lpuart1: serial@2960000 {
484 compatible = "fsl,ls1021a-lpuart";
485 reg = <0x0 0x2960000 0x0 0x1000>;
486 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
487 clocks = <&clockgen 4 1>;
492 lpuart2: serial@2970000 {
493 compatible = "fsl,ls1021a-lpuart";
494 reg = <0x0 0x2970000 0x0 0x1000>;
495 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
496 clocks = <&clockgen 4 1>;
501 lpuart3: serial@2980000 {
502 compatible = "fsl,ls1021a-lpuart";
503 reg = <0x0 0x2980000 0x0 0x1000>;
504 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
505 clocks = <&clockgen 4 1>;
510 lpuart4: serial@2990000 {
511 compatible = "fsl,ls1021a-lpuart";
512 reg = <0x0 0x2990000 0x0 0x1000>;
513 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
514 clocks = <&clockgen 4 1>;
519 lpuart5: serial@29a0000 {
520 compatible = "fsl,ls1021a-lpuart";
521 reg = <0x0 0x29a0000 0x0 0x1000>;
522 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
523 clocks = <&clockgen 4 1>;
528 wdog0: watchdog@2ad0000 {
529 compatible = "fsl,imx21-wdt";
530 reg = <0x0 0x2ad0000 0x0 0x10000>;
531 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
532 clocks = <&clockgen 4 1>;
533 clock-names = "wdog-en";
538 #sound-dai-cells = <0>;
539 compatible = "fsl,vf610-sai";
540 reg = <0x0 0x2b50000 0x0 0x10000>;
541 interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
542 clocks = <&clockgen 4 1>, <&clockgen 4 1>,
543 <&clockgen 4 1>, <&clockgen 4 1>;
544 clock-names = "bus", "mclk1", "mclk2", "mclk3";
545 dma-names = "tx", "rx";
546 dmas = <&edma0 1 47>,
552 #sound-dai-cells = <0>;
553 compatible = "fsl,vf610-sai";
554 reg = <0x0 0x2b60000 0x0 0x10000>;
555 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
556 clocks = <&clockgen 4 1>, <&clockgen 4 1>,
557 <&clockgen 4 1>, <&clockgen 4 1>;
558 clock-names = "bus", "mclk1", "mclk2", "mclk3";
559 dma-names = "tx", "rx";
560 dmas = <&edma0 1 45>,
565 edma0: edma@2c00000 {
567 compatible = "fsl,vf610-edma";
568 reg = <0x0 0x2c00000 0x0 0x10000>,
569 <0x0 0x2c10000 0x0 0x10000>,
570 <0x0 0x2c20000 0x0 0x10000>;
571 interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
572 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>;
573 interrupt-names = "edma-tx", "edma-err";
576 clock-names = "dmamux0", "dmamux1";
577 clocks = <&clockgen 4 1>,
582 compatible = "fsl,ls1021a-dcu";
583 reg = <0x0 0x2ce0000 0x0 0x10000>;
584 interrupts = <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>;
585 clocks = <&clockgen 4 0>,
587 clock-names = "dcu", "pix";
592 mdio0: mdio@2d24000 {
593 compatible = "gianfar";
594 device_type = "mdio";
595 #address-cells = <1>;
597 reg = <0x0 0x2d24000 0x0 0x4000>,
598 <0x0 0x2d10030 0x0 0x4>;
602 compatible = "fsl,etsec-ptp";
603 reg = <0x0 0x2d10e00 0x0 0xb0>;
604 interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
605 fsl,tclk-period = <5>;
607 fsl,tmr-add = <0xaaaaaaab>;
608 fsl,tmr-fiper1 = <999999995>;
609 fsl,tmr-fiper2 = <99990>;
610 fsl,max-adj = <499999999>;
613 enet0: ethernet@2d10000 {
614 compatible = "fsl,etsec2";
615 device_type = "network";
616 #address-cells = <2>;
618 interrupt-parent = <&gic>;
624 queue-group@2d10000 {
625 #address-cells = <2>;
627 reg = <0x0 0x2d10000 0x0 0x1000>;
628 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
629 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
630 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
633 queue-group@2d14000 {
634 #address-cells = <2>;
636 reg = <0x0 0x2d14000 0x0 0x1000>;
637 interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
638 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
639 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
643 enet1: ethernet@2d50000 {
644 compatible = "fsl,etsec2";
645 device_type = "network";
646 #address-cells = <2>;
648 interrupt-parent = <&gic>;
653 queue-group@2d50000 {
654 #address-cells = <2>;
656 reg = <0x0 0x2d50000 0x0 0x1000>;
657 interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>,
658 <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
659 <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
662 queue-group@2d54000 {
663 #address-cells = <2>;
665 reg = <0x0 0x2d54000 0x0 0x1000>;
666 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
667 <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
668 <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
672 enet2: ethernet@2d90000 {
673 compatible = "fsl,etsec2";
674 device_type = "network";
675 #address-cells = <2>;
677 interrupt-parent = <&gic>;
682 queue-group@2d90000 {
683 #address-cells = <2>;
685 reg = <0x0 0x2d90000 0x0 0x1000>;
686 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
687 <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>,
688 <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
691 queue-group@2d94000 {
692 #address-cells = <2>;
694 reg = <0x0 0x2d94000 0x0 0x1000>;
695 interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
696 <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
697 <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
702 compatible = "fsl-usb2-dr-v2.5", "fsl-usb2-dr";
703 reg = <0x0 0x8600000 0x0 0x1000>;
704 interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>;
710 compatible = "snps,dwc3";
711 reg = <0x0 0x3100000 0x0 0x10000>;
712 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
714 snps,quirk-frame-length-adjustment = <0x20>;
715 snps,dis_rxdet_inp3_quirk;
719 compatible = "fsl,ls1021a-pcie", "snps,dw-pcie";
720 reg = <0x00 0x03400000 0x0 0x00010000 /* controller registers */
721 0x40 0x00000000 0x0 0x00002000>; /* configuration space */
722 reg-names = "regs", "config";
723 interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
724 fsl,pcie-scfg = <&scfg 0>;
725 #address-cells = <3>;
729 bus-range = <0x0 0xff>;
730 ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000 /* downstream I/O */
731 0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
732 msi-parent = <&msi1>, <&msi2>;
733 #interrupt-cells = <1>;
734 interrupt-map-mask = <0 0 0 7>;
735 interrupt-map = <0000 0 0 1 &gic GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,
736 <0000 0 0 2 &gic GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
737 <0000 0 0 3 &gic GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
738 <0000 0 0 4 &gic GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>;
742 compatible = "fsl,ls1021a-pcie", "snps,dw-pcie";
743 reg = <0x00 0x03500000 0x0 0x00010000 /* controller registers */
744 0x48 0x00000000 0x0 0x00002000>; /* configuration space */
745 reg-names = "regs", "config";
746 interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;
747 fsl,pcie-scfg = <&scfg 1>;
748 #address-cells = <3>;
752 bus-range = <0x0 0xff>;
753 ranges = <0x81000000 0x0 0x00000000 0x48 0x00010000 0x0 0x00010000 /* downstream I/O */
754 0x82000000 0x0 0x40000000 0x48 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
755 msi-parent = <&msi1>, <&msi2>;
756 #interrupt-cells = <1>;
757 interrupt-map-mask = <0 0 0 7>;
758 interrupt-map = <0000 0 0 1 &gic GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>,
759 <0000 0 0 2 &gic GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
760 <0000 0 0 3 &gic GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
761 <0000 0 0 4 &gic GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
765 compatible = "fsl,ls1021ar2-flexcan";
766 reg = <0x0 0x2a70000 0x0 0x1000>;
767 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
768 clocks = <&clockgen 4 1>, <&clockgen 4 1>;
769 clock-names = "ipg", "per";
774 compatible = "fsl,ls1021ar2-flexcan";
775 reg = <0x0 0x2a80000 0x0 0x1000>;
776 interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
777 clocks = <&clockgen 4 1>, <&clockgen 4 1>;
778 clock-names = "ipg", "per";
783 compatible = "fsl,ls1021ar2-flexcan";
784 reg = <0x0 0x2a90000 0x0 0x1000>;
785 interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>;
786 clocks = <&clockgen 4 1>, <&clockgen 4 1>;
787 clock-names = "ipg", "per";
792 compatible = "fsl,ls1021ar2-flexcan";
793 reg = <0x0 0x2aa0000 0x0 0x1000>;
794 interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>;
795 clocks = <&clockgen 4 1>, <&clockgen 4 1>;
796 clock-names = "ipg", "per";
800 ocram1: sram@10000000 {
801 compatible = "mmio-sram";
802 reg = <0x0 0x10000000 0x0 0x10000>;
803 #address-cells = <1>;
805 ranges = <0x0 0x0 0x10000000 0x10000>;
808 ocram2: sram@10010000 {
809 compatible = "mmio-sram";
810 reg = <0x0 0x10010000 0x0 0x10000>;
811 #address-cells = <1>;
813 ranges = <0x0 0x0 0x10010000 0x10000>;