2 * Copyright 2014 Carlo Caione <carlo@caione.org>
4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual
6 * licensing only applies to this file, and not this project as a
9 * a) This library is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of the
12 * License, or (at your option) any later version.
14 * This library is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program. If not, see <http://www.gnu.org/licenses/>.
24 * b) Permission is hereby granted, free of charge, to any person
25 * obtaining a copy of this software and associated documentation
26 * files (the "Software"), to deal in the Software without
27 * restriction, including without limitation the rights to use,
28 * copy, modify, merge, publish, distribute, sublicense, and/or
29 * sell copies of the Software, and to permit persons to whom the
30 * Software is furnished to do so, subject to the following
33 * The above copyright notice and this permission notice shall be
34 * included in all copies or substantial portions of the Software.
36 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
37 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
38 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
39 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
40 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
41 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
42 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
43 * OTHER DEALINGS IN THE SOFTWARE.
46 #include <dt-bindings/clock/meson8b-clkc.h>
47 #include <dt-bindings/gpio/meson8-gpio.h>
48 #include <dt-bindings/reset/amlogic,meson8b-clkc-reset.h>
49 #include <dt-bindings/reset/amlogic,meson8b-reset.h>
53 model = "Amlogic Meson8 SoC";
54 compatible = "amlogic,meson8";
62 compatible = "arm,cortex-a9";
63 next-level-cache = <&L2>;
65 enable-method = "amlogic,meson8-smp";
66 resets = <&clkc CLKC_RESET_CPU0_SOFT_RESET>;
67 operating-points-v2 = <&cpu_opp_table>;
68 clocks = <&clkc CLKID_CPUCLK>;
73 compatible = "arm,cortex-a9";
74 next-level-cache = <&L2>;
76 enable-method = "amlogic,meson8-smp";
77 resets = <&clkc CLKC_RESET_CPU1_SOFT_RESET>;
78 operating-points-v2 = <&cpu_opp_table>;
79 clocks = <&clkc CLKID_CPUCLK>;
84 compatible = "arm,cortex-a9";
85 next-level-cache = <&L2>;
87 enable-method = "amlogic,meson8-smp";
88 resets = <&clkc CLKC_RESET_CPU2_SOFT_RESET>;
89 operating-points-v2 = <&cpu_opp_table>;
90 clocks = <&clkc CLKID_CPUCLK>;
95 compatible = "arm,cortex-a9";
96 next-level-cache = <&L2>;
98 enable-method = "amlogic,meson8-smp";
99 resets = <&clkc CLKC_RESET_CPU3_SOFT_RESET>;
100 operating-points-v2 = <&cpu_opp_table>;
101 clocks = <&clkc CLKID_CPUCLK>;
105 cpu_opp_table: opp-table {
106 compatible = "operating-points-v2";
110 opp-hz = /bits/ 64 <96000000>;
111 opp-microvolt = <825000>;
114 opp-hz = /bits/ 64 <192000000>;
115 opp-microvolt = <825000>;
118 opp-hz = /bits/ 64 <312000000>;
119 opp-microvolt = <825000>;
122 opp-hz = /bits/ 64 <408000000>;
123 opp-microvolt = <825000>;
126 opp-hz = /bits/ 64 <504000000>;
127 opp-microvolt = <825000>;
130 opp-hz = /bits/ 64 <600000000>;
131 opp-microvolt = <850000>;
134 opp-hz = /bits/ 64 <720000000>;
135 opp-microvolt = <850000>;
138 opp-hz = /bits/ 64 <816000000>;
139 opp-microvolt = <875000>;
142 opp-hz = /bits/ 64 <1008000000>;
143 opp-microvolt = <925000>;
146 opp-hz = /bits/ 64 <1200000000>;
147 opp-microvolt = <975000>;
150 opp-hz = /bits/ 64 <1416000000>;
151 opp-microvolt = <1025000>;
154 opp-hz = /bits/ 64 <1608000000>;
155 opp-microvolt = <1100000>;
159 opp-hz = /bits/ 64 <1800000000>;
160 opp-microvolt = <1125000>;
164 opp-hz = /bits/ 64 <1992000000>;
165 opp-microvolt = <1150000>;
169 gpu_opp_table: gpu-opp-table {
170 compatible = "operating-points-v2";
173 opp-hz = /bits/ 64 <182150000>;
174 opp-microvolt = <1150000>;
177 opp-hz = /bits/ 64 <318750000>;
178 opp-microvolt = <1150000>;
181 opp-hz = /bits/ 64 <425000000>;
182 opp-microvolt = <1150000>;
185 opp-hz = /bits/ 64 <510000000>;
186 opp-microvolt = <1150000>;
189 opp-hz = /bits/ 64 <637500000>;
190 opp-microvolt = <1150000>;
196 compatible = "arm,cortex-a9-pmu";
197 interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
198 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
199 <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
200 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
201 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
205 #address-cells = <1>;
209 /* 2 MiB reserved for Hardware ROM Firmware? */
211 reg = <0x0 0x200000>;
216 * 1 MiB reserved for the "ARM Power Firmware": this is ARM
217 * code which is responsible for system suspend. It loads a
218 * piece of ARC code ("arc_power" in the vendor u-boot tree)
219 * into SRAM, executes that and shuts down the (last) ARM core.
220 * The arc_power firmware then checks various wakeup sources
221 * (IR remote receiver, HDMI CEC, WIFI and Bluetooth wakeup or
222 * simply the power key) and re-starts the ARM core once it
223 * detects a wakeup request.
225 power-firmware@4f00000 {
226 reg = <0x4f00000 0x100000>;
232 compatible = "simple-bus";
233 reg = <0xd0000000 0x200000>;
234 #address-cells = <1>;
236 ranges = <0x0 0xd0000000 0x200000>;
239 compatible = "amlogic,meson8-mali", "arm,mali-450";
240 reg = <0xc0000 0x40000>;
241 interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
242 <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
243 <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>,
244 <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
245 <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>,
246 <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>,
247 <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>,
248 <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>,
249 <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
250 <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>,
251 <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>,
252 <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>,
253 <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>,
254 <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>,
255 <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>,
256 <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>,
257 <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>,
258 <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>;
259 interrupt-names = "gp", "gpmmu", "pp", "pmu",
260 "pp0", "ppmmu0", "pp1", "ppmmu1",
261 "pp2", "ppmmu2", "pp4", "ppmmu4",
262 "pp5", "ppmmu5", "pp6", "ppmmu6";
263 resets = <&reset RESET_MALI>;
264 clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_MALI>;
265 clock-names = "bus", "core";
266 operating-points-v2 = <&gpu_opp_table>;
267 switch-delay = <0xffff>;
274 compatible = "amlogic,meson8-pmu", "syscon";
278 pinctrl_aobus: pinctrl@84 {
279 compatible = "amlogic,meson8-aobus-pinctrl";
281 #address-cells = <1>;
285 gpio_ao: ao-bank@14 {
289 reg-names = "mux", "pull", "gpio";
292 gpio-ranges = <&pinctrl_aobus 0 0 16>;
295 uart_ao_a_pins: uart_ao_a {
297 groups = "uart_tx_ao_a", "uart_rx_ao_a";
298 function = "uart_ao";
303 i2c_ao_pins: i2c_mst_ao {
305 groups = "i2c_mst_sck_ao", "i2c_mst_sda_ao";
306 function = "i2c_mst_ao";
311 ir_recv_pins: remote {
313 groups = "remote_input";
319 pwm_f_ao_pins: pwm-f-ao {
322 function = "pwm_f_ao";
330 reset: reset-controller@4404 {
331 compatible = "amlogic,meson8b-reset";
336 analog_top: analog-top@81a8 {
337 compatible = "amlogic,meson8-analog-top", "syscon";
342 compatible = "amlogic,meson8-pwm", "amlogic,meson8b-pwm";
348 pinctrl_cbus: pinctrl@9880 {
349 compatible = "amlogic,meson8-cbus-pinctrl";
351 #address-cells = <1>;
360 reg-names = "mux", "pull", "pull-enable", "gpio";
363 gpio-ranges = <&pinctrl_cbus 0 0 120>;
368 groups = "sd_d0_a", "sd_d1_a", "sd_d2_a",
369 "sd_d3_a", "sd_clk_a", "sd_cmd_a";
377 groups = "sd_d0_b", "sd_d1_b", "sd_d2_b",
378 "sd_d3_b", "sd_clk_b", "sd_cmd_b";
386 groups = "sd_d0_c", "sd_d1_c", "sd_d2_c",
387 "sd_d3_c", "sd_clk_c", "sd_cmd_c";
395 groups = "nor_d", "nor_q", "nor_c", "nor_cs";
403 groups = "eth_tx_clk_50m", "eth_tx_en",
404 "eth_txd1", "eth_txd0",
405 "eth_rx_clk_in", "eth_rx_dv",
406 "eth_rxd1", "eth_rxd0", "eth_mdio",
408 function = "ethernet";
421 uart_a1_pins: uart-a1 {
423 groups = "uart_tx_a1",
430 uart_a1_cts_rts_pins: uart-a1-cts-rts {
432 groups = "uart_cts_a1",
443 compatible = "amlogic,meson8-smp-sram";
449 compatible = "amlogic,meson8-efuse";
450 clocks = <&clkc CLKID_EFUSE>;
451 clock-names = "core";
453 temperature_calib: calib@1f4 {
454 /* only the upper two bytes are relevant */
460 clocks = <&clkc CLKID_ETH>;
461 clock-names = "stmmaceth";
465 compatible = "amlogic,meson8-gpio-intc", "amlogic,meson-gpio-intc";
470 clkc: clock-controller {
471 compatible = "amlogic,meson8-clkc";
478 compatible = "amlogic,meson8-rng", "amlogic,meson-rng";
479 clocks = <&clkc CLKID_RNG0>;
480 clock-names = "core";
484 clocks = <&clkc CLKID_CLK81>;
488 clocks = <&clkc CLKID_CLK81>;
492 clocks = <&clkc CLKID_CLK81>;
496 arm,data-latency = <3 3 3>;
497 arm,tag-latency = <2 2 2>;
498 arm,filter-ranges = <0x100000 0xc0000000>;
500 prefetch-instr = <1>;
506 compatible = "arm,cortex-a9-scu";
511 compatible = "arm,cortex-a9-global-timer";
513 interrupts = <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>;
514 clocks = <&clkc CLKID_PERIPH>;
517 * the arm_global_timer driver currently does not handle clock
518 * rate changes. Keep it disabled for now.
524 compatible = "arm,cortex-a9-twd-timer";
526 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>;
527 clocks = <&clkc CLKID_PERIPH>;
532 compatible = "amlogic,meson8-pwm", "amlogic,meson8b-pwm";
536 compatible = "amlogic,meson8-pwm", "amlogic,meson8b-pwm";
540 compatible = "amlogic,meson8-saradc", "amlogic,meson-saradc";
541 clocks = <&clkc CLKID_XTAL>,
542 <&clkc CLKID_SAR_ADC>;
543 clock-names = "clkin", "core";
544 amlogic,hhi-sysctrl = <&hhi>;
545 nvmem-cells = <&temperature_calib>;
546 nvmem-cell-names = "temperature_calib";
550 compatible = "amlogic,meson8-sdio", "amlogic,meson-mx-sdio";
551 clocks = <&clkc CLKID_SDIO>, <&clkc CLKID_CLK81>;
552 clock-names = "core", "clkin";
556 clocks = <&clkc CLKID_CLK81>;
560 clocks = <&clkc CLKID_XTAL>, <&clkc CLKID_CLK81>;
561 clock-names = "xtal", "pclk";
565 compatible = "amlogic,meson8-uart", "amlogic,meson-uart";
566 clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_XTAL>, <&clkc CLKID_CLK81>;
567 clock-names = "baud", "xtal", "pclk";
571 compatible = "amlogic,meson8-uart", "amlogic,meson-uart";
572 clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_XTAL>, <&clkc CLKID_UART0>;
573 clock-names = "baud", "xtal", "pclk";
577 compatible = "amlogic,meson8-uart", "amlogic,meson-uart";
578 clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_XTAL>, <&clkc CLKID_UART1>;
579 clock-names = "baud", "xtal", "pclk";
583 compatible = "amlogic,meson8-uart", "amlogic,meson-uart";
584 clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_XTAL>, <&clkc CLKID_UART2>;
585 clock-names = "baud", "xtal", "pclk";
589 compatible = "amlogic,meson8-usb", "snps,dwc2";
590 clocks = <&clkc CLKID_USB0_DDR_BRIDGE>;
595 compatible = "amlogic,meson8-usb", "snps,dwc2";
596 clocks = <&clkc CLKID_USB1_DDR_BRIDGE>;
601 compatible = "amlogic,meson8-usb2-phy", "amlogic,meson-mx-usb2-phy";
602 clocks = <&clkc CLKID_USB>, <&clkc CLKID_USB0>;
603 clock-names = "usb_general", "usb";
604 resets = <&reset RESET_USB_OTG>;
608 compatible = "amlogic,meson8-usb2-phy", "amlogic,meson-mx-usb2-phy";
609 clocks = <&clkc CLKID_USB>, <&clkc CLKID_USB1>;
610 clock-names = "usb_general", "usb";
611 resets = <&reset RESET_USB_OTG>;