sys/gnu/dts/arm/meson8.dtsi

   1 /*
   2  * Copyright 2014 Carlo Caione <carlo@caione.org>
   3  *
   4  * This file is dual-licensed: you can use it either under the terms
   5  * of the GPL or the X11 license, at your option. Note that this dual
   6  * licensing only applies to this file, and not this project as a
   7  * whole.
   8  *
   9  *  a) This library is free software; you can redistribute it and/or
  10  *     modify it under the terms of the GNU General Public License as
  11  *     published by the Free Software Foundation; either version 2 of the
  12  *     License, or (at your option) any later version.
  13  *
  14  *     This library is distributed in the hope that it will be useful,
  15  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  *     GNU General Public License for more details.
  18  *
  19  *     You should have received a copy of the GNU General Public License
  20  *     along with this program. If not, see <http://www.gnu.org/licenses/>.
  21  *
  22  * Or, alternatively,
  23  *
  24  *  b) Permission is hereby granted, free of charge, to any person
  25  *     obtaining a copy of this software and associated documentation
  26  *     files (the "Software"), to deal in the Software without
  27  *     restriction, including without limitation the rights to use,
  28  *     copy, modify, merge, publish, distribute, sublicense, and/or
  29  *     sell copies of the Software, and to permit persons to whom the
  30  *     Software is furnished to do so, subject to the following
  31  *     conditions:
  32  *
  33  *     The above copyright notice and this permission notice shall be
  34  *     included in all copies or substantial portions of the Software.
  35  *
  36  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  37  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  38  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  39  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  40  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  41  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  42  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  43  *     OTHER DEALINGS IN THE SOFTWARE.
  44  */
  45
  46 #include <dt-bindings/clock/meson8b-clkc.h>
  47 #include <dt-bindings/gpio/meson8-gpio.h>
  48 #include <dt-bindings/reset/amlogic,meson8b-clkc-reset.h>
  49 #include <dt-bindings/reset/amlogic,meson8b-reset.h>
  50 #include "meson.dtsi"
  51
  52 / {
  53         model = "Amlogic Meson8 SoC";
  54         compatible = "amlogic,meson8";
  55
  56         cpus {
  57                 #address-cells = <1>;
  58                 #size-cells = <0>;
  59
  60                 cpu@200 {
  61                         device_type = "cpu";
  62                         compatible = "arm,cortex-a9";
  63                         next-level-cache = <&L2>;
  64                         reg = <0x200>;
  65                         enable-method = "amlogic,meson8-smp";
  66                         resets = <&clkc CLKC_RESET_CPU0_SOFT_RESET>;
  67                 };
  68
  69                 cpu@201 {
  70                         device_type = "cpu";
  71                         compatible = "arm,cortex-a9";
  72                         next-level-cache = <&L2>;
  73                         reg = <0x201>;
  74                         enable-method = "amlogic,meson8-smp";
  75                         resets = <&clkc CLKC_RESET_CPU1_SOFT_RESET>;
  76                 };
  77
  78                 cpu@202 {
  79                         device_type = "cpu";
  80                         compatible = "arm,cortex-a9";
  81                         next-level-cache = <&L2>;
  82                         reg = <0x202>;
  83                         enable-method = "amlogic,meson8-smp";
  84                         resets = <&clkc CLKC_RESET_CPU2_SOFT_RESET>;
  85                 };
  86
  87                 cpu@203 {
  88                         device_type = "cpu";
  89                         compatible = "arm,cortex-a9";
  90                         next-level-cache = <&L2>;
  91                         reg = <0x203>;
  92                         enable-method = "amlogic,meson8-smp";
  93                         resets = <&clkc CLKC_RESET_CPU3_SOFT_RESET>;
  94                 };
  95         };
  96
  97         reserved-memory {
  98                 #address-cells = <1>;
  99                 #size-cells = <1>;
 100                 ranges;
 101
 102                 /* 2 MiB reserved for Hardware ROM Firmware? */
 103                 hwrom@0 {
 104                         reg = <0x0 0x200000>;
 105                         no-map;
 106                 };
 107
 108                 /*
 109                  * 1 MiB reserved for the "ARM Power Firmware": this is ARM
 110                  * code which is responsible for system suspend. It loads a
 111                  * piece of ARC code ("arc_power" in the vendor u-boot tree)
 112                  * into SRAM, executes that and shuts down the (last) ARM core.
 113                  * The arc_power firmware then checks various wakeup sources
 114                  * (IR remote receiver, HDMI CEC, WIFI and Bluetooth wakeup or
 115                  * simply the power key) and re-starts the ARM core once it
 116                  * detects a wakeup request.
 117                  */
 118                 power-firmware@4f00000 {
 119                         reg = <0x4f00000 0x100000>;
 120                         no-map;
 121                 };
 122         };
 123
 124         scu@c4300000 {
 125                 compatible = "arm,cortex-a9-scu";
 126                 reg = <0xc4300000 0x100>;
 127         };
 128 }; /* end of / */
 129
 130 &aobus {
 131         pmu: pmu@e0 {
 132                 compatible = "amlogic,meson8-pmu", "syscon";
 133                 reg = <0xe0 0x8>;
 134         };
 135
 136         pinctrl_aobus: pinctrl@84 {
 137                 compatible = "amlogic,meson8-aobus-pinctrl";
 138                 reg = <0x84 0xc>;
 139                 #address-cells = <1>;
 140                 #size-cells = <1>;
 141                 ranges;
 142
 143                 gpio_ao: ao-bank@14 {
 144                         reg = <0x14 0x4>,
 145                               <0x2c 0x4>,
 146                               <0x24 0x8>;
 147                         reg-names = "mux", "pull", "gpio";
 148                         gpio-controller;
 149                         #gpio-cells = <2>;
 150                         gpio-ranges = <&pinctrl_aobus 0 0 16>;
 151                 };
 152
 153                 uart_ao_a_pins: uart_ao_a {
 154                         mux {
 155                                 groups = "uart_tx_ao_a", "uart_rx_ao_a";
 156                                 function = "uart_ao";
 157                         };
 158                 };
 159
 160                 i2c_ao_pins: i2c_mst_ao {
 161                         mux {
 162                                 groups = "i2c_mst_sck_ao", "i2c_mst_sda_ao";
 163                                 function = "i2c_mst_ao";
 164                         };
 165                 };
 166
 167                 ir_recv_pins: remote {
 168                         mux {
 169                                 groups = "remote_input";
 170                                 function = "remote";
 171                         };
 172                 };
 173
 174                 pwm_f_ao_pins: pwm-f-ao {
 175                         mux {
 176                                 groups = "pwm_f_ao";
 177                                 function = "pwm_f_ao";
 178                         };
 179                 };
 180         };
 181 };
 182
 183 &cbus {
 184         clkc: clock-controller@4000 {
 185                 #clock-cells = <1>;
 186                 #reset-cells = <1>;
 187                 compatible = "amlogic,meson8-clkc";
 188                 reg = <0x8000 0x4>, <0x4000 0x460>;
 189         };
 190
 191         reset: reset-controller@4404 {
 192                 compatible = "amlogic,meson8b-reset";
 193                 reg = <0x4404 0x9c>;
 194                 #reset-cells = <1>;
 195         };
 196
 197         analog_top: analog-top@81a8 {
 198                 compatible = "amlogic,meson8-analog-top", "syscon";
 199                 reg = <0x81a8 0x14>;
 200         };
 201
 202         pwm_ef: pwm@86c0 {
 203                 compatible = "amlogic,meson8-pwm", "amlogic,meson8b-pwm";
 204                 reg = <0x86c0 0x10>;
 205                 #pwm-cells = <3>;
 206                 status = "disabled";
 207         };
 208
 209         pinctrl_cbus: pinctrl@9880 {
 210                 compatible = "amlogic,meson8-cbus-pinctrl";
 211                 reg = <0x9880 0x10>;
 212                 #address-cells = <1>;
 213                 #size-cells = <1>;
 214                 ranges;
 215
 216                 gpio: banks@80b0 {
 217                         reg = <0x80b0 0x28>,
 218                               <0x80e8 0x18>,
 219                               <0x8120 0x18>,
 220                               <0x8030 0x30>;
 221                         reg-names = "mux", "pull", "pull-enable", "gpio";
 222                         gpio-controller;
 223                         #gpio-cells = <2>;
 224                         gpio-ranges = <&pinctrl_cbus 0 0 120>;
 225                 };
 226
 227                 sd_a_pins: sd-a {
 228                         mux {
 229                                 groups = "sd_d0_a", "sd_d1_a", "sd_d2_a",
 230                                         "sd_d3_a", "sd_clk_a", "sd_cmd_a";
 231                                 function = "sd_a";
 232                         };
 233                 };
 234
 235                 sd_b_pins: sd-b {
 236                         mux {
 237                                 groups = "sd_d0_b", "sd_d1_b", "sd_d2_b",
 238                                         "sd_d3_b", "sd_clk_b", "sd_cmd_b";
 239                                 function = "sd_b";
 240                         };
 241                 };
 242
 243                 sd_c_pins: sd-c {
 244                         mux {
 245                                 groups = "sd_d0_c", "sd_d1_c", "sd_d2_c",
 246                                         "sd_d3_c", "sd_clk_c", "sd_cmd_c";
 247                                 function = "sd_c";
 248                         };
 249                 };
 250
 251                 spi_nor_pins: nor {
 252                         mux {
 253                                 groups = "nor_d", "nor_q", "nor_c", "nor_cs";
 254                                 function = "nor";
 255                         };
 256                 };
 257
 258                 eth_pins: ethernet {
 259                         mux {
 260                                 groups = "eth_tx_clk_50m", "eth_tx_en",
 261                                          "eth_txd1", "eth_txd0",
 262                                          "eth_rx_clk_in", "eth_rx_dv",
 263                                          "eth_rxd1", "eth_rxd0", "eth_mdio",
 264                                          "eth_mdc";
 265                                 function = "ethernet";
 266                         };
 267                 };
 268
 269                 pwm_e_pins: pwm-e {
 270                         mux {
 271                                 groups = "pwm_e";
 272                                 function = "pwm_e";
 273                         };
 274                 };
 275         };
 276 };
 277
 278 &ahb_sram {
 279         smp-sram@1ff80 {
 280                 compatible = "amlogic,meson8-smp-sram";
 281                 reg = <0x1ff80 0x8>;
 282         };
 283 };
 284
 285 &efuse {
 286         compatible = "amlogic,meson8-efuse";
 287         clocks = <&clkc CLKID_EFUSE>;
 288         clock-names = "core";
 289 };
 290
 291 &ethmac {
 292         clocks = <&clkc CLKID_ETH>;
 293         clock-names = "stmmaceth";
 294 };
 295
 296 &gpio_intc {
 297         compatible = "amlogic,meson8-gpio-intc", "amlogic,meson-gpio-intc";
 298         status = "okay";
 299 };
 300
 301 &hwrng {
 302         compatible = "amlogic,meson8-rng", "amlogic,meson-rng";
 303         clocks = <&clkc CLKID_RNG0>;
 304         clock-names = "core";
 305 };
 306
 307 &i2c_AO {
 308         clocks = <&clkc CLKID_CLK81>;
 309 };
 310
 311 &i2c_A {
 312         clocks = <&clkc CLKID_CLK81>;
 313 };
 314
 315 &i2c_B {
 316         clocks = <&clkc CLKID_CLK81>;
 317 };
 318
 319 &L2 {
 320         arm,data-latency = <3 3 3>;
 321         arm,tag-latency = <2 2 2>;
 322         arm,filter-ranges = <0x100000 0xc0000000>;
 323         prefetch-data = <1>;
 324         prefetch-instr = <1>;
 325         arm,shared-override;
 326 };
 327
 328 &pwm_ab {
 329         compatible = "amlogic,meson8-pwm", "amlogic,meson8b-pwm";
 330 };
 331
 332 &pwm_cd {
 333         compatible = "amlogic,meson8-pwm", "amlogic,meson8b-pwm";
 334 };
 335
 336 &saradc {
 337         compatible = "amlogic,meson8-saradc", "amlogic,meson-saradc";
 338         clocks = <&clkc CLKID_XTAL>,
 339                 <&clkc CLKID_SAR_ADC>;
 340         clock-names = "clkin", "core";
 341 };
 342
 343 &sdio {
 344         compatible = "amlogic,meson8-sdio", "amlogic,meson-mx-sdio";
 345         clocks = <&clkc CLKID_SDIO>, <&clkc CLKID_CLK81>;
 346         clock-names = "core", "clkin";
 347 };
 348
 349 &spifc {
 350         clocks = <&clkc CLKID_CLK81>;
 351 };
 352
 353 &uart_AO {
 354         compatible = "amlogic,meson8-uart", "amlogic,meson-uart";
 355         clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_XTAL>, <&clkc CLKID_CLK81>;
 356         clock-names = "baud", "xtal", "pclk";
 357 };
 358
 359 &uart_A {
 360         compatible = "amlogic,meson8-uart", "amlogic,meson-uart";
 361         clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_XTAL>, <&clkc CLKID_UART0>;
 362         clock-names = "baud", "xtal", "pclk";
 363 };
 364
 365 &uart_B {
 366         compatible = "amlogic,meson8-uart", "amlogic,meson-uart";
 367         clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_XTAL>, <&clkc CLKID_UART1>;
 368         clock-names = "baud", "xtal", "pclk";
 369 };
 370
 371 &uart_C {
 372         compatible = "amlogic,meson8-uart", "amlogic,meson-uart";
 373         clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_XTAL>, <&clkc CLKID_UART2>;
 374         clock-names = "baud", "xtal", "pclk";
 375 };
 376
 377 &usb0 {
 378         compatible = "amlogic,meson8-usb", "snps,dwc2";
 379         clocks = <&clkc CLKID_USB0_DDR_BRIDGE>;
 380         clock-names = "otg";
 381 };
 382
 383 &usb1 {
 384         compatible = "amlogic,meson8-usb", "snps,dwc2";
 385         clocks = <&clkc CLKID_USB1_DDR_BRIDGE>;
 386         clock-names = "otg";
 387 };
 388
 389 &usb0_phy {
 390         compatible = "amlogic,meson8-usb2-phy", "amlogic,meson-mx-usb2-phy";
 391         clocks = <&clkc CLKID_USB>, <&clkc CLKID_USB0>;
 392         clock-names = "usb_general", "usb";
 393         resets = <&reset RESET_USB_OTG>;
 394 };
 395
 396 &usb1_phy {
 397         compatible = "amlogic,meson8-usb2-phy", "amlogic,meson-mx-usb2-phy";
 398         clocks = <&clkc CLKID_USB>, <&clkc CLKID_USB1>;
 399         clock-names = "usb_general", "usb";
 400         resets = <&reset RESET_USB_OTG>;
 401 };