1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Copyright (c) 2017 Martin Blumenstingl <martin.blumenstingl@googlemail.com>.
9 model = "Amlogic Meson8m2 SoC";
10 compatible = "amlogic,meson8m2";
14 compatible = "amlogic,meson8m2-clkc", "amlogic,meson8-clkc";
18 /* the offset of the canvas registers has changed compared to Meson8 */
19 /delete-node/ video-lut@20;
21 canvas: video-lut@48 {
22 compatible = "amlogic,meson8m2-canvas", "amlogic,canvas";
28 compatible = "amlogic,meson8m2-dwmac", "snps,dwmac";
29 reg = <0xc9410000 0x10000
31 clocks = <&clkc CLKID_ETH>,
34 <&clkc CLKID_FCLK_DIV2>;
35 clock-names = "stmmaceth", "clkin0", "clkin1", "timing-adjustment";
36 resets = <&reset RESET_ETHERNET>;
37 reset-names = "stmmaceth";
41 compatible = "amlogic,meson8m2-aobus-pinctrl",
42 "amlogic,meson8-aobus-pinctrl";
46 compatible = "amlogic,meson8m2-cbus-pinctrl",
47 "amlogic,meson8-cbus-pinctrl";
49 eth_rgmii_pins: ethernet {
51 groups = "eth_tx_clk_50m", "eth_tx_en",
52 "eth_txd3", "eth_txd2",
53 "eth_txd1", "eth_txd0",
54 "eth_rx_clk_in", "eth_rx_dv",
55 "eth_rxd3", "eth_rxd2",
56 "eth_rxd1", "eth_rxd0",
57 "eth_mdio", "eth_mdc";
58 function = "ethernet";
65 compatible = "amlogic,meson8m2-saradc", "amlogic,meson-saradc";
69 compatible = "amlogic,meson8m2-usb2-phy", "amlogic,meson-mx-usb2-phy";
73 compatible = "amlogic,meson8m2-usb2-phy", "amlogic,meson-mx-usb2-phy";
77 compatible = "amlogic,meson8m2-wdt", "amlogic,meson8b-wdt";