sys/gnu/dts/arm/mmp2.dtsi

   1 /*
   2  *  Copyright (C) 2012 Marvell Technology Group Ltd.
   3  *  Author: Haojian Zhuang <haojian.zhuang@marvell.com>
   4  *
   5  *  This program is free software; you can redistribute it and/or modify
   6  *  it under the terms of the GNU General Public License version 2 as
   7  *  publishhed by the Free Software Foundation.
   8  */
   9
  10 #include "skeleton.dtsi"
  11 #include <dt-bindings/clock/marvell,mmp2.h>
  12
  13 / {
  14         aliases {
  15                 serial0 = &uart1;
  16                 serial1 = &uart2;
  17                 serial2 = &uart3;
  18                 serial3 = &uart4;
  19                 i2c0 = &twsi1;
  20                 i2c1 = &twsi2;
  21         };
  22
  23         soc {
  24                 #address-cells = <1>;
  25                 #size-cells = <1>;
  26                 compatible = "simple-bus";
  27                 interrupt-parent = <&intc>;
  28                 ranges;
  29
  30                 L2: l2-cache {
  31                         compatible = "marvell,tauros2-cache";
  32                         marvell,tauros2-cache-features = <0x3>;
  33                 };
  34
  35                 axi@d4200000 {  /* AXI */
  36                         compatible = "mrvl,axi-bus", "simple-bus";
  37                         #address-cells = <1>;
  38                         #size-cells = <1>;
  39                         reg = <0xd4200000 0x00200000>;
  40                         ranges;
  41
  42                         intc: interrupt-controller@d4282000 {
  43                                 compatible = "mrvl,mmp2-intc";
  44                                 interrupt-controller;
  45                                 #interrupt-cells = <1>;
  46                                 reg = <0xd4282000 0x1000>;
  47                                 mrvl,intc-nr-irqs = <64>;
  48                         };
  49
  50                         intcmux4: interrupt-controller@d4282150 {
  51                                 compatible = "mrvl,mmp2-mux-intc";
  52                                 interrupts = <4>;
  53                                 interrupt-controller;
  54                                 #interrupt-cells = <1>;
  55                                 reg = <0x150 0x4>, <0x168 0x4>;
  56                                 reg-names = "mux status", "mux mask";
  57                                 mrvl,intc-nr-irqs = <2>;
  58                         };
  59
  60                         intcmux5: interrupt-controller@d4282154 {
  61                                 compatible = "mrvl,mmp2-mux-intc";
  62                                 interrupts = <5>;
  63                                 interrupt-controller;
  64                                 #interrupt-cells = <1>;
  65                                 reg = <0x154 0x4>, <0x16c 0x4>;
  66                                 reg-names = "mux status", "mux mask";
  67                                 mrvl,intc-nr-irqs = <2>;
  68                                 mrvl,clr-mfp-irq = <1>;
  69                         };
  70
  71                         intcmux9: interrupt-controller@d4282180 {
  72                                 compatible = "mrvl,mmp2-mux-intc";
  73                                 interrupts = <9>;
  74                                 interrupt-controller;
  75                                 #interrupt-cells = <1>;
  76                                 reg = <0x180 0x4>, <0x17c 0x4>;
  77                                 reg-names = "mux status", "mux mask";
  78                                 mrvl,intc-nr-irqs = <3>;
  79                         };
  80
  81                         intcmux17: interrupt-controller@d4282158 {
  82                                 compatible = "mrvl,mmp2-mux-intc";
  83                                 interrupts = <17>;
  84                                 interrupt-controller;
  85                                 #interrupt-cells = <1>;
  86                                 reg = <0x158 0x4>, <0x170 0x4>;
  87                                 reg-names = "mux status", "mux mask";
  88                                 mrvl,intc-nr-irqs = <5>;
  89                         };
  90
  91                         intcmux35: interrupt-controller@d428215c {
  92                                 compatible = "mrvl,mmp2-mux-intc";
  93                                 interrupts = <35>;
  94                                 interrupt-controller;
  95                                 #interrupt-cells = <1>;
  96                                 reg = <0x15c 0x4>, <0x174 0x4>;
  97                                 reg-names = "mux status", "mux mask";
  98                                 mrvl,intc-nr-irqs = <15>;
  99                         };
 100
 101                         intcmux51: interrupt-controller@d4282160 {
 102                                 compatible = "mrvl,mmp2-mux-intc";
 103                                 interrupts = <51>;
 104                                 interrupt-controller;
 105                                 #interrupt-cells = <1>;
 106                                 reg = <0x160 0x4>, <0x178 0x4>;
 107                                 reg-names = "mux status", "mux mask";
 108                                 mrvl,intc-nr-irqs = <2>;
 109                         };
 110
 111                         intcmux55: interrupt-controller@d4282188 {
 112                                 compatible = "mrvl,mmp2-mux-intc";
 113                                 interrupts = <55>;
 114                                 interrupt-controller;
 115                                 #interrupt-cells = <1>;
 116                                 reg = <0x188 0x4>, <0x184 0x4>;
 117                                 reg-names = "mux status", "mux mask";
 118                                 mrvl,intc-nr-irqs = <2>;
 119                         };
 120
 121                         usb_otg_phy0: usb-otg-phy@d4207000 {
 122                                 compatible = "marvell,mmp2-usb-phy";
 123                                 reg = <0xd4207000 0x40>;
 124                                 #phy-cells = <0>;
 125                                 status = "disabled";
 126                         };
 127
 128                         usb_otg0: usb-otg@d4208000 {
 129                                 compatible = "marvell,pxau2o-ehci";
 130                                 reg = <0xd4208000 0x200>;
 131                                 interrupts = <44>;
 132                                 clocks = <&soc_clocks MMP2_CLK_USB>;
 133                                 clock-names = "USBCLK";
 134                                 phys = <&usb_otg_phy0>;
 135                                 phy-names = "usb";
 136                                 status = "disabled";
 137                         };
 138
 139                         mmc1: mmc@d4280000 {
 140                                 compatible = "mrvl,pxav3-mmc";
 141                                 reg = <0xd4280000 0x120>;
 142                                 clocks = <&soc_clocks MMP2_CLK_SDH0>;
 143                                 clock-names = "io";
 144                                 interrupts = <39>;
 145                                 status = "disabled";
 146                         };
 147
 148                         mmc2: mmc@d4280800 {
 149                                 compatible = "mrvl,pxav3-mmc";
 150                                 reg = <0xd4280800 0x120>;
 151                                 clocks = <&soc_clocks MMP2_CLK_SDH1>;
 152                                 clock-names = "io";
 153                                 interrupts = <52>;
 154                                 status = "disabled";
 155                         };
 156
 157                         mmc3: mmc@d4281000 {
 158                                 compatible = "mrvl,pxav3-mmc";
 159                                 reg = <0xd4281000 0x120>;
 160                                 clocks = <&soc_clocks MMP2_CLK_SDH2>;
 161                                 clock-names = "io";
 162                                 interrupts = <53>;
 163                                 status = "disabled";
 164                         };
 165
 166                         mmc4: mmc@d4281800 {
 167                                 compatible = "mrvl,pxav3-mmc";
 168                                 reg = <0xd4281800 0x120>;
 169                                 clocks = <&soc_clocks MMP2_CLK_SDH3>;
 170                                 clock-names = "io";
 171                                 interrupts = <54>;
 172                                 status = "disabled";
 173                         };
 174                 };
 175
 176                 apb@d4000000 {  /* APB */
 177                         compatible = "mrvl,apb-bus", "simple-bus";
 178                         #address-cells = <1>;
 179                         #size-cells = <1>;
 180                         reg = <0xd4000000 0x00200000>;
 181                         ranges;
 182
 183                         timer0: timer@d4014000 {
 184                                 compatible = "mrvl,mmp-timer";
 185                                 reg = <0xd4014000 0x100>;
 186                                 interrupts = <13>;
 187                                 clocks = <&soc_clocks MMP2_CLK_TIMER>;
 188                         };
 189
 190                         uart1: uart@d4030000 {
 191                                 compatible = "mrvl,mmp-uart";
 192                                 reg = <0xd4030000 0x1000>;
 193                                 interrupts = <27>;
 194                                 clocks = <&soc_clocks MMP2_CLK_UART0>;
 195                                 resets = <&soc_clocks MMP2_CLK_UART0>;
 196                                 status = "disabled";
 197                         };
 198
 199                         uart2: uart@d4017000 {
 200                                 compatible = "mrvl,mmp-uart";
 201                                 reg = <0xd4017000 0x1000>;
 202                                 interrupts = <28>;
 203                                 clocks = <&soc_clocks MMP2_CLK_UART1>;
 204                                 resets = <&soc_clocks MMP2_CLK_UART1>;
 205                                 status = "disabled";
 206                         };
 207
 208                         uart3: uart@d4018000 {
 209                                 compatible = "mrvl,mmp-uart";
 210                                 reg = <0xd4018000 0x1000>;
 211                                 interrupts = <24>;
 212                                 clocks = <&soc_clocks MMP2_CLK_UART2>;
 213                                 resets = <&soc_clocks MMP2_CLK_UART2>;
 214                                 status = "disabled";
 215                         };
 216
 217                         uart4: uart@d4016000 {
 218                                 compatible = "mrvl,mmp-uart";
 219                                 reg = <0xd4016000 0x1000>;
 220                                 interrupts = <46>;
 221                                 clocks = <&soc_clocks MMP2_CLK_UART3>;
 222                                 resets = <&soc_clocks MMP2_CLK_UART3>;
 223                                 status = "disabled";
 224                         };
 225
 226                         gpio: gpio@d4019000 {
 227                                 compatible = "marvell,mmp2-gpio";
 228                                 #address-cells = <1>;
 229                                 #size-cells = <1>;
 230                                 reg = <0xd4019000 0x1000>;
 231                                 gpio-controller;
 232                                 #gpio-cells = <2>;
 233                                 interrupts = <49>;
 234                                 interrupt-names = "gpio_mux";
 235                                 clocks = <&soc_clocks MMP2_CLK_GPIO>;
 236                                 resets = <&soc_clocks MMP2_CLK_GPIO>;
 237                                 interrupt-controller;
 238                                 #interrupt-cells = <2>;
 239                                 ranges;
 240
 241                                 gcb0: gpio@d4019000 {
 242                                         reg = <0xd4019000 0x4>;
 243                                 };
 244
 245                                 gcb1: gpio@d4019004 {
 246                                         reg = <0xd4019004 0x4>;
 247                                 };
 248
 249                                 gcb2: gpio@d4019008 {
 250                                         reg = <0xd4019008 0x4>;
 251                                 };
 252
 253                                 gcb3: gpio@d4019100 {
 254                                         reg = <0xd4019100 0x4>;
 255                                 };
 256
 257                                 gcb4: gpio@d4019104 {
 258                                         reg = <0xd4019104 0x4>;
 259                                 };
 260
 261                                 gcb5: gpio@d4019108 {
 262                                         reg = <0xd4019108 0x4>;
 263                                 };
 264                         };
 265
 266                         twsi1: i2c@d4011000 {
 267                                 compatible = "mrvl,mmp-twsi";
 268                                 reg = <0xd4011000 0x1000>;
 269                                 interrupts = <7>;
 270                                 clocks = <&soc_clocks MMP2_CLK_TWSI0>;
 271                                 resets = <&soc_clocks MMP2_CLK_TWSI0>;
 272                                 #address-cells = <1>;
 273                                 #size-cells = <0>;
 274                                 mrvl,i2c-fast-mode;
 275                                 status = "disabled";
 276                         };
 277
 278                         twsi2: i2c@d4031000 {
 279                                 compatible = "mrvl,mmp-twsi";
 280                                 reg = <0xd4031000 0x1000>;
 281                                 interrupt-parent = <&intcmux17>;
 282                                 interrupts = <0>;
 283                                 clocks = <&soc_clocks MMP2_CLK_TWSI1>;
 284                                 resets = <&soc_clocks MMP2_CLK_TWSI1>;
 285                                 #address-cells = <1>;
 286                                 #size-cells = <0>;
 287                                 status = "disabled";
 288                         };
 289
 290                         twsi3: i2c@d4032000 {
 291                                 compatible = "mrvl,mmp-twsi";
 292                                 reg = <0xd4032000 0x1000>;
 293                                 interrupt-parent = <&intcmux17>;
 294                                 interrupts = <1>;
 295                                 clocks = <&soc_clocks MMP2_CLK_TWSI2>;
 296                                 resets = <&soc_clocks MMP2_CLK_TWSI2>;
 297                                 #address-cells = <1>;
 298                                 #size-cells = <0>;
 299                                 status = "disabled";
 300                         };
 301
 302                         twsi4: i2c@d4033000 {
 303                                 compatible = "mrvl,mmp-twsi";
 304                                 reg = <0xd4033000 0x1000>;
 305                                 interrupt-parent = <&intcmux17>;
 306                                 interrupts = <2>;
 307                                 clocks = <&soc_clocks MMP2_CLK_TWSI3>;
 308                                 resets = <&soc_clocks MMP2_CLK_TWSI3>;
 309                                 #address-cells = <1>;
 310                                 #size-cells = <0>;
 311                                 status = "disabled";
 312                         };
 313
 314
 315                         twsi5: i2c@d4033800 {
 316                                 compatible = "mrvl,mmp-twsi";
 317                                 reg = <0xd4033800 0x1000>;
 318                                 interrupt-parent = <&intcmux17>;
 319                                 interrupts = <3>;
 320                                 clocks = <&soc_clocks MMP2_CLK_TWSI4>;
 321                                 resets = <&soc_clocks MMP2_CLK_TWSI4>;
 322                                 #address-cells = <1>;
 323                                 #size-cells = <0>;
 324                                 status = "disabled";
 325                         };
 326
 327                         twsi6: i2c@d4034000 {
 328                                 compatible = "mrvl,mmp-twsi";
 329                                 reg = <0xd4034000 0x1000>;
 330                                 interrupt-parent = <&intcmux17>;
 331                                 interrupts = <4>;
 332                                 clocks = <&soc_clocks MMP2_CLK_TWSI5>;
 333                                 resets = <&soc_clocks MMP2_CLK_TWSI5>;
 334                                 #address-cells = <1>;
 335                                 #size-cells = <0>;
 336                                 status = "disabled";
 337                         };
 338
 339                         rtc: rtc@d4010000 {
 340                                 compatible = "mrvl,mmp-rtc";
 341                                 reg = <0xd4010000 0x1000>;
 342                                 interrupts = <1 0>;
 343                                 interrupt-names = "rtc 1Hz", "rtc alarm";
 344                                 interrupt-parent = <&intcmux5>;
 345                                 clocks = <&soc_clocks MMP2_CLK_RTC>;
 346                                 resets = <&soc_clocks MMP2_CLK_RTC>;
 347                                 status = "disabled";
 348                         };
 349
 350                         ssp1: ssp@d4035000 {
 351                                 compatible = "marvell,mmp2-ssp";
 352                                 reg = <0xd4035000 0x1000>;
 353                                 clocks = <&soc_clocks MMP2_CLK_SSP0>;
 354                                 interrupts = <0>;
 355                                 status = "disabled";
 356                         };
 357
 358                         ssp2: ssp@d4036000 {
 359                                 compatible = "marvell,mmp2-ssp";
 360                                 reg = <0xd4036000 0x1000>;
 361                                 clocks = <&soc_clocks MMP2_CLK_SSP1>;
 362                                 interrupts = <1>;
 363                                 status = "disabled";
 364                         };
 365
 366                         ssp3: ssp@d4037000 {
 367                                 compatible = "marvell,mmp2-ssp";
 368                                 reg = <0xd4037000 0x1000>;
 369                                 clocks = <&soc_clocks MMP2_CLK_SSP2>;
 370                                 interrupts = <20>;
 371                                 status = "disabled";
 372                         };
 373
 374                         ssp4: ssp@d4039000 {
 375                                 compatible = "marvell,mmp2-ssp";
 376                                 reg = <0xd4039000 0x1000>;
 377                                 clocks = <&soc_clocks MMP2_CLK_SSP3>;
 378                                 interrupts = <21>;
 379                                 status = "disabled";
 380                         };
 381                 };
 382
 383                 soc_clocks: clocks{
 384                         compatible = "marvell,mmp2-clock";
 385                         reg = <0xd4050000 0x1000>,
 386                               <0xd4282800 0x400>,
 387                               <0xd4015000 0x1000>;
 388                         reg-names = "mpmu", "apmu", "apbc";
 389                         #clock-cells = <1>;
 390                         #reset-cells = <1>;
 391                 };
 392         };
 393 };