1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
3 * Copyright (C) 2019 Lubomir Rintel <lkundrak@v3.sk>
6 #include <dt-bindings/clock/marvell,mmp2.h>
7 #include <dt-bindings/interrupt-controller/arm-gic.h>
16 enable-method = "marvell,mmp3-smp";
19 compatible = "marvell,pj4b";
21 next-level-cache = <&l2>;
26 compatible = "marvell,pj4b";
28 next-level-cache = <&l2>;
36 compatible = "simple-bus";
37 interrupt-parent = <&gic>;
41 compatible = "simple-bus";
44 reg = <0xd4200000 0x00200000>;
47 interrupt-controller@d4282000 {
48 compatible = "marvell,mmp3-intc";
50 #interrupt-cells = <1>;
51 reg = <0xd4282000 0x1000>,
53 mrvl,intc-nr-irqs = <64>;
56 pmic_mux: interrupt-controller@d4282150 {
57 compatible = "mrvl,mmp2-mux-intc";
58 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
60 #interrupt-cells = <1>;
61 reg = <0x150 0x4>, <0x168 0x4>;
62 reg-names = "mux status", "mux mask";
63 mrvl,intc-nr-irqs = <4>;
66 rtc_mux: interrupt-controller@d4282154 {
67 compatible = "mrvl,mmp2-mux-intc";
68 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
70 #interrupt-cells = <1>;
71 reg = <0x154 0x4>, <0x16c 0x4>;
72 reg-names = "mux status", "mux mask";
73 mrvl,intc-nr-irqs = <2>;
76 hsi3_mux: interrupt-controller@d42821bc {
77 compatible = "mrvl,mmp2-mux-intc";
78 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
80 #interrupt-cells = <1>;
81 reg = <0x1bc 0x4>, <0x1a4 0x4>;
82 reg-names = "mux status", "mux mask";
83 mrvl,intc-nr-irqs = <3>;
86 gpu_mux: interrupt-controller@d42821c0 {
87 compatible = "mrvl,mmp2-mux-intc";
88 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
90 #interrupt-cells = <1>;
91 reg = <0x1c0 0x4>, <0x1a8 0x4>;
92 reg-names = "mux status", "mux mask";
93 mrvl,intc-nr-irqs = <3>;
96 twsi_mux: interrupt-controller@d4282158 {
97 compatible = "mrvl,mmp2-mux-intc";
98 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
100 #interrupt-cells = <1>;
101 reg = <0x158 0x4>, <0x170 0x4>;
102 reg-names = "mux status", "mux mask";
103 mrvl,intc-nr-irqs = <5>;
106 hsi2_mux: interrupt-controller@d42821c4 {
107 compatible = "mrvl,mmp2-mux-intc";
108 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
109 interrupt-controller;
110 #interrupt-cells = <1>;
111 reg = <0x1c4 0x4>, <0x1ac 0x4>;
112 reg-names = "mux status", "mux mask";
113 mrvl,intc-nr-irqs = <2>;
116 dxo_mux: interrupt-controller@d42821c8 {
117 compatible = "mrvl,mmp2-mux-intc";
118 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
119 interrupt-controller;
120 #interrupt-cells = <1>;
121 reg = <0x1c8 0x4>, <0x1b0 0x4>;
122 reg-names = "mux status", "mux mask";
123 mrvl,intc-nr-irqs = <2>;
126 misc1_mux: interrupt-controller@d428215c {
127 compatible = "mrvl,mmp2-mux-intc";
128 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
129 interrupt-controller;
130 #interrupt-cells = <1>;
131 reg = <0x15c 0x4>, <0x174 0x4>;
132 reg-names = "mux status", "mux mask";
133 mrvl,intc-nr-irqs = <31>;
136 ci_mux: interrupt-controller@d42821cc {
137 compatible = "mrvl,mmp2-mux-intc";
138 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
139 interrupt-controller;
140 #interrupt-cells = <1>;
141 reg = <0x1cc 0x4>, <0x1b4 0x4>;
142 reg-names = "mux status", "mux mask";
143 mrvl,intc-nr-irqs = <2>;
146 ssp_mux: interrupt-controller@d4282160 {
147 compatible = "mrvl,mmp2-mux-intc";
148 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
149 interrupt-controller;
150 #interrupt-cells = <1>;
151 reg = <0x160 0x4>, <0x178 0x4>;
152 reg-names = "mux status", "mux mask";
153 mrvl,intc-nr-irqs = <2>;
156 hsi1_mux: interrupt-controller@d4282184 {
157 compatible = "mrvl,mmp2-mux-intc";
158 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
159 interrupt-controller;
160 #interrupt-cells = <1>;
161 reg = <0x184 0x4>, <0x17c 0x4>;
162 reg-names = "mux status", "mux mask";
163 mrvl,intc-nr-irqs = <4>;
166 misc2_mux: interrupt-controller@d4282188 {
167 compatible = "mrvl,mmp2-mux-intc";
168 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
169 interrupt-controller;
170 #interrupt-cells = <1>;
171 reg = <0x188 0x4>, <0x180 0x4>;
172 reg-names = "mux status", "mux mask";
173 mrvl,intc-nr-irqs = <20>;
176 hsi0_mux: interrupt-controller@d42821d0 {
177 compatible = "mrvl,mmp2-mux-intc";
178 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
179 interrupt-controller;
180 #interrupt-cells = <1>;
181 reg = <0x1d0 0x4>, <0x1b8 0x4>;
182 reg-names = "mux status", "mux mask";
183 mrvl,intc-nr-irqs = <5>;
186 usb_otg_phy0: usb-phy@d4207000 {
187 compatible = "marvell,mmp3-usb-phy";
188 reg = <0xd4207000 0x40>;
193 usb_otg0: usb@d4208000 {
194 compatible = "marvell,pxau2o-ehci";
195 reg = <0xd4208000 0x200>;
196 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
197 clocks = <&soc_clocks MMP2_CLK_USB>;
198 clock-names = "USBCLK";
199 phys = <&usb_otg_phy0>;
204 hsic_phy0: usb-phy@f0001800 {
205 compatible = "marvell,mmp3-hsic-phy";
206 reg = <0xf0001800 0x40>;
211 hsic0: usb@f0001000 {
212 compatible = "marvell,pxau2o-ehci";
213 reg = <0xf0001000 0x200>;
214 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
215 clocks = <&soc_clocks MMP2_CLK_USBHSIC0>;
216 clock-names = "USBCLK";
220 #address-cells = <0x01>;
221 #size-cells = <0x00>;
225 hsic_phy1: usb-phy@f0002800 {
226 compatible = "marvell,mmp3-hsic-phy";
227 reg = <0xf0002800 0x40>;
232 hsic1: usb@f0002000 {
233 compatible = "marvell,pxau2o-ehci";
234 reg = <0xf0002000 0x200>;
235 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
236 clocks = <&soc_clocks MMP2_CLK_USBHSIC1>;
237 clock-names = "USBCLK";
241 #address-cells = <0x01>;
242 #size-cells = <0x00>;
247 compatible = "mrvl,pxav3-mmc";
248 reg = <0xd4280000 0x120>;
249 clocks = <&soc_clocks MMP2_CLK_SDH0>;
251 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
256 compatible = "mrvl,pxav3-mmc";
257 reg = <0xd4280800 0x120>;
258 clocks = <&soc_clocks MMP2_CLK_SDH1>;
260 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
265 compatible = "mrvl,pxav3-mmc";
266 reg = <0xd4281000 0x120>;
267 clocks = <&soc_clocks MMP2_CLK_SDH2>;
269 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
274 compatible = "mrvl,pxav3-mmc";
275 reg = <0xd4281800 0x120>;
276 clocks = <&soc_clocks MMP2_CLK_SDH3>;
278 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
283 compatible = "mrvl,pxav3-mmc";
284 reg = <0xd4217000 0x120>;
285 clocks = <&soc_clocks MMP3_CLK_SDH4>;
287 interrupt-parent = <&hsi1_mux>;
292 camera0: camera@d420a000 {
293 compatible = "marvell,mmp2-ccic";
294 reg = <0xd420a000 0x800>;
295 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
296 clocks = <&soc_clocks MMP2_CLK_CCIC0>;
299 clock-output-names = "mclk";
303 camera1: camera@d420a800 {
304 compatible = "marvell,mmp2-ccic";
305 reg = <0xd420a800 0x800>;
306 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
307 clocks = <&soc_clocks MMP2_CLK_CCIC1>;
310 clock-output-names = "mclk";
316 compatible = "simple-bus";
317 #address-cells = <1>;
319 reg = <0xd4000000 0x00200000>;
322 timer: timer@d4014000 {
323 compatible = "mrvl,mmp-timer";
324 reg = <0xd4014000 0x100>;
325 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
326 clocks = <&soc_clocks MMP2_CLK_TIMER>;
329 uart1: serial@d4030000 {
330 compatible = "mrvl,mmp-uart", "intel,xscale-uart";
331 reg = <0xd4030000 0x1000>;
332 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
333 clocks = <&soc_clocks MMP2_CLK_UART0>;
334 resets = <&soc_clocks MMP2_CLK_UART0>;
339 uart2: serial@d4017000 {
340 compatible = "mrvl,mmp-uart", "intel,xscale-uart";
341 reg = <0xd4017000 0x1000>;
342 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
343 clocks = <&soc_clocks MMP2_CLK_UART1>;
344 resets = <&soc_clocks MMP2_CLK_UART1>;
349 uart3: serial@d4018000 {
350 compatible = "mrvl,mmp-uart", "intel,xscale-uart";
351 reg = <0xd4018000 0x1000>;
352 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
353 clocks = <&soc_clocks MMP2_CLK_UART2>;
354 resets = <&soc_clocks MMP2_CLK_UART2>;
359 uart4: serial@d4016000 {
360 compatible = "mrvl,mmp-uart", "intel,xscale-uart";
361 reg = <0xd4016000 0x1000>;
362 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
363 clocks = <&soc_clocks MMP2_CLK_UART3>;
364 resets = <&soc_clocks MMP2_CLK_UART3>;
369 gpio: gpio@d4019000 {
370 compatible = "marvell,mmp2-gpio";
371 #address-cells = <1>;
373 reg = <0xd4019000 0x1000>;
376 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
377 interrupt-names = "gpio_mux";
378 clocks = <&soc_clocks MMP2_CLK_GPIO>;
379 resets = <&soc_clocks MMP2_CLK_GPIO>;
380 interrupt-controller;
381 #interrupt-cells = <2>;
384 gcb0: gpio@d4019000 {
385 reg = <0xd4019000 0x4>;
388 gcb1: gpio@d4019004 {
389 reg = <0xd4019004 0x4>;
392 gcb2: gpio@d4019008 {
393 reg = <0xd4019008 0x4>;
396 gcb3: gpio@d4019100 {
397 reg = <0xd4019100 0x4>;
400 gcb4: gpio@d4019104 {
401 reg = <0xd4019104 0x4>;
404 gcb5: gpio@d4019108 {
405 reg = <0xd4019108 0x4>;
409 twsi1: i2c@d4011000 {
410 compatible = "mrvl,mmp-twsi";
411 reg = <0xd4011000 0x70>;
412 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
413 clocks = <&soc_clocks MMP2_CLK_TWSI0>;
414 resets = <&soc_clocks MMP2_CLK_TWSI0>;
415 #address-cells = <1>;
421 twsi2: i2c@d4031000 {
422 compatible = "mrvl,mmp-twsi";
423 reg = <0xd4031000 0x70>;
424 interrupt-parent = <&twsi_mux>;
426 clocks = <&soc_clocks MMP2_CLK_TWSI1>;
427 resets = <&soc_clocks MMP2_CLK_TWSI1>;
428 #address-cells = <1>;
433 twsi3: i2c@d4032000 {
434 compatible = "mrvl,mmp-twsi";
435 reg = <0xd4032000 0x70>;
436 interrupt-parent = <&twsi_mux>;
438 clocks = <&soc_clocks MMP2_CLK_TWSI2>;
439 resets = <&soc_clocks MMP2_CLK_TWSI2>;
440 #address-cells = <1>;
445 twsi4: i2c@d4033000 {
446 compatible = "mrvl,mmp-twsi";
447 reg = <0xd4033000 0x70>;
448 interrupt-parent = <&twsi_mux>;
450 clocks = <&soc_clocks MMP2_CLK_TWSI3>;
451 resets = <&soc_clocks MMP2_CLK_TWSI3>;
452 #address-cells = <1>;
458 twsi5: i2c@d4033800 {
459 compatible = "mrvl,mmp-twsi";
460 reg = <0xd4033800 0x70>;
461 interrupt-parent = <&twsi_mux>;
463 clocks = <&soc_clocks MMP2_CLK_TWSI4>;
464 resets = <&soc_clocks MMP2_CLK_TWSI4>;
465 #address-cells = <1>;
470 twsi6: i2c@d4034000 {
471 compatible = "mrvl,mmp-twsi";
472 reg = <0xd4034000 0x70>;
473 interrupt-parent = <&twsi_mux>;
475 clocks = <&soc_clocks MMP2_CLK_TWSI5>;
476 resets = <&soc_clocks MMP2_CLK_TWSI5>;
477 #address-cells = <1>;
483 compatible = "mrvl,mmp-rtc";
484 reg = <0xd4010000 0x1000>;
485 interrupts = <1>, <0>;
486 interrupt-names = "rtc 1Hz", "rtc alarm";
487 interrupt-parent = <&rtc_mux>;
488 clocks = <&soc_clocks MMP2_CLK_RTC>;
489 resets = <&soc_clocks MMP2_CLK_RTC>;
494 compatible = "marvell,mmp2-ssp";
495 reg = <0xd4035000 0x1000>;
496 clocks = <&soc_clocks MMP2_CLK_SSP0>;
497 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
498 #address-cells = <1>;
504 compatible = "marvell,mmp2-ssp";
505 reg = <0xd4036000 0x1000>;
506 clocks = <&soc_clocks MMP2_CLK_SSP1>;
507 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
508 #address-cells = <1>;
514 compatible = "marvell,mmp2-ssp";
515 reg = <0xd4037000 0x1000>;
516 clocks = <&soc_clocks MMP2_CLK_SSP2>;
517 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
518 #address-cells = <1>;
524 compatible = "marvell,mmp2-ssp";
525 reg = <0xd4039000 0x1000>;
526 clocks = <&soc_clocks MMP2_CLK_SSP3>;
527 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
528 #address-cells = <1>;
534 l2: cache-controller@d0020000 {
535 compatible = "marvell,tauros3-cache", "arm,pl310-cache";
536 reg = <0xd0020000 0x1000>;
541 soc_clocks: clocks@d4050000 {
542 compatible = "marvell,mmp3-clock";
543 reg = <0xd4050000 0x1000>,
546 reg-names = "mpmu", "apmu", "apbc";
549 #power-domain-cells = <1>;
552 snoop-control-unit@e0000000 {
553 compatible = "arm,arm11mp-scu";
554 reg = <0xe0000000 0x100>;
557 gic: interrupt-controller@e0001000 {
558 compatible = "arm,arm11mp-gic";
559 interrupt-controller;
560 #interrupt-cells = <3>;
561 reg = <0xe0001000 0x1000>,
565 local-timer@e0000600 {
566 compatible = "arm,arm11mp-twd-timer";
567 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) |
568 IRQ_TYPE_EDGE_RISING)>;
569 reg = <0xe0000600 0x20>;
573 compatible = "arm,arm11mp-twd-wdt";
574 reg = <0xe0000620 0x20>;
575 interrupts = <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) |
576 IRQ_TYPE_EDGE_RISING)>;