1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2017-2018 MediaTek Inc.
4 * Author: John Crispin <john@phrozen.org>
5 * Sean Wang <sean.wang@mediatek.com>
9 #include <dt-bindings/interrupt-controller/irq.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/clock/mt2701-clk.h>
12 #include <dt-bindings/pinctrl/mt7623-pinfunc.h>
13 #include <dt-bindings/power/mt2701-power.h>
14 #include <dt-bindings/gpio/gpio.h>
15 #include <dt-bindings/phy/phy.h>
16 #include <dt-bindings/reset/mt2701-resets.h>
17 #include <dt-bindings/thermal/thermal.h>
20 compatible = "mediatek,mt7623";
21 interrupt-parent = <&sysirq>;
25 cpu_opp_table: opp-table {
26 compatible = "operating-points-v2";
30 opp-hz = /bits/ 64 <98000000>;
31 opp-microvolt = <1050000>;
35 opp-hz = /bits/ 64 <198000000>;
36 opp-microvolt = <1050000>;
40 opp-hz = /bits/ 64 <398000000>;
41 opp-microvolt = <1050000>;
45 opp-hz = /bits/ 64 <598000000>;
46 opp-microvolt = <1050000>;
50 opp-hz = /bits/ 64 <747500000>;
51 opp-microvolt = <1050000>;
55 opp-hz = /bits/ 64 <1040000000>;
56 opp-microvolt = <1150000>;
60 opp-hz = /bits/ 64 <1196000000>;
61 opp-microvolt = <1200000>;
65 opp-hz = /bits/ 64 <1300000000>;
66 opp-microvolt = <1300000>;
73 enable-method = "mediatek,mt6589-smp";
77 compatible = "arm,cortex-a7";
79 clocks = <&infracfg CLK_INFRA_CPUSEL>,
80 <&apmixedsys CLK_APMIXED_MAINPLL>;
81 clock-names = "cpu", "intermediate";
82 operating-points-v2 = <&cpu_opp_table>;
84 clock-frequency = <1300000000>;
89 compatible = "arm,cortex-a7";
91 clocks = <&infracfg CLK_INFRA_CPUSEL>,
92 <&apmixedsys CLK_APMIXED_MAINPLL>;
93 clock-names = "cpu", "intermediate";
94 operating-points-v2 = <&cpu_opp_table>;
95 clock-frequency = <1300000000>;
100 compatible = "arm,cortex-a7";
102 clocks = <&infracfg CLK_INFRA_CPUSEL>,
103 <&apmixedsys CLK_APMIXED_MAINPLL>;
104 clock-names = "cpu", "intermediate";
105 operating-points-v2 = <&cpu_opp_table>;
106 clock-frequency = <1300000000>;
111 compatible = "arm,cortex-a7";
113 clocks = <&infracfg CLK_INFRA_CPUSEL>,
114 <&apmixedsys CLK_APMIXED_MAINPLL>;
115 clock-names = "cpu", "intermediate";
116 operating-points-v2 = <&cpu_opp_table>;
117 clock-frequency = <1300000000>;
121 system_clk: dummy13m {
122 compatible = "fixed-clock";
123 clock-frequency = <13000000>;
127 rtc32k: oscillator-1 {
128 compatible = "fixed-clock";
130 clock-frequency = <32000>;
131 clock-output-names = "rtc32k";
134 clk26m: oscillator-0 {
135 compatible = "fixed-clock";
137 clock-frequency = <26000000>;
138 clock-output-names = "clk26m";
142 cpu_thermal: cpu-thermal {
143 polling-delay-passive = <1000>;
144 polling-delay = <1000>;
146 thermal-sensors = <&thermal 0>;
149 cpu_passive: cpu-passive {
150 temperature = <47000>;
155 cpu_active: cpu-active {
156 temperature = <67000>;
162 temperature = <87000>;
168 temperature = <107000>;
176 trip = <&cpu_passive>;
177 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
181 trip = <&cpu_active>;
182 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
187 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
194 compatible = "arm,armv7-timer";
195 interrupt-parent = <&gic>;
196 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
197 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
198 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
199 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
200 clock-frequency = <13000000>;
201 arm,cpu-registers-not-fw-configured;
204 topckgen: syscon@10000000 {
205 compatible = "mediatek,mt7623-topckgen",
206 "mediatek,mt2701-topckgen",
208 reg = <0 0x10000000 0 0x1000>;
212 infracfg: syscon@10001000 {
213 compatible = "mediatek,mt7623-infracfg",
214 "mediatek,mt2701-infracfg",
216 reg = <0 0x10001000 0 0x1000>;
221 pericfg: syscon@10003000 {
222 compatible = "mediatek,mt7623-pericfg",
223 "mediatek,mt2701-pericfg",
225 reg = <0 0x10003000 0 0x1000>;
230 pio: pinctrl@10005000 {
231 compatible = "mediatek,mt7623-pinctrl";
232 reg = <0 0x1000b000 0 0x1000>;
233 mediatek,pctl-regmap = <&syscfg_pctl_a>;
237 interrupt-controller;
238 interrupt-parent = <&gic>;
239 #interrupt-cells = <2>;
240 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
241 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
244 syscfg_pctl_a: syscfg@10005000 {
245 compatible = "mediatek,mt7623-pctl-a-syscfg", "syscon";
246 reg = <0 0x10005000 0 0x1000>;
249 scpsys: scpsys@10006000 {
250 compatible = "mediatek,mt7623-scpsys",
251 "mediatek,mt2701-scpsys",
253 #power-domain-cells = <1>;
254 reg = <0 0x10006000 0 0x1000>;
255 infracfg = <&infracfg>;
256 clocks = <&topckgen CLK_TOP_MM_SEL>,
257 <&topckgen CLK_TOP_MFG_SEL>,
258 <&topckgen CLK_TOP_ETHIF_SEL>;
259 clock-names = "mm", "mfg", "ethif";
262 watchdog: watchdog@10007000 {
263 compatible = "mediatek,mt7623-wdt",
264 "mediatek,mt6589-wdt";
265 reg = <0 0x10007000 0 0x100>;
268 timer: timer@10008000 {
269 compatible = "mediatek,mt7623-timer",
270 "mediatek,mt6577-timer";
271 reg = <0 0x10008000 0 0x80>;
272 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_LOW>;
273 clocks = <&system_clk>, <&rtc32k>;
274 clock-names = "system-clk", "rtc-clk";
277 pwrap: pwrap@1000d000 {
278 compatible = "mediatek,mt7623-pwrap",
279 "mediatek,mt2701-pwrap";
280 reg = <0 0x1000d000 0 0x1000>;
282 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
283 resets = <&infracfg MT2701_INFRA_PMIC_WRAP_RST>;
284 reset-names = "pwrap";
285 clocks = <&infracfg CLK_INFRA_PMICSPI>,
286 <&infracfg CLK_INFRA_PMICWRAP>;
287 clock-names = "spi", "wrap";
291 compatible = "mediatek,mt7623-cir";
292 reg = <0 0x10013000 0 0x1000>;
293 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_LOW>;
294 clocks = <&infracfg CLK_INFRA_IRRX>;
299 sysirq: interrupt-controller@10200100 {
300 compatible = "mediatek,mt7623-sysirq",
301 "mediatek,mt6577-sysirq";
302 interrupt-controller;
303 #interrupt-cells = <3>;
304 interrupt-parent = <&gic>;
305 reg = <0 0x10200100 0 0x1c>;
308 efuse: efuse@10206000 {
309 compatible = "mediatek,mt7623-efuse",
310 "mediatek,mt8173-efuse";
311 reg = <0 0x10206000 0 0x1000>;
312 #address-cells = <1>;
314 thermal_calibration_data: calib@424 {
319 apmixedsys: syscon@10209000 {
320 compatible = "mediatek,mt7623-apmixedsys",
321 "mediatek,mt2701-apmixedsys",
323 reg = <0 0x10209000 0 0x1000>;
328 compatible = "mediatek,mt7623-rng";
329 reg = <0 0x1020f000 0 0x1000>;
330 clocks = <&infracfg CLK_INFRA_TRNG>;
334 gic: interrupt-controller@10211000 {
335 compatible = "arm,cortex-a7-gic";
336 interrupt-controller;
337 #interrupt-cells = <3>;
338 interrupt-parent = <&gic>;
339 reg = <0 0x10211000 0 0x1000>,
340 <0 0x10212000 0 0x2000>,
341 <0 0x10214000 0 0x2000>,
342 <0 0x10216000 0 0x2000>;
345 auxadc: adc@11001000 {
346 compatible = "mediatek,mt7623-auxadc",
347 "mediatek,mt2701-auxadc";
348 reg = <0 0x11001000 0 0x1000>;
349 clocks = <&pericfg CLK_PERI_AUXADC>;
350 clock-names = "main";
351 #io-channel-cells = <1>;
354 uart0: serial@11002000 {
355 compatible = "mediatek,mt7623-uart",
356 "mediatek,mt6577-uart";
357 reg = <0 0x11002000 0 0x400>;
358 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_LOW>;
359 clocks = <&pericfg CLK_PERI_UART0_SEL>,
360 <&pericfg CLK_PERI_UART0>;
361 clock-names = "baud", "bus";
365 uart1: serial@11003000 {
366 compatible = "mediatek,mt7623-uart",
367 "mediatek,mt6577-uart";
368 reg = <0 0x11003000 0 0x400>;
369 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_LOW>;
370 clocks = <&pericfg CLK_PERI_UART1_SEL>,
371 <&pericfg CLK_PERI_UART1>;
372 clock-names = "baud", "bus";
376 uart2: serial@11004000 {
377 compatible = "mediatek,mt7623-uart",
378 "mediatek,mt6577-uart";
379 reg = <0 0x11004000 0 0x400>;
380 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_LOW>;
381 clocks = <&pericfg CLK_PERI_UART2_SEL>,
382 <&pericfg CLK_PERI_UART2>;
383 clock-names = "baud", "bus";
387 uart3: serial@11005000 {
388 compatible = "mediatek,mt7623-uart",
389 "mediatek,mt6577-uart";
390 reg = <0 0x11005000 0 0x400>;
391 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_LOW>;
392 clocks = <&pericfg CLK_PERI_UART3_SEL>,
393 <&pericfg CLK_PERI_UART3>;
394 clock-names = "baud", "bus";
399 compatible = "mediatek,mt7623-pwm";
400 reg = <0 0x11006000 0 0x1000>;
402 clocks = <&topckgen CLK_TOP_PWM_SEL>,
403 <&pericfg CLK_PERI_PWM>,
404 <&pericfg CLK_PERI_PWM1>,
405 <&pericfg CLK_PERI_PWM2>,
406 <&pericfg CLK_PERI_PWM3>,
407 <&pericfg CLK_PERI_PWM4>,
408 <&pericfg CLK_PERI_PWM5>;
409 clock-names = "top", "main", "pwm1", "pwm2",
410 "pwm3", "pwm4", "pwm5";
415 compatible = "mediatek,mt7623-i2c",
416 "mediatek,mt6577-i2c";
417 reg = <0 0x11007000 0 0x70>,
418 <0 0x11000200 0 0x80>;
419 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_LOW>;
421 clocks = <&pericfg CLK_PERI_I2C0>,
422 <&pericfg CLK_PERI_AP_DMA>;
423 clock-names = "main", "dma";
424 #address-cells = <1>;
430 compatible = "mediatek,mt7623-i2c",
431 "mediatek,mt6577-i2c";
432 reg = <0 0x11008000 0 0x70>,
433 <0 0x11000280 0 0x80>;
434 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_LOW>;
436 clocks = <&pericfg CLK_PERI_I2C1>,
437 <&pericfg CLK_PERI_AP_DMA>;
438 clock-names = "main", "dma";
439 #address-cells = <1>;
445 compatible = "mediatek,mt7623-i2c",
446 "mediatek,mt6577-i2c";
447 reg = <0 0x11009000 0 0x70>,
448 <0 0x11000300 0 0x80>;
449 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_LOW>;
451 clocks = <&pericfg CLK_PERI_I2C2>,
452 <&pericfg CLK_PERI_AP_DMA>;
453 clock-names = "main", "dma";
454 #address-cells = <1>;
460 compatible = "mediatek,mt7623-spi",
461 "mediatek,mt2701-spi";
462 #address-cells = <1>;
464 reg = <0 0x1100a000 0 0x100>;
465 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_LOW>;
466 clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
467 <&topckgen CLK_TOP_SPI0_SEL>,
468 <&pericfg CLK_PERI_SPI0>;
469 clock-names = "parent-clk", "sel-clk", "spi-clk";
473 thermal: thermal@1100b000 {
474 #thermal-sensor-cells = <1>;
475 compatible = "mediatek,mt7623-thermal",
476 "mediatek,mt2701-thermal";
477 reg = <0 0x1100b000 0 0x1000>;
478 interrupts = <0 70 IRQ_TYPE_LEVEL_LOW>;
479 clocks = <&pericfg CLK_PERI_THERM>, <&pericfg CLK_PERI_AUXADC>;
480 clock-names = "therm", "auxadc";
481 resets = <&pericfg MT2701_PERI_THERM_SW_RST>;
482 reset-names = "therm";
483 mediatek,auxadc = <&auxadc>;
484 mediatek,apmixedsys = <&apmixedsys>;
485 nvmem-cells = <&thermal_calibration_data>;
486 nvmem-cell-names = "calibration-data";
489 btif: serial@1100c000 {
490 compatible = "mediatek,mt7623-btif",
492 reg = <0 0x1100c000 0 0x1000>;
493 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_LOW>;
494 clocks = <&pericfg CLK_PERI_BTIF>;
495 clock-names = "main";
501 nandc: nfi@1100d000 {
502 compatible = "mediatek,mt7623-nfc",
503 "mediatek,mt2701-nfc";
504 reg = <0 0x1100d000 0 0x1000>;
505 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_LOW>;
506 power-domains = <&scpsys MT2701_POWER_DOMAIN_IFR_MSC>;
507 clocks = <&pericfg CLK_PERI_NFI>,
508 <&pericfg CLK_PERI_NFI_PAD>;
509 clock-names = "nfi_clk", "pad_clk";
512 #address-cells = <1>;
517 compatible = "mediatek,mt7623-ecc",
518 "mediatek,mt2701-ecc";
519 reg = <0 0x1100e000 0 0x1000>;
520 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_LOW>;
521 clocks = <&pericfg CLK_PERI_NFI_ECC>;
522 clock-names = "nfiecc_clk";
526 nor_flash: spi@11014000 {
527 compatible = "mediatek,mt7623-nor",
528 "mediatek,mt8173-nor";
529 reg = <0 0x11014000 0 0x1000>;
530 clocks = <&pericfg CLK_PERI_FLASH>,
531 <&topckgen CLK_TOP_FLASH_SEL>;
532 clock-names = "spi", "sf";
533 #address-cells = <1>;
539 compatible = "mediatek,mt7623-spi",
540 "mediatek,mt2701-spi";
541 #address-cells = <1>;
543 reg = <0 0x11016000 0 0x100>;
544 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_LOW>;
545 clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
546 <&topckgen CLK_TOP_SPI1_SEL>,
547 <&pericfg CLK_PERI_SPI1>;
548 clock-names = "parent-clk", "sel-clk", "spi-clk";
553 compatible = "mediatek,mt7623-spi",
554 "mediatek,mt2701-spi";
555 #address-cells = <1>;
557 reg = <0 0x11017000 0 0x1000>;
558 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_LOW>;
559 clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
560 <&topckgen CLK_TOP_SPI2_SEL>,
561 <&pericfg CLK_PERI_SPI2>;
562 clock-names = "parent-clk", "sel-clk", "spi-clk";
566 audsys: clock-controller@11220000 {
567 compatible = "mediatek,mt7623-audsys",
568 "mediatek,mt2701-audsys",
570 reg = <0 0x11220000 0 0x2000>;
573 afe: audio-controller {
574 compatible = "mediatek,mt7623-audio",
575 "mediatek,mt2701-audio";
576 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_LOW>,
577 <GIC_SPI 132 IRQ_TYPE_LEVEL_LOW>;
578 interrupt-names = "afe", "asys";
579 power-domains = <&scpsys MT2701_POWER_DOMAIN_IFR_MSC>;
581 clocks = <&infracfg CLK_INFRA_AUDIO>,
582 <&topckgen CLK_TOP_AUD_MUX1_SEL>,
583 <&topckgen CLK_TOP_AUD_MUX2_SEL>,
584 <&topckgen CLK_TOP_AUD_48K_TIMING>,
585 <&topckgen CLK_TOP_AUD_44K_TIMING>,
586 <&topckgen CLK_TOP_AUD_K1_SRC_SEL>,
587 <&topckgen CLK_TOP_AUD_K2_SRC_SEL>,
588 <&topckgen CLK_TOP_AUD_K3_SRC_SEL>,
589 <&topckgen CLK_TOP_AUD_K4_SRC_SEL>,
590 <&topckgen CLK_TOP_AUD_K1_SRC_DIV>,
591 <&topckgen CLK_TOP_AUD_K2_SRC_DIV>,
592 <&topckgen CLK_TOP_AUD_K3_SRC_DIV>,
593 <&topckgen CLK_TOP_AUD_K4_SRC_DIV>,
594 <&topckgen CLK_TOP_AUD_I2S1_MCLK>,
595 <&topckgen CLK_TOP_AUD_I2S2_MCLK>,
596 <&topckgen CLK_TOP_AUD_I2S3_MCLK>,
597 <&topckgen CLK_TOP_AUD_I2S4_MCLK>,
598 <&audsys CLK_AUD_I2SO1>,
599 <&audsys CLK_AUD_I2SO2>,
600 <&audsys CLK_AUD_I2SO3>,
601 <&audsys CLK_AUD_I2SO4>,
602 <&audsys CLK_AUD_I2SIN1>,
603 <&audsys CLK_AUD_I2SIN2>,
604 <&audsys CLK_AUD_I2SIN3>,
605 <&audsys CLK_AUD_I2SIN4>,
606 <&audsys CLK_AUD_ASRCO1>,
607 <&audsys CLK_AUD_ASRCO2>,
608 <&audsys CLK_AUD_ASRCO3>,
609 <&audsys CLK_AUD_ASRCO4>,
610 <&audsys CLK_AUD_AFE>,
611 <&audsys CLK_AUD_AFE_CONN>,
612 <&audsys CLK_AUD_A1SYS>,
613 <&audsys CLK_AUD_A2SYS>,
614 <&audsys CLK_AUD_AFE_MRGIF>;
616 clock-names = "infra_sys_audio_clk",
617 "top_audio_mux1_sel",
618 "top_audio_mux2_sel",
619 "top_audio_a1sys_hp",
620 "top_audio_a2sys_hp",
651 assigned-clocks = <&topckgen CLK_TOP_AUD_MUX1_SEL>,
652 <&topckgen CLK_TOP_AUD_MUX2_SEL>,
653 <&topckgen CLK_TOP_AUD_MUX1_DIV>,
654 <&topckgen CLK_TOP_AUD_MUX2_DIV>;
655 assigned-clock-parents = <&topckgen CLK_TOP_AUD1PLL_98M>,
656 <&topckgen CLK_TOP_AUD2PLL_90M>;
657 assigned-clock-rates = <0>, <0>, <49152000>, <45158400>;
662 compatible = "mediatek,mt7623-mmc",
663 "mediatek,mt2701-mmc";
664 reg = <0 0x11230000 0 0x1000>;
665 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_LOW>;
666 clocks = <&pericfg CLK_PERI_MSDC30_0>,
667 <&topckgen CLK_TOP_MSDC30_0_SEL>;
668 clock-names = "source", "hclk";
673 compatible = "mediatek,mt7623-mmc",
674 "mediatek,mt2701-mmc";
675 reg = <0 0x11240000 0 0x1000>;
676 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_LOW>;
677 clocks = <&pericfg CLK_PERI_MSDC30_1>,
678 <&topckgen CLK_TOP_MSDC30_1_SEL>;
679 clock-names = "source", "hclk";
683 hifsys: syscon@1a000000 {
684 compatible = "mediatek,mt7623-hifsys",
685 "mediatek,mt2701-hifsys",
687 reg = <0 0x1a000000 0 0x1000>;
692 pcie: pcie@1a140000 {
693 compatible = "mediatek,mt7623-pcie";
695 reg = <0 0x1a140000 0 0x1000>, /* PCIe shared registers */
696 <0 0x1a142000 0 0x1000>, /* Port0 registers */
697 <0 0x1a143000 0 0x1000>, /* Port1 registers */
698 <0 0x1a144000 0 0x1000>; /* Port2 registers */
699 reg-names = "subsys", "port0", "port1", "port2";
700 #address-cells = <3>;
702 #interrupt-cells = <1>;
703 interrupt-map-mask = <0xf800 0 0 0>;
704 interrupt-map = <0x0000 0 0 0 &sysirq GIC_SPI 193 IRQ_TYPE_LEVEL_LOW>,
705 <0x0800 0 0 0 &sysirq GIC_SPI 194 IRQ_TYPE_LEVEL_LOW>,
706 <0x1000 0 0 0 &sysirq GIC_SPI 195 IRQ_TYPE_LEVEL_LOW>;
707 clocks = <&topckgen CLK_TOP_ETHIF_SEL>,
708 <&hifsys CLK_HIFSYS_PCIE0>,
709 <&hifsys CLK_HIFSYS_PCIE1>,
710 <&hifsys CLK_HIFSYS_PCIE2>;
711 clock-names = "free_ck", "sys_ck0", "sys_ck1", "sys_ck2";
712 resets = <&hifsys MT2701_HIFSYS_PCIE0_RST>,
713 <&hifsys MT2701_HIFSYS_PCIE1_RST>,
714 <&hifsys MT2701_HIFSYS_PCIE2_RST>;
715 reset-names = "pcie-rst0", "pcie-rst1", "pcie-rst2";
716 phys = <&pcie0_port PHY_TYPE_PCIE>,
717 <&pcie1_port PHY_TYPE_PCIE>,
718 <&u3port1 PHY_TYPE_PCIE>;
719 phy-names = "pcie-phy0", "pcie-phy1", "pcie-phy2";
720 power-domains = <&scpsys MT2701_POWER_DOMAIN_HIF>;
721 bus-range = <0x00 0xff>;
723 ranges = <0x81000000 0 0x1a160000 0 0x1a160000 0 0x00010000
724 0x83000000 0 0x60000000 0 0x60000000 0 0x10000000>;
727 reg = <0x0000 0 0 0 0>;
728 #address-cells = <3>;
730 #interrupt-cells = <1>;
731 interrupt-map-mask = <0 0 0 0>;
732 interrupt-map = <0 0 0 0 &sysirq GIC_SPI 193 IRQ_TYPE_LEVEL_LOW>;
739 reg = <0x0800 0 0 0 0>;
740 #address-cells = <3>;
742 #interrupt-cells = <1>;
743 interrupt-map-mask = <0 0 0 0>;
744 interrupt-map = <0 0 0 0 &sysirq GIC_SPI 194 IRQ_TYPE_LEVEL_LOW>;
751 reg = <0x1000 0 0 0 0>;
752 #address-cells = <3>;
754 #interrupt-cells = <1>;
755 interrupt-map-mask = <0 0 0 0>;
756 interrupt-map = <0 0 0 0 &sysirq GIC_SPI 195 IRQ_TYPE_LEVEL_LOW>;
763 pcie0_phy: pcie-phy@1a149000 {
764 compatible = "mediatek,generic-tphy-v1";
765 reg = <0 0x1a149000 0 0x0700>;
766 #address-cells = <2>;
771 pcie0_port: pcie-phy@1a149900 {
772 reg = <0 0x1a149900 0 0x0700>;
780 pcie1_phy: pcie-phy@1a14a000 {
781 compatible = "mediatek,generic-tphy-v1";
782 reg = <0 0x1a14a000 0 0x0700>;
783 #address-cells = <2>;
788 pcie1_port: pcie-phy@1a14a900 {
789 reg = <0 0x1a14a900 0 0x0700>;
798 compatible = "mediatek,mt7623-xhci",
799 "mediatek,mt8173-xhci";
800 reg = <0 0x1a1c0000 0 0x1000>,
801 <0 0x1a1c4700 0 0x0100>;
802 reg-names = "mac", "ippc";
803 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_LOW>;
804 clocks = <&hifsys CLK_HIFSYS_USB0PHY>,
805 <&topckgen CLK_TOP_ETHIF_SEL>;
806 clock-names = "sys_ck", "ref_ck";
807 power-domains = <&scpsys MT2701_POWER_DOMAIN_HIF>;
808 phys = <&u2port0 PHY_TYPE_USB2>, <&u3port0 PHY_TYPE_USB3>;
812 u3phy1: usb-phy@1a1c4000 {
813 compatible = "mediatek,mt7623-u3phy",
814 "mediatek,mt2701-u3phy";
815 reg = <0 0x1a1c4000 0 0x0700>;
816 #address-cells = <2>;
821 u2port0: usb-phy@1a1c4800 {
822 reg = <0 0x1a1c4800 0 0x0100>;
823 clocks = <&topckgen CLK_TOP_USB_PHY48M>;
829 u3port0: usb-phy@1a1c4900 {
830 reg = <0 0x1a1c4900 0 0x0700>;
839 compatible = "mediatek,mt7623-xhci",
840 "mediatek,mt8173-xhci";
841 reg = <0 0x1a240000 0 0x1000>,
842 <0 0x1a244700 0 0x0100>;
843 reg-names = "mac", "ippc";
844 interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_LOW>;
845 clocks = <&hifsys CLK_HIFSYS_USB1PHY>,
846 <&topckgen CLK_TOP_ETHIF_SEL>;
847 clock-names = "sys_ck", "ref_ck";
848 power-domains = <&scpsys MT2701_POWER_DOMAIN_HIF>;
849 phys = <&u2port1 PHY_TYPE_USB2>, <&u3port1 PHY_TYPE_USB3>;
853 u3phy2: usb-phy@1a244000 {
854 compatible = "mediatek,mt7623-u3phy",
855 "mediatek,mt2701-u3phy";
856 reg = <0 0x1a244000 0 0x0700>;
857 #address-cells = <2>;
862 u2port1: usb-phy@1a244800 {
863 reg = <0 0x1a244800 0 0x0100>;
864 clocks = <&topckgen CLK_TOP_USB_PHY48M>;
870 u3port1: usb-phy@1a244900 {
871 reg = <0 0x1a244900 0 0x0700>;
879 ethsys: syscon@1b000000 {
880 compatible = "mediatek,mt7623-ethsys",
881 "mediatek,mt2701-ethsys",
883 reg = <0 0x1b000000 0 0x1000>;
888 hsdma: dma-controller@1b007000 {
889 compatible = "mediatek,mt7623-hsdma";
890 reg = <0 0x1b007000 0 0x1000>;
891 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_LOW>;
892 clocks = <ðsys CLK_ETHSYS_HSDMA>;
893 clock-names = "hsdma";
894 power-domains = <&scpsys MT2701_POWER_DOMAIN_ETH>;
898 eth: ethernet@1b100000 {
899 compatible = "mediatek,mt7623-eth",
900 "mediatek,mt2701-eth",
902 reg = <0 0x1b100000 0 0x20000>;
903 interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_LOW>,
904 <GIC_SPI 199 IRQ_TYPE_LEVEL_LOW>,
905 <GIC_SPI 198 IRQ_TYPE_LEVEL_LOW>;
906 clocks = <&topckgen CLK_TOP_ETHIF_SEL>,
907 <ðsys CLK_ETHSYS_ESW>,
908 <ðsys CLK_ETHSYS_GP1>,
909 <ðsys CLK_ETHSYS_GP2>,
910 <&apmixedsys CLK_APMIXED_TRGPLL>;
911 clock-names = "ethif", "esw", "gp1", "gp2", "trgpll";
912 resets = <ðsys MT2701_ETHSYS_FE_RST>,
913 <ðsys MT2701_ETHSYS_GMAC_RST>,
914 <ðsys MT2701_ETHSYS_PPE_RST>;
915 reset-names = "fe", "gmac", "ppe";
916 power-domains = <&scpsys MT2701_POWER_DOMAIN_ETH>;
917 mediatek,ethsys = <ðsys>;
918 mediatek,pctl = <&syscfg_pctl_a>;
919 #address-cells = <1>;
924 crypto: crypto@1b240000 {
925 compatible = "mediatek,eip97-crypto";
926 reg = <0 0x1b240000 0 0x20000>;
927 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_LOW>,
928 <GIC_SPI 83 IRQ_TYPE_LEVEL_LOW>,
929 <GIC_SPI 84 IRQ_TYPE_LEVEL_LOW>,
930 <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>,
931 <GIC_SPI 97 IRQ_TYPE_LEVEL_LOW>;
932 clocks = <ðsys CLK_ETHSYS_CRYPTO>;
933 clock-names = "cryp";
934 power-domains = <&scpsys MT2701_POWER_DOMAIN_ETH>;
940 cir_pins_a:cir-default {
942 pinmux = <MT7623_PIN_46_IR_FUNC_IR>;
947 i2c0_pins_a: i2c0-default {
949 pinmux = <MT7623_PIN_75_SDA0_FUNC_SDA0>,
950 <MT7623_PIN_76_SCL0_FUNC_SCL0>;
955 i2c1_pins_a: i2c1-default {
957 pinmux = <MT7623_PIN_57_SDA1_FUNC_SDA1>,
958 <MT7623_PIN_58_SCL1_FUNC_SCL1>;
963 i2c1_pins_b: i2c1-alt {
965 pinmux = <MT7623_PIN_242_URTS2_FUNC_SCL1>,
966 <MT7623_PIN_243_UCTS2_FUNC_SDA1>;
971 i2c2_pins_a: i2c2-default {
973 pinmux = <MT7623_PIN_77_SDA2_FUNC_SDA2>,
974 <MT7623_PIN_78_SCL2_FUNC_SCL2>;
979 i2c2_pins_b: i2c2-alt {
981 pinmux = <MT7623_PIN_122_GPIO122_FUNC_SDA2>,
982 <MT7623_PIN_123_HTPLG_FUNC_SCL2>;
987 i2s0_pins_a: i2s0-default {
989 pinmux = <MT7623_PIN_49_I2S0_DATA_FUNC_I2S0_DATA>,
990 <MT7623_PIN_72_I2S0_DATA_IN_FUNC_I2S0_DATA_IN>,
991 <MT7623_PIN_73_I2S0_LRCK_FUNC_I2S0_LRCK>,
992 <MT7623_PIN_74_I2S0_BCK_FUNC_I2S0_BCK>,
993 <MT7623_PIN_126_I2S0_MCLK_FUNC_I2S0_MCLK>;
994 drive-strength = <MTK_DRIVE_12mA>;
999 i2s1_pins_a: i2s1-default {
1001 pinmux = <MT7623_PIN_33_I2S1_DATA_FUNC_I2S1_DATA>,
1002 <MT7623_PIN_34_I2S1_DATA_IN_FUNC_I2S1_DATA_IN>,
1003 <MT7623_PIN_35_I2S1_BCK_FUNC_I2S1_BCK>,
1004 <MT7623_PIN_36_I2S1_LRCK_FUNC_I2S1_LRCK>,
1005 <MT7623_PIN_37_I2S1_MCLK_FUNC_I2S1_MCLK>;
1006 drive-strength = <MTK_DRIVE_12mA>;
1011 key_pins_a: keys-alt {
1013 pinmux = <MT7623_PIN_256_GPIO256_FUNC_GPIO256>,
1014 <MT7623_PIN_257_GPIO257_FUNC_GPIO257> ;
1019 led_pins_a: leds-alt {
1021 pinmux = <MT7623_PIN_239_EXT_SDIO0_FUNC_GPIO239>,
1022 <MT7623_PIN_240_EXT_XCS_FUNC_GPIO240>,
1023 <MT7623_PIN_241_EXT_SCK_FUNC_GPIO241>;
1027 mmc0_pins_default: mmc0default {
1029 pinmux = <MT7623_PIN_111_MSDC0_DAT7_FUNC_MSDC0_DAT7>,
1030 <MT7623_PIN_112_MSDC0_DAT6_FUNC_MSDC0_DAT6>,
1031 <MT7623_PIN_113_MSDC0_DAT5_FUNC_MSDC0_DAT5>,
1032 <MT7623_PIN_114_MSDC0_DAT4_FUNC_MSDC0_DAT4>,
1033 <MT7623_PIN_118_MSDC0_DAT3_FUNC_MSDC0_DAT3>,
1034 <MT7623_PIN_119_MSDC0_DAT2_FUNC_MSDC0_DAT2>,
1035 <MT7623_PIN_120_MSDC0_DAT1_FUNC_MSDC0_DAT1>,
1036 <MT7623_PIN_121_MSDC0_DAT0_FUNC_MSDC0_DAT0>,
1037 <MT7623_PIN_116_MSDC0_CMD_FUNC_MSDC0_CMD>;
1043 pinmux = <MT7623_PIN_117_MSDC0_CLK_FUNC_MSDC0_CLK>;
1048 pinmux = <MT7623_PIN_115_MSDC0_RSTB_FUNC_MSDC0_RSTB>;
1053 mmc0_pins_uhs: mmc0 {
1055 pinmux = <MT7623_PIN_111_MSDC0_DAT7_FUNC_MSDC0_DAT7>,
1056 <MT7623_PIN_112_MSDC0_DAT6_FUNC_MSDC0_DAT6>,
1057 <MT7623_PIN_113_MSDC0_DAT5_FUNC_MSDC0_DAT5>,
1058 <MT7623_PIN_114_MSDC0_DAT4_FUNC_MSDC0_DAT4>,
1059 <MT7623_PIN_118_MSDC0_DAT3_FUNC_MSDC0_DAT3>,
1060 <MT7623_PIN_119_MSDC0_DAT2_FUNC_MSDC0_DAT2>,
1061 <MT7623_PIN_120_MSDC0_DAT1_FUNC_MSDC0_DAT1>,
1062 <MT7623_PIN_121_MSDC0_DAT0_FUNC_MSDC0_DAT0>,
1063 <MT7623_PIN_116_MSDC0_CMD_FUNC_MSDC0_CMD>;
1065 drive-strength = <MTK_DRIVE_2mA>;
1066 bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
1070 pinmux = <MT7623_PIN_117_MSDC0_CLK_FUNC_MSDC0_CLK>;
1071 drive-strength = <MTK_DRIVE_2mA>;
1072 bias-pull-down = <MTK_PUPD_SET_R1R0_01>;
1076 pinmux = <MT7623_PIN_115_MSDC0_RSTB_FUNC_MSDC0_RSTB>;
1081 mmc1_pins_default: mmc1default {
1083 pinmux = <MT7623_PIN_107_MSDC1_DAT0_FUNC_MSDC1_DAT0>,
1084 <MT7623_PIN_108_MSDC1_DAT1_FUNC_MSDC1_DAT1>,
1085 <MT7623_PIN_109_MSDC1_DAT2_FUNC_MSDC1_DAT2>,
1086 <MT7623_PIN_110_MSDC1_DAT3_FUNC_MSDC1_DAT3>,
1087 <MT7623_PIN_105_MSDC1_CMD_FUNC_MSDC1_CMD>;
1089 drive-strength = <MTK_DRIVE_4mA>;
1090 bias-pull-up = <MTK_PUPD_SET_R1R0_10>;
1094 pinmux = <MT7623_PIN_106_MSDC1_CLK_FUNC_MSDC1_CLK>;
1096 drive-strength = <MTK_DRIVE_4mA>;
1100 pinmux = <MT7623_PIN_29_EINT7_FUNC_MSDC1_WP>;
1106 pinmux = <MT7623_PIN_261_MSDC1_INS_FUNC_GPIO261>;
1111 mmc1_pins_uhs: mmc1 {
1113 pinmux = <MT7623_PIN_107_MSDC1_DAT0_FUNC_MSDC1_DAT0>,
1114 <MT7623_PIN_108_MSDC1_DAT1_FUNC_MSDC1_DAT1>,
1115 <MT7623_PIN_109_MSDC1_DAT2_FUNC_MSDC1_DAT2>,
1116 <MT7623_PIN_110_MSDC1_DAT3_FUNC_MSDC1_DAT3>,
1117 <MT7623_PIN_105_MSDC1_CMD_FUNC_MSDC1_CMD>;
1119 drive-strength = <MTK_DRIVE_4mA>;
1120 bias-pull-up = <MTK_PUPD_SET_R1R0_10>;
1124 pinmux = <MT7623_PIN_106_MSDC1_CLK_FUNC_MSDC1_CLK>;
1125 drive-strength = <MTK_DRIVE_4mA>;
1126 bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
1130 nand_pins_default: nanddefault {
1132 pinmux = <MT7623_PIN_116_MSDC0_CMD_FUNC_NALE>;
1133 drive-strength = <MTK_DRIVE_8mA>;
1134 bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
1138 pinmux = <MT7623_PIN_111_MSDC0_DAT7_FUNC_NLD7>,
1139 <MT7623_PIN_112_MSDC0_DAT6_FUNC_NLD6>,
1140 <MT7623_PIN_114_MSDC0_DAT4_FUNC_NLD4>,
1141 <MT7623_PIN_118_MSDC0_DAT3_FUNC_NLD3>,
1142 <MT7623_PIN_121_MSDC0_DAT0_FUNC_NLD0>,
1143 <MT7623_PIN_120_MSDC0_DAT1_FUNC_NLD1>,
1144 <MT7623_PIN_113_MSDC0_DAT5_FUNC_NLD5>,
1145 <MT7623_PIN_115_MSDC0_RSTB_FUNC_NLD8>,
1146 <MT7623_PIN_119_MSDC0_DAT2_FUNC_NLD2>;
1148 drive-strength = <MTK_DRIVE_8mA>;
1153 pinmux = <MT7623_PIN_117_MSDC0_CLK_FUNC_NWEB>;
1154 drive-strength = <MTK_DRIVE_8mA>;
1155 bias-pull-up = <MTK_PUPD_SET_R1R0_10>;
1159 pcie_default: pcie_pin_default {
1161 pinmux = <MT7623_PIN_208_AUD_EXT_CK1_FUNC_PCIE0_PERST_N>,
1162 <MT7623_PIN_209_AUD_EXT_CK2_FUNC_PCIE1_PERST_N>;
1167 pwm_pins_a: pwm-default {
1169 pinmux = <MT7623_PIN_203_PWM0_FUNC_PWM0>,
1170 <MT7623_PIN_204_PWM1_FUNC_PWM1>,
1171 <MT7623_PIN_205_PWM2_FUNC_PWM2>,
1172 <MT7623_PIN_206_PWM3_FUNC_PWM3>,
1173 <MT7623_PIN_207_PWM4_FUNC_PWM4>;
1177 spi0_pins_a: spi0-default {
1179 pinmux = <MT7623_PIN_53_SPI0_CSN_FUNC_SPI0_CS>,
1180 <MT7623_PIN_54_SPI0_CK_FUNC_SPI0_CK>,
1181 <MT7623_PIN_55_SPI0_MI_FUNC_SPI0_MI>,
1182 <MT7623_PIN_56_SPI0_MO_FUNC_SPI0_MO>;
1187 spi1_pins_a: spi1-default {
1189 pinmux = <MT7623_PIN_7_SPI1_CSN_FUNC_SPI1_CS>,
1190 <MT7623_PIN_199_SPI1_CK_FUNC_SPI1_CK>,
1191 <MT7623_PIN_8_SPI1_MI_FUNC_SPI1_MI>,
1192 <MT7623_PIN_9_SPI1_MO_FUNC_SPI1_MO>;
1196 spi2_pins_a: spi2-default {
1198 pinmux = <MT7623_PIN_101_SPI2_CSN_FUNC_SPI2_CS>,
1199 <MT7623_PIN_104_SPI2_CK_FUNC_SPI2_CK>,
1200 <MT7623_PIN_102_SPI2_MI_FUNC_SPI2_MI>,
1201 <MT7623_PIN_103_SPI2_MO_FUNC_SPI2_MO>;
1205 uart0_pins_a: uart0-default {
1207 pinmux = <MT7623_PIN_79_URXD0_FUNC_URXD0>,
1208 <MT7623_PIN_80_UTXD0_FUNC_UTXD0>;
1212 uart1_pins_a: uart1-default {
1214 pinmux = <MT7623_PIN_81_URXD1_FUNC_URXD1>,
1215 <MT7623_PIN_82_UTXD1_FUNC_UTXD1>;
1219 uart2_pins_a: uart2-default {
1221 pinmux = <MT7623_PIN_14_GPIO14_FUNC_URXD2>,
1222 <MT7623_PIN_15_GPIO15_FUNC_UTXD2>;
1226 uart2_pins_b: uart2-alt {
1228 pinmux = <MT7623_PIN_200_URXD2_FUNC_URXD2>,
1229 <MT7623_PIN_201_UTXD2_FUNC_UTXD2>;