sys/gnu/dts/arm/omap4.dtsi

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
   4  */
   5
   6 #include <dt-bindings/bus/ti-sysc.h>
   7 #include <dt-bindings/clock/omap4.h>
   8 #include <dt-bindings/gpio/gpio.h>
   9 #include <dt-bindings/interrupt-controller/arm-gic.h>
  10 #include <dt-bindings/pinctrl/omap.h>
  11 #include <dt-bindings/clock/omap4.h>
  12
  13 / {
  14         compatible = "ti,omap4430", "ti,omap4";
  15         interrupt-parent = <&wakeupgen>;
  16         #address-cells = <1>;
  17         #size-cells = <1>;
  18         chosen { };
  19
  20         aliases {
  21                 i2c0 = &i2c1;
  22                 i2c1 = &i2c2;
  23                 i2c2 = &i2c3;
  24                 i2c3 = &i2c4;
  25                 serial0 = &uart1;
  26                 serial1 = &uart2;
  27                 serial2 = &uart3;
  28                 serial3 = &uart4;
  29         };
  30
  31         cpus {
  32                 #address-cells = <1>;
  33                 #size-cells = <0>;
  34
  35                 cpu@0 {
  36                         compatible = "arm,cortex-a9";
  37                         device_type = "cpu";
  38                         next-level-cache = <&L2>;
  39                         reg = <0x0>;
  40
  41                         clocks = <&dpll_mpu_ck>;
  42                         clock-names = "cpu";
  43
  44                         clock-latency = <300000>; /* From omap-cpufreq driver */
  45                 };
  46                 cpu@1 {
  47                         compatible = "arm,cortex-a9";
  48                         device_type = "cpu";
  49                         next-level-cache = <&L2>;
  50                         reg = <0x1>;
  51                 };
  52         };
  53
  54         /*
  55          * Note that 4430 needs cross trigger interface (CTI) supported
  56          * before we can configure the interrupts. This means sampling
  57          * events are not supported for pmu. Note that 4460 does not use
  58          * CTI, see also 4460.dtsi.
  59          */
  60         pmu {
  61                 compatible = "arm,cortex-a9-pmu";
  62                 ti,hwmods = "debugss";
  63         };
  64
  65         gic: interrupt-controller@48241000 {
  66                 compatible = "arm,cortex-a9-gic";
  67                 interrupt-controller;
  68                 #interrupt-cells = <3>;
  69                 reg = <0x48241000 0x1000>,
  70                       <0x48240100 0x0100>;
  71                 interrupt-parent = <&gic>;
  72         };
  73
  74         L2: l2-cache-controller@48242000 {
  75                 compatible = "arm,pl310-cache";
  76                 reg = <0x48242000 0x1000>;
  77                 cache-unified;
  78                 cache-level = <2>;
  79         };
  80
  81         local-timer@48240600 {
  82                 compatible = "arm,cortex-a9-twd-timer";
  83                 clocks = <&mpu_periphclk>;
  84                 reg = <0x48240600 0x20>;
  85                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_EDGE_RISING)>;
  86                 interrupt-parent = <&gic>;
  87         };
  88
  89         wakeupgen: interrupt-controller@48281000 {
  90                 compatible = "ti,omap4-wugen-mpu";
  91                 interrupt-controller;
  92                 #interrupt-cells = <3>;
  93                 reg = <0x48281000 0x1000>;
  94                 interrupt-parent = <&gic>;
  95         };
  96
  97         /*
  98          * The soc node represents the soc top level view. It is used for IPs
  99          * that are not memory mapped in the MPU view or for the MPU itself.
 100          */
 101         soc {
 102                 compatible = "ti,omap-infra";
 103                 mpu {
 104                         compatible = "ti,omap4-mpu";
 105                         ti,hwmods = "mpu";
 106                         sram = <&ocmcram>;
 107                 };
 108
 109                 dsp {
 110                         compatible = "ti,omap3-c64";
 111                         ti,hwmods = "dsp";
 112                 };
 113
 114                 iva {
 115                         compatible = "ti,ivahd";
 116                         ti,hwmods = "iva";
 117                 };
 118         };
 119
 120         /*
 121          * XXX: Use a flat representation of the OMAP4 interconnect.
 122          * The real OMAP interconnect network is quite complex.
 123          * Since it will not bring real advantage to represent that in DT for
 124          * the moment, just use a fake OCP bus entry to represent the whole bus
 125          * hierarchy.
 126          */
 127         ocp {
 128                 compatible = "ti,omap4-l3-noc", "simple-bus";
 129                 #address-cells = <1>;
 130                 #size-cells = <1>;
 131                 ranges;
 132                 ti,hwmods = "l3_main_1", "l3_main_2", "l3_main_3";
 133                 reg = <0x44000000 0x1000>,
 134                       <0x44800000 0x2000>,
 135                       <0x45000000 0x1000>;
 136                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
 137                              <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 138
 139                 l4_wkup: interconnect@4a300000 {
 140                 };
 141
 142                 l4_cfg: interconnect@4a000000 {
 143                 };
 144
 145                 l4_per: interconnect@48000000 {
 146                 };
 147
 148                 l4_abe: interconnect@40100000 {
 149                 };
 150
 151                 ocmcram: sram@40304000 {
 152                         compatible = "mmio-sram";
 153                         reg = <0x40304000 0xa000>; /* 40k */
 154                 };
 155
 156                 gpmc: gpmc@50000000 {
 157                         compatible = "ti,omap4430-gpmc";
 158                         reg = <0x50000000 0x1000>;
 159                         #address-cells = <2>;
 160                         #size-cells = <1>;
 161                         interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
 162                         dmas = <&sdma 4>;
 163                         dma-names = "rxtx";
 164                         gpmc,num-cs = <8>;
 165                         gpmc,num-waitpins = <4>;
 166                         ti,hwmods = "gpmc";
 167                         ti,no-idle-on-init;
 168                         clocks = <&l3_div_ck>;
 169                         clock-names = "fck";
 170                         interrupt-controller;
 171                         #interrupt-cells = <2>;
 172                         gpio-controller;
 173                         #gpio-cells = <2>;
 174                 };
 175
 176                 target-module@52000000 {
 177                         compatible = "ti,sysc-omap4", "ti,sysc";
 178                         ti,hwmods = "iss";
 179                         reg = <0x52000000 0x4>,
 180                               <0x52000010 0x4>;
 181                         reg-names = "rev", "sysc";
 182                         ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
 183                         ti,sysc-midle = <SYSC_IDLE_FORCE>,
 184                                         <SYSC_IDLE_NO>,
 185                                         <SYSC_IDLE_SMART>,
 186                                         <SYSC_IDLE_SMART_WKUP>;
 187                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
 188                                         <SYSC_IDLE_NO>,
 189                                         <SYSC_IDLE_SMART>,
 190                                         <SYSC_IDLE_SMART_WKUP>;
 191                         ti,sysc-delay-us = <2>;
 192                         clocks = <&iss_clkctrl OMAP4_ISS_CLKCTRL 0>;
 193                         clock-names = "fck";
 194                         #address-cells = <1>;
 195                         #size-cells = <1>;
 196                         ranges = <0 0x52000000 0x1000000>;
 197
 198                         /* No child device binding, driver in staging */
 199                 };
 200
 201                 target-module@55082000 {
 202                         compatible = "ti,sysc-omap2", "ti,sysc";
 203                         reg = <0x55082000 0x4>,
 204                               <0x55082010 0x4>,
 205                               <0x55082014 0x4>;
 206                         reg-names = "rev", "sysc", "syss";
 207                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
 208                                         <SYSC_IDLE_NO>,
 209                                         <SYSC_IDLE_SMART>;
 210                         ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
 211                                          SYSC_OMAP2_SOFTRESET |
 212                                          SYSC_OMAP2_AUTOIDLE)>;
 213                         clocks = <&ducati_clkctrl OMAP4_IPU_CLKCTRL 0>;
 214                         clock-names = "fck";
 215                         resets = <&prm_core 2>;
 216                         reset-names = "rstctrl";
 217                         ranges = <0x0 0x55082000 0x100>;
 218                         #size-cells = <1>;
 219                         #address-cells = <1>;
 220
 221                         mmu_ipu: mmu@0 {
 222                                 compatible = "ti,omap4-iommu";
 223                                 reg = <0x0 0x100>;
 224                                 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
 225                                 #iommu-cells = <0>;
 226                                 ti,iommu-bus-err-back;
 227                         };
 228                 };
 229
 230                 target-module@4012c000 {
 231                         compatible = "ti,sysc-omap4", "ti,sysc";
 232                         reg = <0x4012c000 0x4>,
 233                               <0x4012c010 0x4>;
 234                         reg-names = "rev", "sysc";
 235                         ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
 236                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
 237                                         <SYSC_IDLE_NO>,
 238                                         <SYSC_IDLE_SMART>,
 239                                         <SYSC_IDLE_SMART_WKUP>;
 240                         clocks = <&abe_clkctrl OMAP4_SLIMBUS1_CLKCTRL 0>;
 241                         clock-names = "fck";
 242                         #address-cells = <1>;
 243                         #size-cells = <1>;
 244                         ranges = <0x00000000 0x4012c000 0x1000>, /* MPU */
 245                                  <0x4902c000 0x4902c000 0x1000>; /* L3 */
 246
 247                         /* No child device binding or driver in mainline */
 248                 };
 249
 250                 dmm@4e000000 {
 251                         compatible = "ti,omap4-dmm";
 252                         reg = <0x4e000000 0x800>;
 253                         interrupts = <0 113 0x4>;
 254                         ti,hwmods = "dmm";
 255                 };
 256
 257                 emif1: emif@4c000000 {
 258                         compatible = "ti,emif-4d";
 259                         reg = <0x4c000000 0x100>;
 260                         interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
 261                         ti,hwmods = "emif1";
 262                         ti,no-idle-on-init;
 263                         phy-type = <1>;
 264                         hw-caps-read-idle-ctrl;
 265                         hw-caps-ll-interface;
 266                         hw-caps-temp-alert;
 267                 };
 268
 269                 emif2: emif@4d000000 {
 270                         compatible = "ti,emif-4d";
 271                         reg = <0x4d000000 0x100>;
 272                         interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
 273                         ti,hwmods = "emif2";
 274                         ti,no-idle-on-init;
 275                         phy-type = <1>;
 276                         hw-caps-read-idle-ctrl;
 277                         hw-caps-ll-interface;
 278                         hw-caps-temp-alert;
 279                 };
 280
 281                 aes1_target: target-module@4b501000 {
 282                         compatible = "ti,sysc-omap2", "ti,sysc";
 283                         reg = <0x4b501080 0x4>,
 284                               <0x4b501084 0x4>,
 285                               <0x4b501088 0x4>;
 286                         reg-names = "rev", "sysc", "syss";
 287                         ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
 288                                          SYSC_OMAP2_AUTOIDLE)>;
 289                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
 290                                         <SYSC_IDLE_NO>,
 291                                         <SYSC_IDLE_SMART>,
 292                                         <SYSC_IDLE_SMART_WKUP>;
 293                         ti,syss-mask = <1>;
 294                         /* Domains (P, C): l4per_pwrdm, l4_secure_clkdm */
 295                         clocks = <&l4_secure_clkctrl OMAP4_AES1_CLKCTRL 0>;
 296                         clock-names = "fck";
 297                         #address-cells = <1>;
 298                         #size-cells = <1>;
 299                         ranges = <0x0 0x4b501000 0x1000>;
 300
 301                         aes1: aes@0 {
 302                                 compatible = "ti,omap4-aes";
 303                                 reg = <0 0xa0>;
 304                                 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
 305                                 dmas = <&sdma 111>, <&sdma 110>;
 306                                 dma-names = "tx", "rx";
 307                         };
 308                 };
 309
 310                 aes2_target: target-module@4b701000 {
 311                         compatible = "ti,sysc-omap2", "ti,sysc";
 312                         reg = <0x4b701080 0x4>,
 313                               <0x4b701084 0x4>,
 314                               <0x4b701088 0x4>;
 315                         reg-names = "rev", "sysc", "syss";
 316                         ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
 317                                          SYSC_OMAP2_AUTOIDLE)>;
 318                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
 319                                         <SYSC_IDLE_NO>,
 320                                         <SYSC_IDLE_SMART>,
 321                                         <SYSC_IDLE_SMART_WKUP>;
 322                         ti,syss-mask = <1>;
 323                         /* Domains (P, C): l4per_pwrdm, l4_secure_clkdm */
 324                         clocks = <&l4_secure_clkctrl OMAP4_AES2_CLKCTRL 0>;
 325                         clock-names = "fck";
 326                         #address-cells = <1>;
 327                         #size-cells = <1>;
 328                         ranges = <0x0 0x4b701000 0x1000>;
 329
 330                         aes2: aes@0 {
 331                                 compatible = "ti,omap4-aes";
 332                                 reg = <0 0xa0>;
 333                                 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
 334                                 dmas = <&sdma 114>, <&sdma 113>;
 335                                 dma-names = "tx", "rx";
 336                         };
 337                 };
 338
 339                 sham_target: target-module@4b100000 {
 340                         compatible = "ti,sysc-omap3-sham", "ti,sysc";
 341                         reg = <0x4b100100 0x4>,
 342                               <0x4b100110 0x4>,
 343                               <0x4b100114 0x4>;
 344                         reg-names = "rev", "sysc", "syss";
 345                         ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
 346                                          SYSC_OMAP2_AUTOIDLE)>;
 347                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
 348                                         <SYSC_IDLE_NO>,
 349                                         <SYSC_IDLE_SMART>;
 350                         ti,syss-mask = <1>;
 351                         /* Domains (P, C): l4per_pwrdm, l4_secure_clkdm */
 352                         clocks = <&l4_secure_clkctrl OMAP4_SHA2MD5_CLKCTRL 0>;
 353                         clock-names = "fck";
 354                         #address-cells = <1>;
 355                         #size-cells = <1>;
 356                         ranges = <0x0 0x4b100000 0x1000>;
 357
 358                         sham: sham@0 {
 359                                 compatible = "ti,omap4-sham";
 360                                 reg = <0 0x300>;
 361                                 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
 362                                 dmas = <&sdma 119>;
 363                                 dma-names = "rx";
 364                         };
 365                 };
 366
 367                 abb_mpu: regulator-abb-mpu {
 368                         compatible = "ti,abb-v2";
 369                         regulator-name = "abb_mpu";
 370                         #address-cells = <0>;
 371                         #size-cells = <0>;
 372                         ti,tranxdone-status-mask = <0x80>;
 373                         clocks = <&sys_clkin_ck>;
 374                         ti,settling-time = <50>;
 375                         ti,clock-cycles = <16>;
 376
 377                         status = "disabled";
 378                 };
 379
 380                 abb_iva: regulator-abb-iva {
 381                         compatible = "ti,abb-v2";
 382                         regulator-name = "abb_iva";
 383                         #address-cells = <0>;
 384                         #size-cells = <0>;
 385                         ti,tranxdone-status-mask = <0x80000000>;
 386                         clocks = <&sys_clkin_ck>;
 387                         ti,settling-time = <50>;
 388                         ti,clock-cycles = <16>;
 389
 390                         status = "disabled";
 391                 };
 392
 393                 target-module@56000000 {
 394                         compatible = "ti,sysc-omap4", "ti,sysc";
 395                         reg = <0x5600fe00 0x4>,
 396                               <0x5600fe10 0x4>;
 397                         reg-names = "rev", "sysc";
 398                         ti,sysc-midle = <SYSC_IDLE_FORCE>,
 399                                         <SYSC_IDLE_NO>,
 400                                         <SYSC_IDLE_SMART>,
 401                                         <SYSC_IDLE_SMART_WKUP>;
 402                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
 403                                         <SYSC_IDLE_NO>,
 404                                         <SYSC_IDLE_SMART>,
 405                                         <SYSC_IDLE_SMART_WKUP>;
 406                         clocks = <&l3_gfx_clkctrl OMAP4_GPU_CLKCTRL 0>;
 407                         clock-names = "fck";
 408                         #address-cells = <1>;
 409                         #size-cells = <1>;
 410                         ranges = <0 0x56000000 0x2000000>;
 411
 412                         /*
 413                          * Closed source PowerVR driver, no child device
 414                          * binding or driver in mainline
 415                          */
 416                 };
 417
 418                 dss: dss@58000000 {
 419                         compatible = "ti,omap4-dss";
 420                         reg = <0x58000000 0x80>;
 421                         status = "disabled";
 422                         ti,hwmods = "dss_core";
 423                         clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 8>;
 424                         clock-names = "fck";
 425                         #address-cells = <1>;
 426                         #size-cells = <1>;
 427                         ranges;
 428
 429                         dispc@58001000 {
 430                                 compatible = "ti,omap4-dispc";
 431                                 reg = <0x58001000 0x1000>;
 432                                 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
 433                                 ti,hwmods = "dss_dispc";
 434                                 clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 8>;
 435                                 clock-names = "fck";
 436                         };
 437
 438                         rfbi: encoder@58002000  {
 439                                 compatible = "ti,omap4-rfbi";
 440                                 reg = <0x58002000 0x1000>;
 441                                 status = "disabled";
 442                                 ti,hwmods = "dss_rfbi";
 443                                 clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 8>, <&l3_div_ck>;
 444                                 clock-names = "fck", "ick";
 445                         };
 446
 447                         venc: encoder@58003000 {
 448                                 compatible = "ti,omap4-venc";
 449                                 reg = <0x58003000 0x1000>;
 450                                 status = "disabled";
 451                                 ti,hwmods = "dss_venc";
 452                                 clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 11>;
 453                                 clock-names = "fck";
 454                         };
 455
 456                         dsi1: encoder@58004000 {
 457                                 compatible = "ti,omap4-dsi";
 458                                 reg = <0x58004000 0x200>,
 459                                       <0x58004200 0x40>,
 460                                       <0x58004300 0x20>;
 461                                 reg-names = "proto", "phy", "pll";
 462                                 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
 463                                 status = "disabled";
 464                                 ti,hwmods = "dss_dsi1";
 465                                 clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 8>,
 466                                          <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 10>;
 467                                 clock-names = "fck", "sys_clk";
 468                         };
 469
 470                         dsi2: encoder@58005000 {
 471                                 compatible = "ti,omap4-dsi";
 472                                 reg = <0x58005000 0x200>,
 473                                       <0x58005200 0x40>,
 474                                       <0x58005300 0x20>;
 475                                 reg-names = "proto", "phy", "pll";
 476                                 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
 477                                 status = "disabled";
 478                                 ti,hwmods = "dss_dsi2";
 479                                 clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 8>,
 480                                          <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 10>;
 481                                 clock-names = "fck", "sys_clk";
 482                         };
 483
 484                         hdmi: encoder@58006000 {
 485                                 compatible = "ti,omap4-hdmi";
 486                                 reg = <0x58006000 0x200>,
 487                                       <0x58006200 0x100>,
 488                                       <0x58006300 0x100>,
 489                                       <0x58006400 0x1000>;
 490                                 reg-names = "wp", "pll", "phy", "core";
 491                                 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
 492                                 status = "disabled";
 493                                 ti,hwmods = "dss_hdmi";
 494                                 clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 9>,
 495                                          <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 10>;
 496                                 clock-names = "fck", "sys_clk";
 497                                 dmas = <&sdma 76>;
 498                                 dma-names = "audio_tx";
 499                         };
 500                 };
 501         };
 502 };
 503
 504 #include "omap4-l4.dtsi"
 505 #include "omap4-l4-abe.dtsi"
 506 #include "omap44xx-clocks.dtsi"
 507
 508 &prm {
 509         prm_tesla: prm@400 {
 510                 compatible = "ti,omap4-prm-inst", "ti,omap-prm-inst";
 511                 reg = <0x400 0x100>;
 512                 #reset-cells = <1>;
 513         };
 514
 515         prm_core: prm@700 {
 516                 compatible = "ti,omap4-prm-inst", "ti,omap-prm-inst";
 517                 reg = <0x700 0x100>;
 518                 #reset-cells = <1>;
 519         };
 520
 521         prm_ivahd: prm@f00 {
 522                 compatible = "ti,omap4-prm-inst", "ti,omap-prm-inst";
 523                 reg = <0xf00 0x100>;
 524                 #reset-cells = <1>;
 525         };
 526
 527         prm_device: prm@1b00 {
 528                 compatible = "ti,omap4-prm-inst", "ti,omap-prm-inst";
 529                 reg = <0x1b00 0x40>;
 530                 #reset-cells = <1>;
 531         };
 532 };