sys/gnu/dts/arm/omap5.dtsi

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
   4  *
   5  * Based on "omap4.dtsi"
   6  */
   7
   8 #include <dt-bindings/bus/ti-sysc.h>
   9 #include <dt-bindings/gpio/gpio.h>
  10 #include <dt-bindings/interrupt-controller/arm-gic.h>
  11 #include <dt-bindings/pinctrl/omap.h>
  12 #include <dt-bindings/clock/omap5.h>
  13
  14 / {
  15         #address-cells = <2>;
  16         #size-cells = <2>;
  17
  18         compatible = "ti,omap5";
  19         interrupt-parent = <&wakeupgen>;
  20         chosen { };
  21
  22         aliases {
  23                 i2c0 = &i2c1;
  24                 i2c1 = &i2c2;
  25                 i2c2 = &i2c3;
  26                 i2c3 = &i2c4;
  27                 i2c4 = &i2c5;
  28                 serial0 = &uart1;
  29                 serial1 = &uart2;
  30                 serial2 = &uart3;
  31                 serial3 = &uart4;
  32                 serial4 = &uart5;
  33                 serial5 = &uart6;
  34         };
  35
  36         cpus {
  37                 #address-cells = <1>;
  38                 #size-cells = <0>;
  39
  40                 cpu0: cpu@0 {
  41                         device_type = "cpu";
  42                         compatible = "arm,cortex-a15";
  43                         reg = <0x0>;
  44
  45                         operating-points = <
  46                                 /* kHz    uV */
  47                                 1000000 1060000
  48                                 1500000 1250000
  49                         >;
  50
  51                         clocks = <&dpll_mpu_ck>;
  52                         clock-names = "cpu";
  53
  54                         clock-latency = <300000>; /* From omap-cpufreq driver */
  55
  56                         /* cooling options */
  57                         #cooling-cells = <2>; /* min followed by max */
  58                 };
  59                 cpu@1 {
  60                         device_type = "cpu";
  61                         compatible = "arm,cortex-a15";
  62                         reg = <0x1>;
  63
  64                         operating-points = <
  65                                 /* kHz    uV */
  66                                 1000000 1060000
  67                                 1500000 1250000
  68                         >;
  69
  70                         clocks = <&dpll_mpu_ck>;
  71                         clock-names = "cpu";
  72
  73                         clock-latency = <300000>; /* From omap-cpufreq driver */
  74
  75                         /* cooling options */
  76                         #cooling-cells = <2>; /* min followed by max */
  77                 };
  78         };
  79
  80         thermal-zones {
  81                 #include "omap4-cpu-thermal.dtsi"
  82                 #include "omap5-gpu-thermal.dtsi"
  83                 #include "omap5-core-thermal.dtsi"
  84         };
  85
  86         timer {
  87                 compatible = "arm,armv7-timer";
  88                 /* PPI secure/nonsecure IRQ */
  89                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>,
  90                              <GIC_PPI 14 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>,
  91                              <GIC_PPI 11 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>,
  92                              <GIC_PPI 10 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>;
  93                 interrupt-parent = <&gic>;
  94         };
  95
  96         pmu {
  97                 compatible = "arm,cortex-a15-pmu";
  98                 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
  99                              <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
 100         };
 101
 102         gic: interrupt-controller@48211000 {
 103                 compatible = "arm,cortex-a15-gic";
 104                 interrupt-controller;
 105                 #interrupt-cells = <3>;
 106                 reg = <0 0x48211000 0 0x1000>,
 107                       <0 0x48212000 0 0x2000>,
 108                       <0 0x48214000 0 0x2000>,
 109                       <0 0x48216000 0 0x2000>;
 110                 interrupt-parent = <&gic>;
 111         };
 112
 113         wakeupgen: interrupt-controller@48281000 {
 114                 compatible = "ti,omap5-wugen-mpu", "ti,omap4-wugen-mpu";
 115                 interrupt-controller;
 116                 #interrupt-cells = <3>;
 117                 reg = <0 0x48281000 0 0x1000>;
 118                 interrupt-parent = <&gic>;
 119         };
 120
 121         /*
 122          * The soc node represents the soc top level view. It is used for IPs
 123          * that are not memory mapped in the MPU view or for the MPU itself.
 124          */
 125         soc {
 126                 compatible = "ti,omap-infra";
 127                 mpu {
 128                         compatible = "ti,omap4-mpu";
 129                         ti,hwmods = "mpu";
 130                         sram = <&ocmcram>;
 131                 };
 132         };
 133
 134         /*
 135          * XXX: Use a flat representation of the OMAP3 interconnect.
 136          * The real OMAP interconnect network is quite complex.
 137          * Since it will not bring real advantage to represent that in DT for
 138          * the moment, just use a fake OCP bus entry to represent the whole bus
 139          * hierarchy.
 140          */
 141         ocp {
 142                 compatible = "ti,omap5-l3-noc", "simple-bus";
 143                 #address-cells = <1>;
 144                 #size-cells = <1>;
 145                 ranges = <0 0 0 0xc0000000>;
 146                 dma-ranges = <0x80000000 0x0 0x80000000 0x80000000>;
 147                 ti,hwmods = "l3_main_1", "l3_main_2", "l3_main_3";
 148                 reg = <0 0x44000000 0 0x2000>,
 149                       <0 0x44800000 0 0x3000>,
 150                       <0 0x45000000 0 0x4000>;
 151                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
 152                              <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 153
 154                 l4_wkup: interconnect@4ae00000 {
 155                 };
 156
 157                 l4_cfg: interconnect@4a000000 {
 158                 };
 159
 160                 l4_per: interconnect@48000000 {
 161                 };
 162
 163                 l4_abe: interconnect@40100000 {
 164                 };
 165
 166                 ocmcram: sram@40300000 {
 167                         compatible = "mmio-sram";
 168                         reg = <0x40300000 0x20000>; /* 128k */
 169                 };
 170
 171                 gpmc: gpmc@50000000 {
 172                         compatible = "ti,omap4430-gpmc";
 173                         reg = <0x50000000 0x1000>;
 174                         #address-cells = <2>;
 175                         #size-cells = <1>;
 176                         interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
 177                         dmas = <&sdma 4>;
 178                         dma-names = "rxtx";
 179                         gpmc,num-cs = <8>;
 180                         gpmc,num-waitpins = <4>;
 181                         ti,hwmods = "gpmc";
 182                         clocks = <&l3_iclk_div>;
 183                         clock-names = "fck";
 184                         interrupt-controller;
 185                         #interrupt-cells = <2>;
 186                         gpio-controller;
 187                         #gpio-cells = <2>;
 188                 };
 189
 190                 target-module@55082000 {
 191                         compatible = "ti,sysc-omap2", "ti,sysc";
 192                         reg = <0x55082000 0x4>,
 193                               <0x55082010 0x4>,
 194                               <0x55082014 0x4>;
 195                         reg-names = "rev", "sysc", "syss";
 196                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
 197                                         <SYSC_IDLE_NO>,
 198                                         <SYSC_IDLE_SMART>;
 199                         ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
 200                                          SYSC_OMAP2_SOFTRESET |
 201                                          SYSC_OMAP2_AUTOIDLE)>;
 202                         clocks = <&ipu_clkctrl OMAP5_MMU_IPU_CLKCTRL 0>;
 203                         clock-names = "fck";
 204                         resets = <&prm_core 2>;
 205                         reset-names = "rstctrl";
 206                         ranges = <0x0 0x55082000 0x100>;
 207                         #size-cells = <1>;
 208                         #address-cells = <1>;
 209
 210                         mmu_ipu: mmu@0 {
 211                                 compatible = "ti,omap4-iommu";
 212                                 reg = <0x0 0x100>;
 213                                 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
 214                                 #iommu-cells = <0>;
 215                                 ti,iommu-bus-err-back;
 216                         };
 217                 };
 218
 219                 dmm@4e000000 {
 220                         compatible = "ti,omap5-dmm";
 221                         reg = <0x4e000000 0x800>;
 222                         interrupts = <0 113 0x4>;
 223                         ti,hwmods = "dmm";
 224                 };
 225
 226                 emif1: emif@4c000000 {
 227                         compatible      = "ti,emif-4d5";
 228                         ti,hwmods       = "emif1";
 229                         ti,no-idle-on-init;
 230                         phy-type        = <2>; /* DDR PHY type: Intelli PHY */
 231                         reg = <0x4c000000 0x400>;
 232                         interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
 233                         hw-caps-read-idle-ctrl;
 234                         hw-caps-ll-interface;
 235                         hw-caps-temp-alert;
 236                 };
 237
 238                 emif2: emif@4d000000 {
 239                         compatible      = "ti,emif-4d5";
 240                         ti,hwmods       = "emif2";
 241                         ti,no-idle-on-init;
 242                         phy-type        = <2>; /* DDR PHY type: Intelli PHY */
 243                         reg = <0x4d000000 0x400>;
 244                         interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
 245                         hw-caps-read-idle-ctrl;
 246                         hw-caps-ll-interface;
 247                         hw-caps-temp-alert;
 248                 };
 249
 250                 bandgap: bandgap@4a0021e0 {
 251                         reg = <0x4a0021e0 0xc
 252                                0x4a00232c 0xc
 253                                0x4a002380 0x2c
 254                                0x4a0023C0 0x3c>;
 255                         interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
 256                         compatible = "ti,omap5430-bandgap";
 257
 258                         #thermal-sensor-cells = <1>;
 259                 };
 260
 261                 /* OCP2SCP3 */
 262                 sata: sata@4a141100 {
 263                         compatible = "snps,dwc-ahci";
 264                         reg = <0x4a140000 0x1100>, <0x4a141100 0x7>;
 265                         interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
 266                         phys = <&sata_phy>;
 267                         phy-names = "sata-phy";
 268                         clocks = <&l3init_clkctrl OMAP5_SATA_CLKCTRL 8>;
 269                         ti,hwmods = "sata";
 270                         ports-implemented = <0x1>;
 271                 };
 272
 273                 target-module@56000000 {
 274                         compatible = "ti,sysc-omap4", "ti,sysc";
 275                         reg = <0x5600fe00 0x4>,
 276                               <0x5600fe10 0x4>;
 277                         reg-names = "rev", "sysc";
 278                         ti,sysc-midle = <SYSC_IDLE_FORCE>,
 279                                         <SYSC_IDLE_NO>,
 280                                         <SYSC_IDLE_SMART>;
 281                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
 282                                         <SYSC_IDLE_NO>,
 283                                         <SYSC_IDLE_SMART>;
 284                         clocks = <&gpu_clkctrl OMAP5_GPU_CLKCTRL 0>;
 285                         clock-names = "fck";
 286                         #address-cells = <1>;
 287                         #size-cells = <1>;
 288                         ranges = <0 0x56000000 0x2000000>;
 289
 290                         /*
 291                          * Closed source PowerVR driver, no child device
 292                          * binding or driver in mainline
 293                          */
 294                 };
 295
 296                 dss: dss@58000000 {
 297                         compatible = "ti,omap5-dss";
 298                         reg = <0x58000000 0x80>;
 299                         status = "disabled";
 300                         ti,hwmods = "dss_core";
 301                         clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>;
 302                         clock-names = "fck";
 303                         #address-cells = <1>;
 304                         #size-cells = <1>;
 305                         ranges;
 306
 307                         dispc@58001000 {
 308                                 compatible = "ti,omap5-dispc";
 309                                 reg = <0x58001000 0x1000>;
 310                                 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
 311                                 ti,hwmods = "dss_dispc";
 312                                 clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>;
 313                                 clock-names = "fck";
 314                         };
 315
 316                         rfbi: encoder@58002000  {
 317                                 compatible = "ti,omap5-rfbi";
 318                                 reg = <0x58002000 0x100>;
 319                                 status = "disabled";
 320                                 ti,hwmods = "dss_rfbi";
 321                                 clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>, <&l3_iclk_div>;
 322                                 clock-names = "fck", "ick";
 323                         };
 324
 325                         dsi1: encoder@58004000 {
 326                                 compatible = "ti,omap5-dsi";
 327                                 reg = <0x58004000 0x200>,
 328                                       <0x58004200 0x40>,
 329                                       <0x58004300 0x40>;
 330                                 reg-names = "proto", "phy", "pll";
 331                                 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
 332                                 status = "disabled";
 333                                 ti,hwmods = "dss_dsi1";
 334                                 clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>,
 335                                          <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 10>;
 336                                 clock-names = "fck", "sys_clk";
 337                         };
 338
 339                         dsi2: encoder@58005000 {
 340                                 compatible = "ti,omap5-dsi";
 341                                 reg = <0x58009000 0x200>,
 342                                       <0x58009200 0x40>,
 343                                       <0x58009300 0x40>;
 344                                 reg-names = "proto", "phy", "pll";
 345                                 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
 346                                 status = "disabled";
 347                                 ti,hwmods = "dss_dsi2";
 348                                 clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>,
 349                                          <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 10>;
 350                                 clock-names = "fck", "sys_clk";
 351                         };
 352
 353                         hdmi: encoder@58060000 {
 354                                 compatible = "ti,omap5-hdmi";
 355                                 reg = <0x58040000 0x200>,
 356                                       <0x58040200 0x80>,
 357                                       <0x58040300 0x80>,
 358                                       <0x58060000 0x19000>;
 359                                 reg-names = "wp", "pll", "phy", "core";
 360                                 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
 361                                 status = "disabled";
 362                                 ti,hwmods = "dss_hdmi";
 363                                 clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 9>,
 364                                          <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 10>;
 365                                 clock-names = "fck", "sys_clk";
 366                                 dmas = <&sdma 76>;
 367                                 dma-names = "audio_tx";
 368                         };
 369                 };
 370
 371                 abb_mpu: regulator-abb-mpu {
 372                         compatible = "ti,abb-v2";
 373                         regulator-name = "abb_mpu";
 374                         #address-cells = <0>;
 375                         #size-cells = <0>;
 376                         clocks = <&sys_clkin>;
 377                         ti,settling-time = <50>;
 378                         ti,clock-cycles = <16>;
 379
 380                         reg = <0x4ae07cdc 0x8>, <0x4ae06014 0x4>,
 381                               <0x4a0021c4 0x8>, <0x4ae0c318 0x4>;
 382                         reg-names = "base-address", "int-address",
 383                                     "efuse-address", "ldo-address";
 384                         ti,tranxdone-status-mask = <0x80>;
 385                         /* LDOVBBMPU_MUX_CTRL */
 386                         ti,ldovbb-override-mask = <0x400>;
 387                         /* LDOVBBMPU_VSET_OUT */
 388                         ti,ldovbb-vset-mask = <0x1F>;
 389
 390                         /*
 391                          * NOTE: only FBB mode used but actual vset will
 392                          * determine final biasing
 393                          */
 394                         ti,abb_info = <
 395                         /*uV            ABB     efuse   rbb_m fbb_m     vset_m*/
 396                         1060000         0       0x0     0 0x02000000 0x01F00000
 397                         1250000         0       0x4     0 0x02000000 0x01F00000
 398                         >;
 399                 };
 400
 401                 abb_mm: regulator-abb-mm {
 402                         compatible = "ti,abb-v2";
 403                         regulator-name = "abb_mm";
 404                         #address-cells = <0>;
 405                         #size-cells = <0>;
 406                         clocks = <&sys_clkin>;
 407                         ti,settling-time = <50>;
 408                         ti,clock-cycles = <16>;
 409
 410                         reg = <0x4ae07ce4 0x8>, <0x4ae06010 0x4>,
 411                               <0x4a0021a4 0x8>, <0x4ae0c314 0x4>;
 412                         reg-names = "base-address", "int-address",
 413                                     "efuse-address", "ldo-address";
 414                         ti,tranxdone-status-mask = <0x80000000>;
 415                         /* LDOVBBMM_MUX_CTRL */
 416                         ti,ldovbb-override-mask = <0x400>;
 417                         /* LDOVBBMM_VSET_OUT */
 418                         ti,ldovbb-vset-mask = <0x1F>;
 419
 420                         /*
 421                          * NOTE: only FBB mode used but actual vset will
 422                          * determine final biasing
 423                          */
 424                         ti,abb_info = <
 425                         /*uV            ABB     efuse   rbb_m fbb_m     vset_m*/
 426                         1025000         0       0x0     0 0x02000000 0x01F00000
 427                         1120000         0       0x4     0 0x02000000 0x01F00000
 428                         >;
 429                 };
 430         };
 431 };
 432
 433 &cpu_thermal {
 434         polling-delay = <500>; /* milliseconds */
 435         coefficients = <65 (-1791)>;
 436 };
 437
 438 #include "omap5-l4.dtsi"
 439 #include "omap54xx-clocks.dtsi"
 440
 441 &gpu_thermal {
 442         coefficients = <117 (-2992)>;
 443 };
 444
 445 &core_thermal {
 446         coefficients = <0 2000>;
 447 };
 448
 449 #include "omap5-l4-abe.dtsi"
 450 #include "omap54xx-clocks.dtsi"
 451
 452 &prm {
 453         prm_dsp: prm@400 {
 454                 compatible = "ti,omap5-prm-inst", "ti,omap-prm-inst";
 455                 reg = <0x400 0x100>;
 456                 #reset-cells = <1>;
 457         };
 458
 459         prm_core: prm@700 {
 460                 compatible = "ti,omap5-prm-inst", "ti,omap-prm-inst";
 461                 reg = <0x700 0x100>;
 462                 #reset-cells = <1>;
 463         };
 464
 465         prm_iva: prm@1200 {
 466                 compatible = "ti,omap5-prm-inst", "ti,omap-prm-inst";
 467                 reg = <0x1200 0x100>;
 468                 #reset-cells = <1>;
 469         };
 470
 471         prm_device: prm@1c00 {
 472                 compatible = "ti,omap5-prm-inst", "ti,omap-prm-inst";
 473                 reg = <0x1c00 0x100>;
 474                 #reset-cells = <1>;
 475         };
 476 };