2 * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 * Based on "omap4.dtsi"
10 #include <dt-bindings/bus/ti-sysc.h>
11 #include <dt-bindings/gpio/gpio.h>
12 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #include <dt-bindings/pinctrl/omap.h>
14 #include <dt-bindings/clock/omap5.h>
20 compatible = "ti,omap5";
21 interrupt-parent = <&wakeupgen>;
44 compatible = "arm,cortex-a15";
53 clocks = <&dpll_mpu_ck>;
56 clock-latency = <300000>; /* From omap-cpufreq driver */
59 #cooling-cells = <2>; /* min followed by max */
63 compatible = "arm,cortex-a15";
72 clocks = <&dpll_mpu_ck>;
75 clock-latency = <300000>; /* From omap-cpufreq driver */
78 #cooling-cells = <2>; /* min followed by max */
83 #include "omap4-cpu-thermal.dtsi"
84 #include "omap5-gpu-thermal.dtsi"
85 #include "omap5-core-thermal.dtsi"
89 compatible = "arm,armv7-timer";
90 /* PPI secure/nonsecure IRQ */
91 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>,
92 <GIC_PPI 14 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>,
93 <GIC_PPI 11 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>,
94 <GIC_PPI 10 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>;
95 interrupt-parent = <&gic>;
99 compatible = "arm,cortex-a15-pmu";
100 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
101 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
104 gic: interrupt-controller@48211000 {
105 compatible = "arm,cortex-a15-gic";
106 interrupt-controller;
107 #interrupt-cells = <3>;
108 reg = <0 0x48211000 0 0x1000>,
109 <0 0x48212000 0 0x2000>,
110 <0 0x48214000 0 0x2000>,
111 <0 0x48216000 0 0x2000>;
112 interrupt-parent = <&gic>;
115 wakeupgen: interrupt-controller@48281000 {
116 compatible = "ti,omap5-wugen-mpu", "ti,omap4-wugen-mpu";
117 interrupt-controller;
118 #interrupt-cells = <3>;
119 reg = <0 0x48281000 0 0x1000>;
120 interrupt-parent = <&gic>;
124 * The soc node represents the soc top level view. It is used for IPs
125 * that are not memory mapped in the MPU view or for the MPU itself.
128 compatible = "ti,omap-infra";
130 compatible = "ti,omap4-mpu";
137 * XXX: Use a flat representation of the OMAP3 interconnect.
138 * The real OMAP interconnect network is quite complex.
139 * Since it will not bring real advantage to represent that in DT for
140 * the moment, just use a fake OCP bus entry to represent the whole bus
144 compatible = "ti,omap5-l3-noc", "simple-bus";
145 #address-cells = <1>;
147 ranges = <0 0 0 0xc0000000>;
148 ti,hwmods = "l3_main_1", "l3_main_2", "l3_main_3";
149 reg = <0 0x44000000 0 0x2000>,
150 <0 0x44800000 0 0x3000>,
151 <0 0x45000000 0 0x4000>;
152 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
153 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
155 l4_wkup: interconnect@4ae00000 {
158 l4_cfg: interconnect@4a000000 {
161 l4_per: interconnect@48000000 {
164 ocmcram: ocmcram@40300000 {
165 compatible = "mmio-sram";
166 reg = <0x40300000 0x20000>; /* 128k */
169 gpmc: gpmc@50000000 {
170 compatible = "ti,omap4430-gpmc";
171 reg = <0x50000000 0x1000>;
172 #address-cells = <2>;
174 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
178 gpmc,num-waitpins = <4>;
180 clocks = <&l3_iclk_div>;
182 interrupt-controller;
183 #interrupt-cells = <2>;
188 mmu_dsp: mmu@4a066000 {
189 compatible = "ti,omap4-iommu";
190 reg = <0x4a066000 0x100>;
191 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
192 ti,hwmods = "mmu_dsp";
196 mmu_ipu: mmu@55082000 {
197 compatible = "ti,omap4-iommu";
198 reg = <0x55082000 0x100>;
199 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
200 ti,hwmods = "mmu_ipu";
202 ti,iommu-bus-err-back;
205 mcpdm: mcpdm@40132000 {
206 compatible = "ti,omap4-mcpdm";
207 reg = <0x40132000 0x7f>, /* MPU private access */
208 <0x49032000 0x7f>; /* L3 Interconnect */
209 reg-names = "mpu", "dma";
210 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
214 dma-names = "up_link", "dn_link";
218 dmic: dmic@4012e000 {
219 compatible = "ti,omap4-dmic";
220 reg = <0x4012e000 0x7f>, /* MPU private access */
221 <0x4902e000 0x7f>; /* L3 Interconnect */
222 reg-names = "mpu", "dma";
223 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
226 dma-names = "up_link";
230 mcbsp1: mcbsp@40122000 {
231 compatible = "ti,omap4-mcbsp";
232 reg = <0x40122000 0xff>, /* MPU private access */
233 <0x49022000 0xff>; /* L3 Interconnect */
234 reg-names = "mpu", "dma";
235 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
236 interrupt-names = "common";
237 ti,buffer-size = <128>;
238 ti,hwmods = "mcbsp1";
241 dma-names = "tx", "rx";
245 mcbsp2: mcbsp@40124000 {
246 compatible = "ti,omap4-mcbsp";
247 reg = <0x40124000 0xff>, /* MPU private access */
248 <0x49024000 0xff>; /* L3 Interconnect */
249 reg-names = "mpu", "dma";
250 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
251 interrupt-names = "common";
252 ti,buffer-size = <128>;
253 ti,hwmods = "mcbsp2";
256 dma-names = "tx", "rx";
260 mcbsp3: mcbsp@40126000 {
261 compatible = "ti,omap4-mcbsp";
262 reg = <0x40126000 0xff>, /* MPU private access */
263 <0x49026000 0xff>; /* L3 Interconnect */
264 reg-names = "mpu", "dma";
265 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
266 interrupt-names = "common";
267 ti,buffer-size = <128>;
268 ti,hwmods = "mcbsp3";
271 dma-names = "tx", "rx";
275 timer5: timer@40138000 {
276 compatible = "ti,omap5430-timer";
277 reg = <0x40138000 0x80>,
279 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
280 ti,hwmods = "timer5";
285 timer6: timer@4013a000 {
286 compatible = "ti,omap5430-timer";
287 reg = <0x4013a000 0x80>,
289 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
290 ti,hwmods = "timer6";
295 timer7: timer@4013c000 {
296 compatible = "ti,omap5430-timer";
297 reg = <0x4013c000 0x80>,
299 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
300 ti,hwmods = "timer7";
304 timer8: timer@4013e000 {
305 compatible = "ti,omap5430-timer";
306 reg = <0x4013e000 0x80>,
308 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
309 ti,hwmods = "timer8";
315 compatible = "ti,omap5-dmm";
316 reg = <0x4e000000 0x800>;
317 interrupts = <0 113 0x4>;
321 emif1: emif@4c000000 {
322 compatible = "ti,emif-4d5";
325 phy-type = <2>; /* DDR PHY type: Intelli PHY */
326 reg = <0x4c000000 0x400>;
327 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
328 hw-caps-read-idle-ctrl;
329 hw-caps-ll-interface;
333 emif2: emif@4d000000 {
334 compatible = "ti,emif-4d5";
337 phy-type = <2>; /* DDR PHY type: Intelli PHY */
338 reg = <0x4d000000 0x400>;
339 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
340 hw-caps-read-idle-ctrl;
341 hw-caps-ll-interface;
345 bandgap: bandgap@4a0021e0 {
346 reg = <0x4a0021e0 0xc
350 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
351 compatible = "ti,omap5430-bandgap";
353 #thermal-sensor-cells = <1>;
357 sata: sata@4a141100 {
358 compatible = "snps,dwc-ahci";
359 reg = <0x4a140000 0x1100>, <0x4a141100 0x7>;
360 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
362 phy-names = "sata-phy";
363 clocks = <&l3init_clkctrl OMAP5_SATA_CLKCTRL 8>;
365 ports-implemented = <0x1>;
369 compatible = "ti,omap5-dss";
370 reg = <0x58000000 0x80>;
372 ti,hwmods = "dss_core";
373 clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>;
375 #address-cells = <1>;
380 compatible = "ti,omap5-dispc";
381 reg = <0x58001000 0x1000>;
382 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
383 ti,hwmods = "dss_dispc";
384 clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>;
388 rfbi: encoder@58002000 {
389 compatible = "ti,omap5-rfbi";
390 reg = <0x58002000 0x100>;
392 ti,hwmods = "dss_rfbi";
393 clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>, <&l3_iclk_div>;
394 clock-names = "fck", "ick";
397 dsi1: encoder@58004000 {
398 compatible = "ti,omap5-dsi";
399 reg = <0x58004000 0x200>,
402 reg-names = "proto", "phy", "pll";
403 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
405 ti,hwmods = "dss_dsi1";
406 clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>,
407 <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 10>;
408 clock-names = "fck", "sys_clk";
411 dsi2: encoder@58005000 {
412 compatible = "ti,omap5-dsi";
413 reg = <0x58009000 0x200>,
416 reg-names = "proto", "phy", "pll";
417 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
419 ti,hwmods = "dss_dsi2";
420 clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>,
421 <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 10>;
422 clock-names = "fck", "sys_clk";
425 hdmi: encoder@58060000 {
426 compatible = "ti,omap5-hdmi";
427 reg = <0x58040000 0x200>,
430 <0x58060000 0x19000>;
431 reg-names = "wp", "pll", "phy", "core";
432 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
434 ti,hwmods = "dss_hdmi";
435 clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 9>,
436 <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 10>;
437 clock-names = "fck", "sys_clk";
439 dma-names = "audio_tx";
443 abb_mpu: regulator-abb-mpu {
444 compatible = "ti,abb-v2";
445 regulator-name = "abb_mpu";
446 #address-cells = <0>;
448 clocks = <&sys_clkin>;
449 ti,settling-time = <50>;
450 ti,clock-cycles = <16>;
452 reg = <0x4ae07cdc 0x8>, <0x4ae06014 0x4>,
453 <0x4a0021c4 0x8>, <0x4ae0c318 0x4>;
454 reg-names = "base-address", "int-address",
455 "efuse-address", "ldo-address";
456 ti,tranxdone-status-mask = <0x80>;
457 /* LDOVBBMPU_MUX_CTRL */
458 ti,ldovbb-override-mask = <0x400>;
459 /* LDOVBBMPU_VSET_OUT */
460 ti,ldovbb-vset-mask = <0x1F>;
463 * NOTE: only FBB mode used but actual vset will
464 * determine final biasing
467 /*uV ABB efuse rbb_m fbb_m vset_m*/
468 1060000 0 0x0 0 0x02000000 0x01F00000
469 1250000 0 0x4 0 0x02000000 0x01F00000
473 abb_mm: regulator-abb-mm {
474 compatible = "ti,abb-v2";
475 regulator-name = "abb_mm";
476 #address-cells = <0>;
478 clocks = <&sys_clkin>;
479 ti,settling-time = <50>;
480 ti,clock-cycles = <16>;
482 reg = <0x4ae07ce4 0x8>, <0x4ae06010 0x4>,
483 <0x4a0021a4 0x8>, <0x4ae0c314 0x4>;
484 reg-names = "base-address", "int-address",
485 "efuse-address", "ldo-address";
486 ti,tranxdone-status-mask = <0x80000000>;
487 /* LDOVBBMM_MUX_CTRL */
488 ti,ldovbb-override-mask = <0x400>;
489 /* LDOVBBMM_VSET_OUT */
490 ti,ldovbb-vset-mask = <0x1F>;
493 * NOTE: only FBB mode used but actual vset will
494 * determine final biasing
497 /*uV ABB efuse rbb_m fbb_m vset_m*/
498 1025000 0 0x0 0 0x02000000 0x01F00000
499 1120000 0 0x4 0 0x02000000 0x01F00000
506 polling-delay = <500>; /* milliseconds */
507 coefficients = <65 (-1791)>;
510 #include "omap5-l4.dtsi"
511 #include "omap54xx-clocks.dtsi"
514 coefficients = <117 (-2992)>;
518 coefficients = <0 2000>;