2 * Copyright (c) 2015, The Linux Foundation. All rights reserved.
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 and
6 * only version 2 as published by the Free Software Foundation.
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
16 #include "skeleton.dtsi"
17 #include <dt-bindings/clock/qcom,gcc-ipq4019.h>
18 #include <dt-bindings/interrupt-controller/arm-gic.h>
19 #include <dt-bindings/interrupt-controller/irq.h>
22 model = "Qualcomm Technologies, Inc. IPQ4019";
23 compatible = "qcom,ipq4019";
24 interrupt-parent = <&intc>;
27 #address-cells = <0x1>;
31 smem_region: smem@87e00000 {
32 reg = <0x87e00000 0x080000>;
37 reg = <0x87e80000 0x180000>;
54 compatible = "arm,cortex-a7";
55 enable-method = "qcom,kpss-acc-v2";
56 next-level-cache = <&L2>;
60 clocks = <&gcc GCC_APPS_CLK_SRC>;
61 clock-frequency = <0>;
62 clock-latency = <256000>;
63 operating-points-v2 = <&cpu0_opp_table>;
68 compatible = "arm,cortex-a7";
69 enable-method = "qcom,kpss-acc-v2";
70 next-level-cache = <&L2>;
74 clocks = <&gcc GCC_APPS_CLK_SRC>;
75 clock-frequency = <0>;
76 clock-latency = <256000>;
77 operating-points-v2 = <&cpu0_opp_table>;
82 compatible = "arm,cortex-a7";
83 enable-method = "qcom,kpss-acc-v2";
84 next-level-cache = <&L2>;
88 clocks = <&gcc GCC_APPS_CLK_SRC>;
89 clock-frequency = <0>;
90 clock-latency = <256000>;
91 operating-points-v2 = <&cpu0_opp_table>;
96 compatible = "arm,cortex-a7";
97 enable-method = "qcom,kpss-acc-v2";
98 next-level-cache = <&L2>;
102 clocks = <&gcc GCC_APPS_CLK_SRC>;
103 clock-frequency = <0>;
104 clock-latency = <256000>;
105 operating-points-v2 = <&cpu0_opp_table>;
109 compatible = "cache";
114 cpu0_opp_table: opp_table0 {
115 compatible = "operating-points-v2";
119 opp-hz = /bits/ 64 <48000000>;
120 clock-latency-ns = <256000>;
123 opp-hz = /bits/ 64 <200000000>;
124 clock-latency-ns = <256000>;
127 opp-hz = /bits/ 64 <500000000>;
128 clock-latency-ns = <256000>;
131 opp-hz = /bits/ 64 <716000000>;
132 clock-latency-ns = <256000>;
137 compatible = "arm,cortex-a7-pmu";
138 interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) |
139 IRQ_TYPE_LEVEL_HIGH)>;
143 sleep_clk: sleep_clk {
144 compatible = "fixed-clock";
145 clock-frequency = <32768>;
150 compatible = "fixed-clock";
151 clock-frequency = <48000000>;
158 compatible = "qcom,scm-ipq4019";
163 compatible = "arm,armv7-timer";
164 interrupts = <1 2 0xf08>,
168 clock-frequency = <48000000>;
172 #address-cells = <1>;
175 compatible = "simple-bus";
177 intc: interrupt-controller@b000000 {
178 compatible = "qcom,msm-qgic2";
179 interrupt-controller;
180 #interrupt-cells = <3>;
181 reg = <0x0b000000 0x1000>,
185 gcc: clock-controller@1800000 {
186 compatible = "qcom,gcc-ipq4019";
189 reg = <0x1800000 0x60000>;
193 compatible = "qcom,prng";
194 reg = <0x22000 0x140>;
195 clocks = <&gcc GCC_PRNG_AHB_CLK>;
196 clock-names = "core";
200 tlmm: pinctrl@1000000 {
201 compatible = "qcom,ipq4019-pinctrl";
202 reg = <0x01000000 0x300000>;
205 interrupt-controller;
206 #interrupt-cells = <2>;
207 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
210 blsp_dma: dma@7884000 {
211 compatible = "qcom,bam-v1.7.0";
212 reg = <0x07884000 0x23000>;
213 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
214 clocks = <&gcc GCC_BLSP1_AHB_CLK>;
215 clock-names = "bam_clk";
221 blsp1_spi1: spi@78b5000 { /* BLSP1 QUP1 */
222 compatible = "qcom,spi-qup-v2.2.1";
223 reg = <0x78b5000 0x600>;
224 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
225 clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>,
226 <&gcc GCC_BLSP1_AHB_CLK>;
227 clock-names = "core", "iface";
228 #address-cells = <1>;
230 dmas = <&blsp_dma 5>, <&blsp_dma 4>;
231 dma-names = "rx", "tx";
235 blsp1_spi2: spi@78b6000 { /* BLSP1 QUP2 */
236 compatible = "qcom,spi-qup-v2.2.1";
237 reg = <0x78b6000 0x600>;
238 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
239 clocks = <&gcc GCC_BLSP1_QUP2_SPI_APPS_CLK>,
240 <&gcc GCC_BLSP1_AHB_CLK>;
241 clock-names = "core", "iface";
242 #address-cells = <1>;
244 dmas = <&blsp_dma 7>, <&blsp_dma 6>;
245 dma-names = "rx", "tx";
249 blsp1_i2c3: i2c@78b7000 { /* BLSP1 QUP3 */
250 compatible = "qcom,i2c-qup-v2.2.1";
251 reg = <0x78b7000 0x600>;
252 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
253 clocks = <&gcc GCC_BLSP1_AHB_CLK>,
254 <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>;
255 clock-names = "iface", "core";
256 #address-cells = <1>;
258 dmas = <&blsp_dma 9>, <&blsp_dma 8>;
259 dma-names = "rx", "tx";
263 blsp1_i2c4: i2c@78b8000 { /* BLSP1 QUP4 */
264 compatible = "qcom,i2c-qup-v2.2.1";
265 reg = <0x78b8000 0x600>;
266 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
267 clocks = <&gcc GCC_BLSP1_AHB_CLK>,
268 <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>;
269 clock-names = "iface", "core";
270 #address-cells = <1>;
272 dmas = <&blsp_dma 11>, <&blsp_dma 10>;
273 dma-names = "rx", "tx";
277 cryptobam: dma@8e04000 {
278 compatible = "qcom,bam-v1.7.0";
279 reg = <0x08e04000 0x20000>;
280 interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>;
281 clocks = <&gcc GCC_CRYPTO_AHB_CLK>;
282 clock-names = "bam_clk";
285 qcom,controlled-remotely;
290 compatible = "qcom,crypto-v5.1";
291 reg = <0x08e3a000 0x6000>;
292 clocks = <&gcc GCC_CRYPTO_AHB_CLK>,
293 <&gcc GCC_CRYPTO_AXI_CLK>,
294 <&gcc GCC_CRYPTO_CLK>;
295 clock-names = "iface", "bus", "core";
296 dmas = <&cryptobam 2>, <&cryptobam 3>;
297 dma-names = "rx", "tx";
301 acc0: clock-controller@b088000 {
302 compatible = "qcom,kpss-acc-v2";
303 reg = <0x0b088000 0x1000>, <0xb008000 0x1000>;
306 acc1: clock-controller@b098000 {
307 compatible = "qcom,kpss-acc-v2";
308 reg = <0x0b098000 0x1000>, <0xb008000 0x1000>;
311 acc2: clock-controller@b0a8000 {
312 compatible = "qcom,kpss-acc-v2";
313 reg = <0x0b0a8000 0x1000>, <0xb008000 0x1000>;
316 acc3: clock-controller@b0b8000 {
317 compatible = "qcom,kpss-acc-v2";
318 reg = <0x0b0b8000 0x1000>, <0xb008000 0x1000>;
321 saw0: regulator@b089000 {
322 compatible = "qcom,saw2";
323 reg = <0x0b089000 0x1000>, <0x0b009000 0x1000>;
327 saw1: regulator@b099000 {
328 compatible = "qcom,saw2";
329 reg = <0x0b099000 0x1000>, <0x0b009000 0x1000>;
333 saw2: regulator@b0a9000 {
334 compatible = "qcom,saw2";
335 reg = <0x0b0a9000 0x1000>, <0x0b009000 0x1000>;
339 saw3: regulator@b0b9000 {
340 compatible = "qcom,saw2";
341 reg = <0x0b0b9000 0x1000>, <0x0b009000 0x1000>;
345 blsp1_uart1: serial@78af000 {
346 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
347 reg = <0x78af000 0x200>;
348 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
350 clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>,
351 <&gcc GCC_BLSP1_AHB_CLK>;
352 clock-names = "core", "iface";
353 dmas = <&blsp_dma 1>, <&blsp_dma 0>;
354 dma-names = "rx", "tx";
357 blsp1_uart2: serial@78b0000 {
358 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
359 reg = <0x78b0000 0x200>;
360 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
362 clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>,
363 <&gcc GCC_BLSP1_AHB_CLK>;
364 clock-names = "core", "iface";
365 dmas = <&blsp_dma 3>, <&blsp_dma 2>;
366 dma-names = "rx", "tx";
370 compatible = "qcom,kpss-wdt", "qcom,kpss-wdt-ipq4019";
371 reg = <0xb017000 0x40>;
372 clocks = <&sleep_clk>;
378 compatible = "qcom,pshold";
379 reg = <0x4ab000 0x4>;
382 pcie0: pci@40000000 {
383 compatible = "qcom,pcie-ipq4019", "snps,dw-pcie";
384 reg = <0x40000000 0xf1d
388 reg-names = "dbi", "elbi", "parf", "config";
390 linux,pci-domain = <0>;
391 bus-range = <0x00 0xff>;
393 #address-cells = <3>;
396 ranges = <0x81000000 0 0x40200000 0x40200000 0 0x00100000
397 0x82000000 0 0x40300000 0x40300000 0 0x400000>;
399 interrupts = <GIC_SPI 141 IRQ_TYPE_EDGE_RISING>;
400 interrupt-names = "msi";
401 #interrupt-cells = <1>;
402 interrupt-map-mask = <0 0 0 0x7>;
403 interrupt-map = <0 0 0 1 &intc 0 142 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
404 <0 0 0 2 &intc 0 143 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
405 <0 0 0 3 &intc 0 144 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
406 <0 0 0 4 &intc 0 145 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
407 clocks = <&gcc GCC_PCIE_AHB_CLK>,
408 <&gcc GCC_PCIE_AXI_M_CLK>,
409 <&gcc GCC_PCIE_AXI_S_CLK>;
414 resets = <&gcc PCIE_AXI_M_ARES>,
415 <&gcc PCIE_AXI_S_ARES>,
416 <&gcc PCIE_PIPE_ARES>,
417 <&gcc PCIE_AXI_M_VMIDMT_ARES>,
418 <&gcc PCIE_AXI_S_XPU_ARES>,
419 <&gcc PCIE_PARF_XPU_ARES>,
420 <&gcc PCIE_PHY_ARES>,
421 <&gcc PCIE_AXI_M_STICKY_ARES>,
422 <&gcc PCIE_PIPE_STICKY_ARES>,
423 <&gcc PCIE_PWR_ARES>,
424 <&gcc PCIE_AHB_ARES>,
425 <&gcc PCIE_PHY_AHB_ARES>;
426 reset-names = "axi_m",
442 qpic_bam: dma@7984000 {
443 compatible = "qcom,bam-v1.7.0";
444 reg = <0x7984000 0x1a000>;
445 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
446 clocks = <&gcc GCC_QPIC_CLK>;
447 clock-names = "bam_clk";
453 nand: qpic-nand@79b0000 {
454 compatible = "qcom,ipq4019-nand";
455 reg = <0x79b0000 0x1000>;
456 #address-cells = <1>;
458 clocks = <&gcc GCC_QPIC_CLK>,
459 <&gcc GCC_QPIC_AHB_CLK>;
460 clock-names = "core", "aon";
462 dmas = <&qpic_bam 0>,
465 dma-names = "tx", "rx", "cmd";
471 nand-ecc-strength = <4>;
472 nand-ecc-step-size = <512>;
473 nand-bus-width = <8>;
477 wifi0: wifi@a000000 {
478 compatible = "qcom,ipq4019-wifi";
479 reg = <0xa000000 0x200000>;
480 resets = <&gcc WIFI0_CPU_INIT_RESET>,
481 <&gcc WIFI0_RADIO_SRIF_RESET>,
482 <&gcc WIFI0_RADIO_WARM_RESET>,
483 <&gcc WIFI0_RADIO_COLD_RESET>,
484 <&gcc WIFI0_CORE_WARM_RESET>,
485 <&gcc WIFI0_CORE_COLD_RESET>;
486 reset-names = "wifi_cpu_init", "wifi_radio_srif",
487 "wifi_radio_warm", "wifi_radio_cold",
488 "wifi_core_warm", "wifi_core_cold";
489 clocks = <&gcc GCC_WCSS2G_CLK>,
490 <&gcc GCC_WCSS2G_REF_CLK>,
491 <&gcc GCC_WCSS2G_RTC_CLK>;
492 clock-names = "wifi_wcss_cmd", "wifi_wcss_ref",
494 interrupts = <GIC_SPI 32 IRQ_TYPE_EDGE_RISING>,
495 <GIC_SPI 33 IRQ_TYPE_EDGE_RISING>,
496 <GIC_SPI 34 IRQ_TYPE_EDGE_RISING>,
497 <GIC_SPI 35 IRQ_TYPE_EDGE_RISING>,
498 <GIC_SPI 36 IRQ_TYPE_EDGE_RISING>,
499 <GIC_SPI 37 IRQ_TYPE_EDGE_RISING>,
500 <GIC_SPI 38 IRQ_TYPE_EDGE_RISING>,
501 <GIC_SPI 39 IRQ_TYPE_EDGE_RISING>,
502 <GIC_SPI 40 IRQ_TYPE_EDGE_RISING>,
503 <GIC_SPI 41 IRQ_TYPE_EDGE_RISING>,
504 <GIC_SPI 42 IRQ_TYPE_EDGE_RISING>,
505 <GIC_SPI 43 IRQ_TYPE_EDGE_RISING>,
506 <GIC_SPI 44 IRQ_TYPE_EDGE_RISING>,
507 <GIC_SPI 45 IRQ_TYPE_EDGE_RISING>,
508 <GIC_SPI 46 IRQ_TYPE_EDGE_RISING>,
509 <GIC_SPI 47 IRQ_TYPE_EDGE_RISING>,
510 <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
511 interrupt-names = "msi0", "msi1", "msi2", "msi3",
512 "msi4", "msi5", "msi6", "msi7",
513 "msi8", "msi9", "msi10", "msi11",
514 "msi12", "msi13", "msi14", "msi15",
519 wifi1: wifi@a800000 {
520 compatible = "qcom,ipq4019-wifi";
521 reg = <0xa800000 0x200000>;
522 resets = <&gcc WIFI1_CPU_INIT_RESET>,
523 <&gcc WIFI1_RADIO_SRIF_RESET>,
524 <&gcc WIFI1_RADIO_WARM_RESET>,
525 <&gcc WIFI1_RADIO_COLD_RESET>,
526 <&gcc WIFI1_CORE_WARM_RESET>,
527 <&gcc WIFI1_CORE_COLD_RESET>;
528 reset-names = "wifi_cpu_init", "wifi_radio_srif",
529 "wifi_radio_warm", "wifi_radio_cold",
530 "wifi_core_warm", "wifi_core_cold";
531 clocks = <&gcc GCC_WCSS5G_CLK>,
532 <&gcc GCC_WCSS5G_REF_CLK>,
533 <&gcc GCC_WCSS5G_RTC_CLK>;
534 clock-names = "wifi_wcss_cmd", "wifi_wcss_ref",
536 interrupts = <GIC_SPI 48 IRQ_TYPE_EDGE_RISING>,
537 <GIC_SPI 49 IRQ_TYPE_EDGE_RISING>,
538 <GIC_SPI 50 IRQ_TYPE_EDGE_RISING>,
539 <GIC_SPI 51 IRQ_TYPE_EDGE_RISING>,
540 <GIC_SPI 52 IRQ_TYPE_EDGE_RISING>,
541 <GIC_SPI 53 IRQ_TYPE_EDGE_RISING>,
542 <GIC_SPI 54 IRQ_TYPE_EDGE_RISING>,
543 <GIC_SPI 55 IRQ_TYPE_EDGE_RISING>,
544 <GIC_SPI 56 IRQ_TYPE_EDGE_RISING>,
545 <GIC_SPI 57 IRQ_TYPE_EDGE_RISING>,
546 <GIC_SPI 58 IRQ_TYPE_EDGE_RISING>,
547 <GIC_SPI 59 IRQ_TYPE_EDGE_RISING>,
548 <GIC_SPI 60 IRQ_TYPE_EDGE_RISING>,
549 <GIC_SPI 61 IRQ_TYPE_EDGE_RISING>,
550 <GIC_SPI 62 IRQ_TYPE_EDGE_RISING>,
551 <GIC_SPI 63 IRQ_TYPE_EDGE_RISING>,
552 <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
553 interrupt-names = "msi0", "msi1", "msi2", "msi3",
554 "msi4", "msi5", "msi6", "msi7",
555 "msi8", "msi9", "msi10", "msi11",
556 "msi12", "msi13", "msi14", "msi15",