sys/gnu/dts/arm/qcom-ipq4019.dtsi

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (c) 2015, The Linux Foundation. All rights reserved.
   4  */
   5
   6 /dts-v1/;
   7
   8 #include <dt-bindings/clock/qcom,gcc-ipq4019.h>
   9 #include <dt-bindings/interrupt-controller/arm-gic.h>
  10 #include <dt-bindings/interrupt-controller/irq.h>
  11
  12 / {
  13         #address-cells = <1>;
  14         #size-cells = <1>;
  15
  16         model = "Qualcomm Technologies, Inc. IPQ4019";
  17         compatible = "qcom,ipq4019";
  18         interrupt-parent = <&intc>;
  19
  20         reserved-memory {
  21                 #address-cells = <0x1>;
  22                 #size-cells = <0x1>;
  23                 ranges;
  24
  25                 smem_region: smem@87e00000 {
  26                         reg = <0x87e00000 0x080000>;
  27                         no-map;
  28                 };
  29
  30                 tz@87e80000 {
  31                         reg = <0x87e80000 0x180000>;
  32                         no-map;
  33                 };
  34         };
  35
  36         aliases {
  37                 spi0 = &blsp1_spi1;
  38                 spi1 = &blsp1_spi2;
  39                 i2c0 = &blsp1_i2c3;
  40                 i2c1 = &blsp1_i2c4;
  41         };
  42
  43         cpus {
  44                 #address-cells = <1>;
  45                 #size-cells = <0>;
  46                 cpu@0 {
  47                         device_type = "cpu";
  48                         compatible = "arm,cortex-a7";
  49                         enable-method = "qcom,kpss-acc-v2";
  50                         next-level-cache = <&L2>;
  51                         qcom,acc = <&acc0>;
  52                         qcom,saw = <&saw0>;
  53                         reg = <0x0>;
  54                         clocks = <&gcc GCC_APPS_CLK_SRC>;
  55                         clock-frequency = <0>;
  56                         clock-latency = <256000>;
  57                         operating-points-v2 = <&cpu0_opp_table>;
  58                 };
  59
  60                 cpu@1 {
  61                         device_type = "cpu";
  62                         compatible = "arm,cortex-a7";
  63                         enable-method = "qcom,kpss-acc-v2";
  64                         next-level-cache = <&L2>;
  65                         qcom,acc = <&acc1>;
  66                         qcom,saw = <&saw1>;
  67                         reg = <0x1>;
  68                         clocks = <&gcc GCC_APPS_CLK_SRC>;
  69                         clock-frequency = <0>;
  70                         clock-latency = <256000>;
  71                         operating-points-v2 = <&cpu0_opp_table>;
  72                 };
  73
  74                 cpu@2 {
  75                         device_type = "cpu";
  76                         compatible = "arm,cortex-a7";
  77                         enable-method = "qcom,kpss-acc-v2";
  78                         next-level-cache = <&L2>;
  79                         qcom,acc = <&acc2>;
  80                         qcom,saw = <&saw2>;
  81                         reg = <0x2>;
  82                         clocks = <&gcc GCC_APPS_CLK_SRC>;
  83                         clock-frequency = <0>;
  84                         clock-latency = <256000>;
  85                         operating-points-v2 = <&cpu0_opp_table>;
  86                 };
  87
  88                 cpu@3 {
  89                         device_type = "cpu";
  90                         compatible = "arm,cortex-a7";
  91                         enable-method = "qcom,kpss-acc-v2";
  92                         next-level-cache = <&L2>;
  93                         qcom,acc = <&acc3>;
  94                         qcom,saw = <&saw3>;
  95                         reg = <0x3>;
  96                         clocks = <&gcc GCC_APPS_CLK_SRC>;
  97                         clock-frequency = <0>;
  98                         clock-latency = <256000>;
  99                         operating-points-v2 = <&cpu0_opp_table>;
 100                 };
 101
 102                 L2: l2-cache {
 103                         compatible = "cache";
 104                         cache-level = <2>;
 105                 };
 106         };
 107
 108         cpu0_opp_table: opp_table0 {
 109                 compatible = "operating-points-v2";
 110                 opp-shared;
 111
 112                 opp-48000000 {
 113                         opp-hz = /bits/ 64 <48000000>;
 114                         clock-latency-ns = <256000>;
 115                 };
 116                 opp-200000000 {
 117                         opp-hz = /bits/ 64 <200000000>;
 118                         clock-latency-ns = <256000>;
 119                 };
 120                 opp-500000000 {
 121                         opp-hz = /bits/ 64 <500000000>;
 122                         clock-latency-ns = <256000>;
 123                 };
 124                 opp-716000000 {
 125                         opp-hz = /bits/ 64 <716000000>;
 126                         clock-latency-ns = <256000>;
 127                 };
 128         };
 129
 130         memory {
 131                 device_type = "memory";
 132                 reg = <0x0 0x0>;
 133         };
 134
 135         pmu {
 136                 compatible = "arm,cortex-a7-pmu";
 137                 interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) |
 138                                          IRQ_TYPE_LEVEL_HIGH)>;
 139         };
 140
 141         clocks {
 142                 sleep_clk: sleep_clk {
 143                         compatible = "fixed-clock";
 144                         clock-frequency = <32768>;
 145                         #clock-cells = <0>;
 146                 };
 147
 148                 xo: xo {
 149                         compatible = "fixed-clock";
 150                         clock-frequency = <48000000>;
 151                         #clock-cells = <0>;
 152                 };
 153         };
 154
 155         firmware {
 156                 scm {
 157                         compatible = "qcom,scm-ipq4019";
 158                 };
 159         };
 160
 161         timer {
 162                 compatible = "arm,armv7-timer";
 163                 interrupts = <1 2 0xf08>,
 164                              <1 3 0xf08>,
 165                              <1 4 0xf08>,
 166                              <1 1 0xf08>;
 167                 clock-frequency = <48000000>;
 168         };
 169
 170         soc {
 171                 #address-cells = <1>;
 172                 #size-cells = <1>;
 173                 ranges;
 174                 compatible = "simple-bus";
 175
 176                 intc: interrupt-controller@b000000 {
 177                         compatible = "qcom,msm-qgic2";
 178                         interrupt-controller;
 179                         #interrupt-cells = <3>;
 180                         reg = <0x0b000000 0x1000>,
 181                         <0x0b002000 0x1000>;
 182                 };
 183
 184                 gcc: clock-controller@1800000 {
 185                         compatible = "qcom,gcc-ipq4019";
 186                         #clock-cells = <1>;
 187                         #reset-cells = <1>;
 188                         reg = <0x1800000 0x60000>;
 189                 };
 190
 191                 rng@22000 {
 192                         compatible = "qcom,prng";
 193                         reg = <0x22000 0x140>;
 194                         clocks = <&gcc GCC_PRNG_AHB_CLK>;
 195                         clock-names = "core";
 196                         status = "disabled";
 197                 };
 198
 199                 tlmm: pinctrl@1000000 {
 200                         compatible = "qcom,ipq4019-pinctrl";
 201                         reg = <0x01000000 0x300000>;
 202                         gpio-controller;
 203                         #gpio-cells = <2>;
 204                         interrupt-controller;
 205                         #interrupt-cells = <2>;
 206                         interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
 207                 };
 208
 209                 sdhci: sdhci@7824900 {
 210                         compatible = "qcom,sdhci-msm-v4";
 211                         reg = <0x7824900 0x11c>, <0x7824000 0x800>;
 212                         interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
 213                         interrupt-names = "hc_irq", "pwr_irq";
 214                         bus-width = <8>;
 215                         clocks = <&gcc GCC_SDCC1_APPS_CLK>, <&gcc GCC_SDCC1_AHB_CLK>,
 216                                  <&gcc GCC_DCD_XO_CLK>;
 217                         clock-names = "core", "iface", "xo";
 218                         status = "disabled";
 219                 };
 220
 221                 blsp_dma: dma@7884000 {
 222                         compatible = "qcom,bam-v1.7.0";
 223                         reg = <0x07884000 0x23000>;
 224                         interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
 225                         clocks = <&gcc GCC_BLSP1_AHB_CLK>;
 226                         clock-names = "bam_clk";
 227                         #dma-cells = <1>;
 228                         qcom,ee = <0>;
 229                         status = "disabled";
 230                 };
 231
 232                 blsp1_spi1: spi@78b5000 { /* BLSP1 QUP1 */
 233                         compatible = "qcom,spi-qup-v2.2.1";
 234                         reg = <0x78b5000 0x600>;
 235                         interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
 236                         clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>,
 237                                  <&gcc GCC_BLSP1_AHB_CLK>;
 238                         clock-names = "core", "iface";
 239                         #address-cells = <1>;
 240                         #size-cells = <0>;
 241                         dmas = <&blsp_dma 5>, <&blsp_dma 4>;
 242                         dma-names = "rx", "tx";
 243                         status = "disabled";
 244                 };
 245
 246                 blsp1_spi2: spi@78b6000 { /* BLSP1 QUP2 */
 247                         compatible = "qcom,spi-qup-v2.2.1";
 248                         reg = <0x78b6000 0x600>;
 249                         interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
 250                         clocks = <&gcc GCC_BLSP1_QUP2_SPI_APPS_CLK>,
 251                                 <&gcc GCC_BLSP1_AHB_CLK>;
 252                         clock-names = "core", "iface";
 253                         #address-cells = <1>;
 254                         #size-cells = <0>;
 255                         dmas = <&blsp_dma 7>, <&blsp_dma 6>;
 256                         dma-names = "rx", "tx";
 257                         status = "disabled";
 258                 };
 259
 260                 blsp1_i2c3: i2c@78b7000 { /* BLSP1 QUP3 */
 261                         compatible = "qcom,i2c-qup-v2.2.1";
 262                         reg = <0x78b7000 0x600>;
 263                         interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
 264                         clocks = <&gcc GCC_BLSP1_AHB_CLK>,
 265                                  <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>;
 266                         clock-names = "iface", "core";
 267                         #address-cells = <1>;
 268                         #size-cells = <0>;
 269                         dmas = <&blsp_dma 9>, <&blsp_dma 8>;
 270                         dma-names = "rx", "tx";
 271                         status = "disabled";
 272                 };
 273
 274                 blsp1_i2c4: i2c@78b8000 { /* BLSP1 QUP4 */
 275                         compatible = "qcom,i2c-qup-v2.2.1";
 276                         reg = <0x78b8000 0x600>;
 277                         interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
 278                         clocks = <&gcc GCC_BLSP1_AHB_CLK>,
 279                                  <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>;
 280                         clock-names = "iface", "core";
 281                         #address-cells = <1>;
 282                         #size-cells = <0>;
 283                         dmas = <&blsp_dma 11>, <&blsp_dma 10>;
 284                         dma-names = "rx", "tx";
 285                         status = "disabled";
 286                 };
 287
 288                 cryptobam: dma@8e04000 {
 289                         compatible = "qcom,bam-v1.7.0";
 290                         reg = <0x08e04000 0x20000>;
 291                         interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>;
 292                         clocks = <&gcc GCC_CRYPTO_AHB_CLK>;
 293                         clock-names = "bam_clk";
 294                         #dma-cells = <1>;
 295                         qcom,ee = <1>;
 296                         qcom,controlled-remotely;
 297                         status = "disabled";
 298                 };
 299
 300                 crypto@8e3a000 {
 301                         compatible = "qcom,crypto-v5.1";
 302                         reg = <0x08e3a000 0x6000>;
 303                         clocks = <&gcc GCC_CRYPTO_AHB_CLK>,
 304                                  <&gcc GCC_CRYPTO_AXI_CLK>,
 305                                  <&gcc GCC_CRYPTO_CLK>;
 306                         clock-names = "iface", "bus", "core";
 307                         dmas = <&cryptobam 2>, <&cryptobam 3>;
 308                         dma-names = "rx", "tx";
 309                         status = "disabled";
 310                 };
 311
 312                 acc0: clock-controller@b088000 {
 313                         compatible = "qcom,kpss-acc-v2";
 314                         reg = <0x0b088000 0x1000>, <0xb008000 0x1000>;
 315                 };
 316
 317                 acc1: clock-controller@b098000 {
 318                         compatible = "qcom,kpss-acc-v2";
 319                         reg = <0x0b098000 0x1000>, <0xb008000 0x1000>;
 320                 };
 321
 322                 acc2: clock-controller@b0a8000 {
 323                         compatible = "qcom,kpss-acc-v2";
 324                         reg = <0x0b0a8000 0x1000>, <0xb008000 0x1000>;
 325                 };
 326
 327                 acc3: clock-controller@b0b8000 {
 328                         compatible = "qcom,kpss-acc-v2";
 329                         reg = <0x0b0b8000 0x1000>, <0xb008000 0x1000>;
 330                 };
 331
 332                 saw0: regulator@b089000 {
 333                         compatible = "qcom,saw2";
 334                         reg = <0x0b089000 0x1000>, <0x0b009000 0x1000>;
 335                         regulator;
 336                 };
 337
 338                 saw1: regulator@b099000 {
 339                         compatible = "qcom,saw2";
 340                         reg = <0x0b099000 0x1000>, <0x0b009000 0x1000>;
 341                         regulator;
 342                 };
 343
 344                 saw2: regulator@b0a9000 {
 345                         compatible = "qcom,saw2";
 346                         reg = <0x0b0a9000 0x1000>, <0x0b009000 0x1000>;
 347                         regulator;
 348                 };
 349
 350                 saw3: regulator@b0b9000 {
 351                         compatible = "qcom,saw2";
 352                         reg = <0x0b0b9000 0x1000>, <0x0b009000 0x1000>;
 353                         regulator;
 354                 };
 355
 356                 blsp1_uart1: serial@78af000 {
 357                         compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
 358                         reg = <0x78af000 0x200>;
 359                         interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
 360                         status = "disabled";
 361                         clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>,
 362                                 <&gcc GCC_BLSP1_AHB_CLK>;
 363                         clock-names = "core", "iface";
 364                         dmas = <&blsp_dma 1>, <&blsp_dma 0>;
 365                         dma-names = "rx", "tx";
 366                 };
 367
 368                 blsp1_uart2: serial@78b0000 {
 369                         compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
 370                         reg = <0x78b0000 0x200>;
 371                         interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
 372                         status = "disabled";
 373                         clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>,
 374                                 <&gcc GCC_BLSP1_AHB_CLK>;
 375                         clock-names = "core", "iface";
 376                         dmas = <&blsp_dma 3>, <&blsp_dma 2>;
 377                         dma-names = "rx", "tx";
 378                 };
 379
 380                 watchdog@b017000 {
 381                         compatible = "qcom,kpss-wdt", "qcom,kpss-wdt-ipq4019";
 382                         reg = <0xb017000 0x40>;
 383                         clocks = <&sleep_clk>;
 384                         timeout-sec = <10>;
 385                         status = "disabled";
 386                 };
 387
 388                 restart@4ab000 {
 389                         compatible = "qcom,pshold";
 390                         reg = <0x4ab000 0x4>;
 391                 };
 392
 393                 pcie0: pci@40000000 {
 394                         compatible = "qcom,pcie-ipq4019", "snps,dw-pcie";
 395                         reg =  <0x40000000 0xf1d
 396                                 0x40000f20 0xa8
 397                                 0x80000 0x2000
 398                                 0x40100000 0x1000>;
 399                         reg-names = "dbi", "elbi", "parf", "config";
 400                         device_type = "pci";
 401                         linux,pci-domain = <0>;
 402                         bus-range = <0x00 0xff>;
 403                         num-lanes = <1>;
 404                         #address-cells = <3>;
 405                         #size-cells = <2>;
 406
 407                         ranges = <0x81000000 0 0x40200000 0x40200000 0 0x00100000>,
 408                                  <0x82000000 0 0x40300000 0x40300000 0 0x00d00000>;
 409
 410                         interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
 411                         interrupt-names = "msi";
 412                         #interrupt-cells = <1>;
 413                         interrupt-map-mask = <0 0 0 0x7>;
 414                         interrupt-map = <0 0 0 1 &intc 0 142 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
 415                                         <0 0 0 2 &intc 0 143 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
 416                                         <0 0 0 3 &intc 0 144 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
 417                                         <0 0 0 4 &intc 0 145 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
 418                         clocks = <&gcc GCC_PCIE_AHB_CLK>,
 419                                  <&gcc GCC_PCIE_AXI_M_CLK>,
 420                                  <&gcc GCC_PCIE_AXI_S_CLK>;
 421                         clock-names = "aux",
 422                                       "master_bus",
 423                                       "slave_bus";
 424
 425                         resets = <&gcc PCIE_AXI_M_ARES>,
 426                                  <&gcc PCIE_AXI_S_ARES>,
 427                                  <&gcc PCIE_PIPE_ARES>,
 428                                  <&gcc PCIE_AXI_M_VMIDMT_ARES>,
 429                                  <&gcc PCIE_AXI_S_XPU_ARES>,
 430                                  <&gcc PCIE_PARF_XPU_ARES>,
 431                                  <&gcc PCIE_PHY_ARES>,
 432                                  <&gcc PCIE_AXI_M_STICKY_ARES>,
 433                                  <&gcc PCIE_PIPE_STICKY_ARES>,
 434                                  <&gcc PCIE_PWR_ARES>,
 435                                  <&gcc PCIE_AHB_ARES>,
 436                                  <&gcc PCIE_PHY_AHB_ARES>;
 437                         reset-names = "axi_m",
 438                                       "axi_s",
 439                                       "pipe",
 440                                       "axi_m_vmid",
 441                                       "axi_s_xpu",
 442                                       "parf",
 443                                       "phy",
 444                                       "axi_m_sticky",
 445                                       "pipe_sticky",
 446                                       "pwr",
 447                                       "ahb",
 448                                       "phy_ahb";
 449
 450                         status = "disabled";
 451                 };
 452
 453                 qpic_bam: dma@7984000 {
 454                         compatible = "qcom,bam-v1.7.0";
 455                         reg = <0x7984000 0x1a000>;
 456                         interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
 457                         clocks = <&gcc GCC_QPIC_CLK>;
 458                         clock-names = "bam_clk";
 459                         #dma-cells = <1>;
 460                         qcom,ee = <0>;
 461                         status = "disabled";
 462                 };
 463
 464                 nand: qpic-nand@79b0000 {
 465                         compatible = "qcom,ipq4019-nand";
 466                         reg = <0x79b0000 0x1000>;
 467                         #address-cells = <1>;
 468                         #size-cells = <0>;
 469                         clocks = <&gcc GCC_QPIC_CLK>,
 470                                  <&gcc GCC_QPIC_AHB_CLK>;
 471                         clock-names = "core", "aon";
 472
 473                         dmas = <&qpic_bam 0>,
 474                                <&qpic_bam 1>,
 475                                <&qpic_bam 2>;
 476                         dma-names = "tx", "rx", "cmd";
 477                         status = "disabled";
 478
 479                         nand@0 {
 480                                 reg = <0>;
 481
 482                                 nand-ecc-strength = <4>;
 483                                 nand-ecc-step-size = <512>;
 484                                 nand-bus-width = <8>;
 485                         };
 486                 };
 487
 488                 wifi0: wifi@a000000 {
 489                         compatible = "qcom,ipq4019-wifi";
 490                         reg = <0xa000000 0x200000>;
 491                         resets = <&gcc WIFI0_CPU_INIT_RESET>,
 492                                  <&gcc WIFI0_RADIO_SRIF_RESET>,
 493                                  <&gcc WIFI0_RADIO_WARM_RESET>,
 494                                  <&gcc WIFI0_RADIO_COLD_RESET>,
 495                                  <&gcc WIFI0_CORE_WARM_RESET>,
 496                                  <&gcc WIFI0_CORE_COLD_RESET>;
 497                         reset-names = "wifi_cpu_init", "wifi_radio_srif",
 498                                       "wifi_radio_warm", "wifi_radio_cold",
 499                                       "wifi_core_warm", "wifi_core_cold";
 500                         clocks = <&gcc GCC_WCSS2G_CLK>,
 501                                  <&gcc GCC_WCSS2G_REF_CLK>,
 502                                  <&gcc GCC_WCSS2G_RTC_CLK>;
 503                         clock-names = "wifi_wcss_cmd", "wifi_wcss_ref",
 504                                       "wifi_wcss_rtc";
 505                         interrupts = <GIC_SPI 32 IRQ_TYPE_EDGE_RISING>,
 506                                      <GIC_SPI 33 IRQ_TYPE_EDGE_RISING>,
 507                                      <GIC_SPI 34 IRQ_TYPE_EDGE_RISING>,
 508                                      <GIC_SPI 35 IRQ_TYPE_EDGE_RISING>,
 509                                      <GIC_SPI 36 IRQ_TYPE_EDGE_RISING>,
 510                                      <GIC_SPI 37 IRQ_TYPE_EDGE_RISING>,
 511                                      <GIC_SPI 38 IRQ_TYPE_EDGE_RISING>,
 512                                      <GIC_SPI 39 IRQ_TYPE_EDGE_RISING>,
 513                                      <GIC_SPI 40 IRQ_TYPE_EDGE_RISING>,
 514                                      <GIC_SPI 41 IRQ_TYPE_EDGE_RISING>,
 515                                      <GIC_SPI 42 IRQ_TYPE_EDGE_RISING>,
 516                                      <GIC_SPI 43 IRQ_TYPE_EDGE_RISING>,
 517                                      <GIC_SPI 44 IRQ_TYPE_EDGE_RISING>,
 518                                      <GIC_SPI 45 IRQ_TYPE_EDGE_RISING>,
 519                                      <GIC_SPI 46 IRQ_TYPE_EDGE_RISING>,
 520                                      <GIC_SPI 47 IRQ_TYPE_EDGE_RISING>,
 521                                      <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
 522                         interrupt-names =  "msi0",  "msi1",  "msi2",  "msi3",
 523                                            "msi4",  "msi5",  "msi6",  "msi7",
 524                                            "msi8",  "msi9", "msi10", "msi11",
 525                                           "msi12", "msi13", "msi14", "msi15",
 526                                           "legacy";
 527                         status = "disabled";
 528                 };
 529
 530                 wifi1: wifi@a800000 {
 531                         compatible = "qcom,ipq4019-wifi";
 532                         reg = <0xa800000 0x200000>;
 533                         resets = <&gcc WIFI1_CPU_INIT_RESET>,
 534                                  <&gcc WIFI1_RADIO_SRIF_RESET>,
 535                                  <&gcc WIFI1_RADIO_WARM_RESET>,
 536                                  <&gcc WIFI1_RADIO_COLD_RESET>,
 537                                  <&gcc WIFI1_CORE_WARM_RESET>,
 538                                  <&gcc WIFI1_CORE_COLD_RESET>;
 539                         reset-names = "wifi_cpu_init", "wifi_radio_srif",
 540                                       "wifi_radio_warm", "wifi_radio_cold",
 541                                       "wifi_core_warm", "wifi_core_cold";
 542                         clocks = <&gcc GCC_WCSS5G_CLK>,
 543                                  <&gcc GCC_WCSS5G_REF_CLK>,
 544                                  <&gcc GCC_WCSS5G_RTC_CLK>;
 545                         clock-names = "wifi_wcss_cmd", "wifi_wcss_ref",
 546                                       "wifi_wcss_rtc";
 547                         interrupts = <GIC_SPI 48 IRQ_TYPE_EDGE_RISING>,
 548                                      <GIC_SPI 49 IRQ_TYPE_EDGE_RISING>,
 549                                      <GIC_SPI 50 IRQ_TYPE_EDGE_RISING>,
 550                                      <GIC_SPI 51 IRQ_TYPE_EDGE_RISING>,
 551                                      <GIC_SPI 52 IRQ_TYPE_EDGE_RISING>,
 552                                      <GIC_SPI 53 IRQ_TYPE_EDGE_RISING>,
 553                                      <GIC_SPI 54 IRQ_TYPE_EDGE_RISING>,
 554                                      <GIC_SPI 55 IRQ_TYPE_EDGE_RISING>,
 555                                      <GIC_SPI 56 IRQ_TYPE_EDGE_RISING>,
 556                                      <GIC_SPI 57 IRQ_TYPE_EDGE_RISING>,
 557                                      <GIC_SPI 58 IRQ_TYPE_EDGE_RISING>,
 558                                      <GIC_SPI 59 IRQ_TYPE_EDGE_RISING>,
 559                                      <GIC_SPI 60 IRQ_TYPE_EDGE_RISING>,
 560                                      <GIC_SPI 61 IRQ_TYPE_EDGE_RISING>,
 561                                      <GIC_SPI 62 IRQ_TYPE_EDGE_RISING>,
 562                                      <GIC_SPI 63 IRQ_TYPE_EDGE_RISING>,
 563                                      <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
 564                         interrupt-names =  "msi0",  "msi1",  "msi2",  "msi3",
 565                                            "msi4",  "msi5",  "msi6",  "msi7",
 566                                            "msi8",  "msi9", "msi10", "msi11",
 567                                           "msi12", "msi13", "msi14", "msi15",
 568                                           "legacy";
 569                         status = "disabled";
 570                 };
 571         };
 572 };