1 // SPDX-License-Identifier: GPL-2.0
4 #include "skeleton.dtsi"
5 #include <dt-bindings/interrupt-controller/arm-gic.h>
6 #include <dt-bindings/clock/qcom,gcc-ipq806x.h>
7 #include <dt-bindings/clock/qcom,lcc-ipq806x.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/reset/qcom,gcc-ipq806x.h>
10 #include <dt-bindings/soc/qcom,gsbi.h>
11 #include <dt-bindings/interrupt-controller/arm-gic.h>
14 model = "Qualcomm IPQ8064";
15 compatible = "qcom,ipq8064";
16 interrupt-parent = <&intc>;
23 compatible = "qcom,krait";
24 enable-method = "qcom,kpss-acc-v1";
27 next-level-cache = <&L2>;
33 compatible = "qcom,krait";
34 enable-method = "qcom,kpss-acc-v1";
37 next-level-cache = <&L2>;
49 compatible = "qcom,krait-pmu";
50 interrupts = <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) |
51 IRQ_TYPE_LEVEL_HIGH)>;
60 reg = <0x40000000 0x1000000>;
65 reg = <0x41000000 0x200000>;
72 compatible = "fixed-clock";
74 clock-frequency = <25000000>;
78 compatible = "fixed-clock";
80 clock-frequency = <25000000>;
83 sleep_clk: sleep_clk {
84 compatible = "fixed-clock";
85 clock-frequency = <32768>;
94 compatible = "simple-bus";
97 compatible = "qcom,lpass-cpu";
99 clocks = <&lcc AHBIX_CLK>,
102 clock-names = "ahbix-clk",
105 interrupts = <GIC_SPI 85 IRQ_TYPE_EDGE_RISING>;
106 interrupt-names = "lpass-irq-lpaif";
107 reg = <0x28100000 0x10000>;
108 reg-names = "lpass-lpaif";
111 qcom_pinmux: pinmux@800000 {
112 compatible = "qcom,ipq8064-pinctrl";
113 reg = <0x800000 0x4000>;
117 interrupt-controller;
118 #interrupt-cells = <2>;
119 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
121 pcie0_pins: pcie0_pinmux {
124 function = "pcie1_rst";
125 drive-strength = <12>;
130 pcie1_pins: pcie1_pinmux {
133 function = "pcie2_rst";
134 drive-strength = <12>;
139 pcie2_pins: pcie2_pinmux {
142 function = "pcie3_rst";
143 drive-strength = <12>;
150 pins = "gpio18", "gpio19", "gpio21";
152 drive-strength = <10>;
157 leds_pins: leds_pins {
159 pins = "gpio7", "gpio8", "gpio9",
162 drive-strength = <2>;
168 buttons_pins: buttons_pins {
171 drive-strength = <2>;
177 intc: interrupt-controller@2000000 {
178 compatible = "qcom,msm-qgic2";
179 interrupt-controller;
180 #interrupt-cells = <3>;
181 reg = <0x02000000 0x1000>,
186 compatible = "qcom,kpss-timer",
187 "qcom,kpss-wdt-ipq8064", "qcom,msm-timer";
188 interrupts = <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(2) |
189 IRQ_TYPE_EDGE_RISING)>,
190 <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(2) |
191 IRQ_TYPE_EDGE_RISING)>,
192 <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(2) |
193 IRQ_TYPE_EDGE_RISING)>,
194 <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(2) |
195 IRQ_TYPE_EDGE_RISING)>,
196 <GIC_PPI 5 (GIC_CPU_MASK_SIMPLE(2) |
197 IRQ_TYPE_EDGE_RISING)>;
198 reg = <0x0200a000 0x100>;
199 clock-frequency = <25000000>,
201 clocks = <&sleep_clk>;
202 clock-names = "sleep";
203 cpu-offset = <0x80000>;
206 acc0: clock-controller@2088000 {
207 compatible = "qcom,kpss-acc-v1";
208 reg = <0x02088000 0x1000>, <0x02008000 0x1000>;
211 acc1: clock-controller@2098000 {
212 compatible = "qcom,kpss-acc-v1";
213 reg = <0x02098000 0x1000>, <0x02008000 0x1000>;
216 saw0: regulator@2089000 {
217 compatible = "qcom,saw2";
218 reg = <0x02089000 0x1000>, <0x02009000 0x1000>;
222 saw1: regulator@2099000 {
223 compatible = "qcom,saw2";
224 reg = <0x02099000 0x1000>, <0x02009000 0x1000>;
228 gsbi2: gsbi@12480000 {
229 compatible = "qcom,gsbi-v1.0.0";
231 reg = <0x12480000 0x100>;
232 clocks = <&gcc GSBI2_H_CLK>;
233 clock-names = "iface";
234 #address-cells = <1>;
239 syscon-tcsr = <&tcsr>;
242 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
243 reg = <0x12490000 0x1000>,
245 interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>;
246 clocks = <&gcc GSBI2_UART_CLK>, <&gcc GSBI2_H_CLK>;
247 clock-names = "core", "iface";
252 compatible = "qcom,i2c-qup-v1.1.1";
253 reg = <0x124a0000 0x1000>;
254 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>;
256 clocks = <&gcc GSBI2_QUP_CLK>, <&gcc GSBI2_H_CLK>;
257 clock-names = "core", "iface";
260 #address-cells = <1>;
266 gsbi4: gsbi@16300000 {
267 compatible = "qcom,gsbi-v1.0.0";
269 reg = <0x16300000 0x100>;
270 clocks = <&gcc GSBI4_H_CLK>;
271 clock-names = "iface";
272 #address-cells = <1>;
277 syscon-tcsr = <&tcsr>;
279 gsbi4_serial: serial@16340000 {
280 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
281 reg = <0x16340000 0x1000>,
283 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
284 clocks = <&gcc GSBI4_UART_CLK>, <&gcc GSBI4_H_CLK>;
285 clock-names = "core", "iface";
290 compatible = "qcom,i2c-qup-v1.1.1";
291 reg = <0x16380000 0x1000>;
292 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
294 clocks = <&gcc GSBI4_QUP_CLK>, <&gcc GSBI4_H_CLK>;
295 clock-names = "core", "iface";
298 #address-cells = <1>;
303 gsbi5: gsbi@1a200000 {
304 compatible = "qcom,gsbi-v1.0.0";
306 reg = <0x1a200000 0x100>;
307 clocks = <&gcc GSBI5_H_CLK>;
308 clock-names = "iface";
309 #address-cells = <1>;
314 syscon-tcsr = <&tcsr>;
317 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
318 reg = <0x1a240000 0x1000>,
320 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
321 clocks = <&gcc GSBI5_UART_CLK>, <&gcc GSBI5_H_CLK>;
322 clock-names = "core", "iface";
327 compatible = "qcom,i2c-qup-v1.1.1";
328 reg = <0x1a280000 0x1000>;
329 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
331 clocks = <&gcc GSBI5_QUP_CLK>, <&gcc GSBI5_H_CLK>;
332 clock-names = "core", "iface";
335 #address-cells = <1>;
340 compatible = "qcom,spi-qup-v1.1.1";
341 reg = <0x1a280000 0x1000>;
342 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
344 clocks = <&gcc GSBI5_QUP_CLK>, <&gcc GSBI5_H_CLK>;
345 clock-names = "core", "iface";
348 #address-cells = <1>;
353 gsbi7: gsbi@16600000 {
355 compatible = "qcom,gsbi-v1.0.0";
357 reg = <0x16600000 0x100>;
358 clocks = <&gcc GSBI7_H_CLK>;
359 clock-names = "iface";
360 #address-cells = <1>;
363 syscon-tcsr = <&tcsr>;
365 gsbi7_serial: serial@16640000 {
366 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
367 reg = <0x16640000 0x1000>,
369 interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
370 clocks = <&gcc GSBI7_UART_CLK>, <&gcc GSBI7_H_CLK>;
371 clock-names = "core", "iface";
376 sata_phy: sata-phy@1b400000 {
377 compatible = "qcom,ipq806x-sata-phy";
378 reg = <0x1b400000 0x200>;
380 clocks = <&gcc SATA_PHY_CFG_CLK>;
388 compatible = "qcom,ipq806x-ahci", "generic-ahci";
389 reg = <0x29000000 0x180>;
391 interrupts = <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>;
393 clocks = <&gcc SFAB_SATA_S_H_CLK>,
396 <&gcc SATA_RXOOB_CLK>,
397 <&gcc SATA_PMALIVE_CLK>;
398 clock-names = "slave_face", "iface", "core",
401 assigned-clocks = <&gcc SATA_RXOOB_CLK>, <&gcc SATA_PMALIVE_CLK>;
402 assigned-clock-rates = <100000000>, <100000000>;
405 phy-names = "sata-phy";
410 compatible = "qcom,ssbi";
411 reg = <0x00500000 0x1000>;
412 qcom,controller-type = "pmic-arbiter";
415 gcc: clock-controller@900000 {
416 compatible = "qcom,gcc-ipq8064";
417 reg = <0x00900000 0x4000>;
422 tcsr: syscon@1a400000 {
423 compatible = "qcom,tcsr-ipq8064", "syscon";
424 reg = <0x1a400000 0x100>;
427 lcc: clock-controller@28000000 {
428 compatible = "qcom,lcc-ipq8064";
429 reg = <0x28000000 0x1000>;
434 pcie0: pci@1b500000 {
435 compatible = "qcom,pcie-ipq8064";
436 reg = <0x1b500000 0x1000
439 0x0ff00000 0x100000>;
440 reg-names = "dbi", "elbi", "parf", "config";
442 linux,pci-domain = <0>;
443 bus-range = <0x00 0xff>;
445 #address-cells = <3>;
448 ranges = <0x81000000 0 0x0fe00000 0x0fe00000 0 0x00100000 /* downstream I/O */
449 0x82000000 0 0x08000000 0x08000000 0 0x07e00000>; /* non-prefetchable memory */
451 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
452 interrupt-names = "msi";
453 #interrupt-cells = <1>;
454 interrupt-map-mask = <0 0 0 0x7>;
455 interrupt-map = <0 0 0 1 &intc 0 36 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
456 <0 0 0 2 &intc 0 37 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
457 <0 0 0 3 &intc 0 38 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
458 <0 0 0 4 &intc 0 39 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
460 clocks = <&gcc PCIE_A_CLK>,
464 <&gcc PCIE_ALT_REF_CLK>;
465 clock-names = "core", "iface", "phy", "aux", "ref";
467 assigned-clocks = <&gcc PCIE_ALT_REF_CLK>;
468 assigned-clock-rates = <100000000>;
470 resets = <&gcc PCIE_ACLK_RESET>,
471 <&gcc PCIE_HCLK_RESET>,
472 <&gcc PCIE_POR_RESET>,
473 <&gcc PCIE_PCI_RESET>,
474 <&gcc PCIE_PHY_RESET>,
475 <&gcc PCIE_EXT_RESET>;
476 reset-names = "axi", "ahb", "por", "pci", "phy", "ext";
478 pinctrl-0 = <&pcie0_pins>;
479 pinctrl-names = "default";
482 perst-gpio = <&qcom_pinmux 3 GPIO_ACTIVE_LOW>;
485 pcie1: pci@1b700000 {
486 compatible = "qcom,pcie-ipq8064";
487 reg = <0x1b700000 0x1000
490 0x31f00000 0x100000>;
491 reg-names = "dbi", "elbi", "parf", "config";
493 linux,pci-domain = <1>;
494 bus-range = <0x00 0xff>;
496 #address-cells = <3>;
499 ranges = <0x81000000 0 0x31e00000 0x31e00000 0 0x00100000 /* downstream I/O */
500 0x82000000 0 0x2e000000 0x2e000000 0 0x03e00000>; /* non-prefetchable memory */
502 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
503 interrupt-names = "msi";
504 #interrupt-cells = <1>;
505 interrupt-map-mask = <0 0 0 0x7>;
506 interrupt-map = <0 0 0 1 &intc 0 58 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
507 <0 0 0 2 &intc 0 59 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
508 <0 0 0 3 &intc 0 60 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
509 <0 0 0 4 &intc 0 61 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
511 clocks = <&gcc PCIE_1_A_CLK>,
513 <&gcc PCIE_1_PHY_CLK>,
514 <&gcc PCIE_1_AUX_CLK>,
515 <&gcc PCIE_1_ALT_REF_CLK>;
516 clock-names = "core", "iface", "phy", "aux", "ref";
518 assigned-clocks = <&gcc PCIE_1_ALT_REF_CLK>;
519 assigned-clock-rates = <100000000>;
521 resets = <&gcc PCIE_1_ACLK_RESET>,
522 <&gcc PCIE_1_HCLK_RESET>,
523 <&gcc PCIE_1_POR_RESET>,
524 <&gcc PCIE_1_PCI_RESET>,
525 <&gcc PCIE_1_PHY_RESET>,
526 <&gcc PCIE_1_EXT_RESET>;
527 reset-names = "axi", "ahb", "por", "pci", "phy", "ext";
529 pinctrl-0 = <&pcie1_pins>;
530 pinctrl-names = "default";
533 perst-gpio = <&qcom_pinmux 48 GPIO_ACTIVE_LOW>;
536 pcie2: pci@1b900000 {
537 compatible = "qcom,pcie-ipq8064";
538 reg = <0x1b900000 0x1000
541 0x35f00000 0x100000>;
542 reg-names = "dbi", "elbi", "parf", "config";
544 linux,pci-domain = <2>;
545 bus-range = <0x00 0xff>;
547 #address-cells = <3>;
550 ranges = <0x81000000 0 0x35e00000 0x35e00000 0 0x00100000 /* downstream I/O */
551 0x82000000 0 0x32000000 0x32000000 0 0x03e00000>; /* non-prefetchable memory */
553 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
554 interrupt-names = "msi";
555 #interrupt-cells = <1>;
556 interrupt-map-mask = <0 0 0 0x7>;
557 interrupt-map = <0 0 0 1 &intc 0 72 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
558 <0 0 0 2 &intc 0 73 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
559 <0 0 0 3 &intc 0 74 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
560 <0 0 0 4 &intc 0 75 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
562 clocks = <&gcc PCIE_2_A_CLK>,
564 <&gcc PCIE_2_PHY_CLK>,
565 <&gcc PCIE_2_AUX_CLK>,
566 <&gcc PCIE_2_ALT_REF_CLK>;
567 clock-names = "core", "iface", "phy", "aux", "ref";
569 assigned-clocks = <&gcc PCIE_2_ALT_REF_CLK>;
570 assigned-clock-rates = <100000000>;
572 resets = <&gcc PCIE_2_ACLK_RESET>,
573 <&gcc PCIE_2_HCLK_RESET>,
574 <&gcc PCIE_2_POR_RESET>,
575 <&gcc PCIE_2_PCI_RESET>,
576 <&gcc PCIE_2_PHY_RESET>,
577 <&gcc PCIE_2_EXT_RESET>;
578 reset-names = "axi", "ahb", "por", "pci", "phy", "ext";
580 pinctrl-0 = <&pcie2_pins>;
581 pinctrl-names = "default";
584 perst-gpio = <&qcom_pinmux 63 GPIO_ACTIVE_LOW>;
587 vsdcc_fixed: vsdcc-regulator {
588 compatible = "regulator-fixed";
589 regulator-name = "SDCC Power";
590 regulator-min-microvolt = <3300000>;
591 regulator-max-microvolt = <3300000>;
595 sdcc1bam:dma@12402000 {
596 compatible = "qcom,bam-v1.3.0";
597 reg = <0x12402000 0x8000>;
598 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
599 clocks = <&gcc SDC1_H_CLK>;
600 clock-names = "bam_clk";
605 sdcc3bam:dma@12182000 {
606 compatible = "qcom,bam-v1.3.0";
607 reg = <0x12182000 0x8000>;
608 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
609 clocks = <&gcc SDC3_H_CLK>;
610 clock-names = "bam_clk";
616 compatible = "simple-bus";
617 #address-cells = <1>;
623 compatible = "arm,pl18x", "arm,primecell";
624 arm,primecell-periphid = <0x00051180>;
625 reg = <0x12400000 0x2000>;
626 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
627 interrupt-names = "cmd_irq";
628 clocks = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>;
629 clock-names = "mclk", "apb_pclk";
631 max-frequency = <96000000>;
636 vmmc-supply = <&vsdcc_fixed>;
637 dmas = <&sdcc1bam 2>, <&sdcc1bam 1>;
638 dma-names = "tx", "rx";
642 compatible = "arm,pl18x", "arm,primecell";
643 arm,primecell-periphid = <0x00051180>;
645 reg = <0x12180000 0x2000>;
646 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
647 interrupt-names = "cmd_irq";
648 clocks = <&gcc SDC3_CLK>, <&gcc SDC3_H_CLK>;
649 clock-names = "mclk", "apb_pclk";
653 max-frequency = <192000000>;
657 vqmmc-supply = <&vsdcc_fixed>;
658 dmas = <&sdcc3bam 2>, <&sdcc3bam 1>;
659 dma-names = "tx", "rx";