3 #include <dt-bindings/interrupt-controller/irq.h>
4 #include <dt-bindings/clock/qcom,gcc-msm8974.h>
5 #include "skeleton.dtsi"
8 model = "Qualcomm MSM8974";
9 compatible = "qcom,msm8974";
10 interrupt-parent = <&intc>;
18 reg = <0x08000000 0x5100000>;
23 reg = <0x0d100000 0x100000>;
28 reg = <0x0d200000 0xa00000>;
33 reg = <0x0dc00000 0x1900000>;
38 reg = <0x0f500000 0x500000>;
42 smem_region: smem@fa00000 {
43 reg = <0xfa00000 0x200000>;
48 reg = <0x0fc00000 0x160000>;
53 reg = <0x0fd60000 0x20000>;
58 reg = <0x0fd80000 0x180000>;
63 reg = <0x0ff00000 0x10100000>;
71 interrupts = <1 9 0xf04>;
74 compatible = "qcom,krait";
75 enable-method = "qcom,kpss-acc-v2";
78 next-level-cache = <&L2>;
81 cpu-idle-states = <&CPU_SPC>;
85 compatible = "qcom,krait";
86 enable-method = "qcom,kpss-acc-v2";
89 next-level-cache = <&L2>;
92 cpu-idle-states = <&CPU_SPC>;
96 compatible = "qcom,krait";
97 enable-method = "qcom,kpss-acc-v2";
100 next-level-cache = <&L2>;
103 cpu-idle-states = <&CPU_SPC>;
107 compatible = "qcom,krait";
108 enable-method = "qcom,kpss-acc-v2";
111 next-level-cache = <&L2>;
114 cpu-idle-states = <&CPU_SPC>;
118 compatible = "cache";
120 qcom,saw = <&saw_l2>;
125 compatible = "qcom,idle-state-spc",
127 entry-latency-us = <150>;
128 exit-latency-us = <200>;
129 min-residency-us = <2000>;
135 compatible = "qcom,krait-pmu";
136 interrupts = <1 7 0xf04>;
141 compatible = "fixed-clock";
143 clock-frequency = <19200000>;
147 compatible = "fixed-clock";
149 clock-frequency = <32768>;
154 compatible = "arm,armv7-timer";
155 interrupts = <1 2 0xf08>,
159 clock-frequency = <19200000>;
163 compatible = "qcom,smem";
165 memory-region = <&smem_region>;
166 qcom,rpm-msg-ram = <&rpm_msg_ram>;
168 hwlocks = <&tcsr_mutex 3>;
172 compatible = "qcom,smp2p";
173 qcom,smem = <435>, <428>;
175 interrupt-parent = <&intc>;
176 interrupts = <0 27 IRQ_TYPE_EDGE_RISING>;
178 qcom,ipc = <&apcs 8 14>;
180 qcom,local-pid = <0>;
181 qcom,remote-pid = <1>;
183 modem_smp2p_out: master-kernel {
184 qcom,entry-name = "master-kernel";
185 #qcom,state-cells = <1>;
188 modem_smp2p_in: slave-kernel {
189 qcom,entry-name = "slave-kernel";
191 interrupt-controller;
192 #interrupt-cells = <2>;
197 compatible = "qcom,smp2p";
198 qcom,smem = <451>, <431>;
200 interrupt-parent = <&intc>;
201 interrupts = <0 143 IRQ_TYPE_EDGE_RISING>;
203 qcom,ipc = <&apcs 8 18>;
205 qcom,local-pid = <0>;
206 qcom,remote-pid = <4>;
208 wcnss_smp2p_out: master-kernel {
209 qcom,entry-name = "master-kernel";
211 #qcom,state-cells = <1>;
214 wcnss_smp2p_in: slave-kernel {
215 qcom,entry-name = "slave-kernel";
217 interrupt-controller;
218 #interrupt-cells = <2>;
223 compatible = "qcom,smsm";
225 #address-cells = <1>;
228 qcom,ipc-1 = <&apcs 8 13>;
229 qcom,ipc-2 = <&apcs 8 9>;
230 qcom,ipc-3 = <&apcs 8 19>;
235 #qcom,state-cells = <1>;
238 modem_smsm: modem@1 {
240 interrupts = <0 26 IRQ_TYPE_EDGE_RISING>;
242 interrupt-controller;
243 #interrupt-cells = <2>;
248 interrupts = <0 157 IRQ_TYPE_EDGE_RISING>;
250 interrupt-controller;
251 #interrupt-cells = <2>;
254 wcnss_smsm: wcnss@7 {
256 interrupts = <0 144 IRQ_TYPE_EDGE_RISING>;
258 interrupt-controller;
259 #interrupt-cells = <2>;
264 #address-cells = <1>;
267 compatible = "simple-bus";
269 intc: interrupt-controller@f9000000 {
270 compatible = "qcom,msm-qgic2";
271 interrupt-controller;
272 #interrupt-cells = <3>;
273 reg = <0xf9000000 0x1000>,
277 apcs: syscon@f9011000 {
278 compatible = "syscon";
279 reg = <0xf9011000 0x1000>;
283 #address-cells = <1>;
286 compatible = "arm,armv7-timer-mem";
287 reg = <0xf9020000 0x1000>;
288 clock-frequency = <19200000>;
292 interrupts = <0 8 0x4>,
294 reg = <0xf9021000 0x1000>,
300 interrupts = <0 9 0x4>;
301 reg = <0xf9023000 0x1000>;
307 interrupts = <0 10 0x4>;
308 reg = <0xf9024000 0x1000>;
314 interrupts = <0 11 0x4>;
315 reg = <0xf9025000 0x1000>;
321 interrupts = <0 12 0x4>;
322 reg = <0xf9026000 0x1000>;
328 interrupts = <0 13 0x4>;
329 reg = <0xf9027000 0x1000>;
335 interrupts = <0 14 0x4>;
336 reg = <0xf9028000 0x1000>;
341 saw0: power-controller@f9089000 {
342 compatible = "qcom,msm8974-saw2-v2.1-cpu", "qcom,saw2";
343 reg = <0xf9089000 0x1000>, <0xf9009000 0x1000>;
346 saw1: power-controller@f9099000 {
347 compatible = "qcom,msm8974-saw2-v2.1-cpu", "qcom,saw2";
348 reg = <0xf9099000 0x1000>, <0xf9009000 0x1000>;
351 saw2: power-controller@f90a9000 {
352 compatible = "qcom,msm8974-saw2-v2.1-cpu", "qcom,saw2";
353 reg = <0xf90a9000 0x1000>, <0xf9009000 0x1000>;
356 saw3: power-controller@f90b9000 {
357 compatible = "qcom,msm8974-saw2-v2.1-cpu", "qcom,saw2";
358 reg = <0xf90b9000 0x1000>, <0xf9009000 0x1000>;
361 saw_l2: power-controller@f9012000 {
362 compatible = "qcom,saw2";
363 reg = <0xf9012000 0x1000>;
367 acc0: clock-controller@f9088000 {
368 compatible = "qcom,kpss-acc-v2";
369 reg = <0xf9088000 0x1000>, <0xf9008000 0x1000>;
372 acc1: clock-controller@f9098000 {
373 compatible = "qcom,kpss-acc-v2";
374 reg = <0xf9098000 0x1000>, <0xf9008000 0x1000>;
377 acc2: clock-controller@f90a8000 {
378 compatible = "qcom,kpss-acc-v2";
379 reg = <0xf90a8000 0x1000>, <0xf9008000 0x1000>;
382 acc3: clock-controller@f90b8000 {
383 compatible = "qcom,kpss-acc-v2";
384 reg = <0xf90b8000 0x1000>, <0xf9008000 0x1000>;
388 compatible = "qcom,pshold";
389 reg = <0xfc4ab000 0x4>;
392 gcc: clock-controller@fc400000 {
393 compatible = "qcom,gcc-msm8974";
396 #power-domain-cells = <1>;
397 reg = <0xfc400000 0x4000>;
400 tcsr_mutex_block: syscon@fd484000 {
401 compatible = "syscon";
402 reg = <0xfd484000 0x2000>;
405 mmcc: clock-controller@fd8c0000 {
406 compatible = "qcom,mmcc-msm8974";
409 #power-domain-cells = <1>;
410 reg = <0xfd8c0000 0x6000>;
413 tcsr_mutex: tcsr-mutex {
414 compatible = "qcom,tcsr-mutex";
415 syscon = <&tcsr_mutex_block 0 0x80>;
420 rpm_msg_ram: memory@fc428000 {
421 compatible = "qcom,rpm-msg-ram";
422 reg = <0xfc428000 0x4000>;
425 blsp1_uart2: serial@f991e000 {
426 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
427 reg = <0xf991e000 0x1000>;
428 interrupts = <0 108 0x0>;
429 clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
430 clock-names = "core", "iface";
435 compatible = "qcom,sdhci-msm-v4";
436 reg = <0xf9824900 0x11c>, <0xf9824000 0x800>;
437 reg-names = "hc_mem", "core_mem";
438 interrupts = <0 123 0>, <0 138 0>;
439 interrupt-names = "hc_irq", "pwr_irq";
440 clocks = <&gcc GCC_SDCC1_APPS_CLK>, <&gcc GCC_SDCC1_AHB_CLK>;
441 clock-names = "core", "iface";
446 compatible = "qcom,sdhci-msm-v4";
447 reg = <0xf98a4900 0x11c>, <0xf98a4000 0x800>;
448 reg-names = "hc_mem", "core_mem";
449 interrupts = <0 125 0>, <0 221 0>;
450 interrupt-names = "hc_irq", "pwr_irq";
451 clocks = <&gcc GCC_SDCC2_APPS_CLK>, <&gcc GCC_SDCC2_AHB_CLK>;
452 clock-names = "core", "iface";
457 compatible = "qcom,prng";
458 reg = <0xf9bff000 0x200>;
459 clocks = <&gcc GCC_PRNG_AHB_CLK>;
460 clock-names = "core";
463 msmgpio: pinctrl@fd510000 {
464 compatible = "qcom,msm8974-pinctrl";
465 reg = <0xfd510000 0x4000>;
468 interrupt-controller;
469 #interrupt-cells = <2>;
470 interrupts = <0 208 0>;
475 compatible = "qcom,i2c-qup-v2.1.1";
476 reg = <0xf9924000 0x1000>;
477 interrupts = <0 96 IRQ_TYPE_NONE>;
478 clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
479 clock-names = "core", "iface";
480 #address-cells = <1>;
484 blsp_i2c8: i2c@f9964000 {
486 compatible = "qcom,i2c-qup-v2.1.1";
487 reg = <0xf9964000 0x1000>;
488 interrupts = <0 102 IRQ_TYPE_NONE>;
489 clocks = <&gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>;
490 clock-names = "core", "iface";
491 #address-cells = <1>;
495 blsp_i2c11: i2c@f9967000 {
497 compatible = "qcom,i2c-qup-v2.1.1";
498 reg = <0xf9967000 0x1000>;
499 interrupts = <0 105 IRQ_TYPE_NONE>;
500 clocks = <&gcc GCC_BLSP2_QUP5_I2C_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>;
501 clock-names = "core", "iface";
502 #address-cells = <1>;
506 spmi_bus: spmi@fc4cf000 {
507 compatible = "qcom,spmi-pmic-arb";
508 reg-names = "core", "intr", "cnfg";
509 reg = <0xfc4cf000 0x1000>,
512 interrupt-names = "periph_irq";
513 interrupts = <0 190 0>;
516 #address-cells = <2>;
518 interrupt-controller;
519 #interrupt-cells = <4>;
524 compatible = "qcom,smd";
527 interrupts = <0 25 IRQ_TYPE_EDGE_RISING>;
529 qcom,ipc = <&apcs 8 12>;
534 interrupts = <0 168 1>;
535 qcom,ipc = <&apcs 8 0>;
536 qcom,smd-edge = <15>;
539 compatible = "qcom,rpm-msm8974";
540 qcom,smd-channels = "rpm_requests";
543 compatible = "qcom,rpm-pm8841-regulators";
556 compatible = "qcom,rpm-pm8941-regulators";
588 pm8941_lvs1: lvs1 {};
589 pm8941_lvs2: lvs2 {};
590 pm8941_lvs3: lvs3 {};
592 pm8941_5vs1: 5vs1 {};
593 pm8941_5vs2: 5vs2 {};