2 * Device Tree Source for the r8a7740 SoC
4 * Copyright (C) 2012 Renesas Solutions Corp.
6 * This file is licensed under the terms of the GNU General Public License
7 * version 2. This program is licensed "as is" without any warranty of any
8 * kind, whether express or implied.
11 #include <dt-bindings/clock/r8a7740-clock.h>
12 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #include <dt-bindings/interrupt-controller/irq.h>
16 compatible = "renesas,r8a7740";
17 interrupt-parent = <&gic>;
25 compatible = "arm,cortex-a9";
28 clock-frequency = <800000000>;
29 power-domains = <&pd_a3sm>;
30 next-level-cache = <&L2>;
34 gic: interrupt-controller@c2800000 {
35 compatible = "arm,pl390";
36 #interrupt-cells = <3>;
38 reg = <0xc2800000 0x1000>,
42 L2: cache-controller@f0100000 {
43 compatible = "arm,pl310-cache";
44 reg = <0xf0100000 0x1000>;
45 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
46 power-domains = <&pd_a3sm>;
47 arm,data-latency = <3 3 3>;
48 arm,tag-latency = <2 2 2>;
54 dbsc3: memory-controller@fe400000 {
55 compatible = "renesas,dbsc3-r8a7740";
56 reg = <0xfe400000 0x400>;
57 power-domains = <&pd_a4s>;
61 compatible = "arm,cortex-a9-pmu";
62 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
66 compatible = "arm,coresight-etm3x";
67 power-domains = <&pd_d4>;
71 reg = <0xfe910000 0x3000>;
72 compatible = "renesas,r8a7740-ceu";
73 interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>;
74 clocks = <&mstp1_clks R8A7740_CLK_CEU20>;
75 power-domains = <&pd_a4r>;
80 reg = <0xfe914000 0x3000>;
81 compatible = "renesas,r8a7740-ceu";
82 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
83 clocks = <&mstp1_clks R8A7740_CLK_CEU21>;
84 power-domains = <&pd_a4r>;
88 cmt1: timer@e6138000 {
89 compatible = "renesas,cmt-48-r8a7740", "renesas,cmt-48";
90 reg = <0xe6138000 0x170>;
91 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
92 clocks = <&mstp3_clks R8A7740_CLK_CMT1>;
94 power-domains = <&pd_c5>;
98 /* irqpin0: IRQ0 - IRQ7 */
99 irqpin0: interrupt-controller@e6900000 {
100 compatible = "renesas,intc-irqpin-r8a7740", "renesas,intc-irqpin";
101 #interrupt-cells = <2>;
102 interrupt-controller;
103 reg = <0xe6900000 4>,
108 interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH
109 GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH
110 GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH
111 GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH
112 GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH
113 GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH
114 GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH
115 GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
116 clocks = <&mstp2_clks R8A7740_CLK_INTCA>;
117 power-domains = <&pd_a4s>;
120 /* irqpin1: IRQ8 - IRQ15 */
121 irqpin1: interrupt-controller@e6900004 {
122 compatible = "renesas,intc-irqpin-r8a7740", "renesas,intc-irqpin";
123 #interrupt-cells = <2>;
124 interrupt-controller;
125 reg = <0xe6900004 4>,
130 interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH
131 GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH
132 GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH
133 GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH
134 GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH
135 GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH
136 GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH
137 GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
138 clocks = <&mstp2_clks R8A7740_CLK_INTCA>;
139 power-domains = <&pd_a4s>;
142 /* irqpin2: IRQ16 - IRQ23 */
143 irqpin2: interrupt-controller@e6900008 {
144 compatible = "renesas,intc-irqpin-r8a7740", "renesas,intc-irqpin";
145 #interrupt-cells = <2>;
146 interrupt-controller;
147 reg = <0xe6900008 4>,
152 interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH
153 GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH
154 GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH
155 GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH
156 GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH
157 GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH
158 GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH
159 GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
160 clocks = <&mstp2_clks R8A7740_CLK_INTCA>;
161 power-domains = <&pd_a4s>;
164 /* irqpin3: IRQ24 - IRQ31 */
165 irqpin3: interrupt-controller@e690000c {
166 compatible = "renesas,intc-irqpin-r8a7740", "renesas,intc-irqpin";
167 #interrupt-cells = <2>;
168 interrupt-controller;
169 reg = <0xe690000c 4>,
174 interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH
175 GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH
176 GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH
177 GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH
178 GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH
179 GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH
180 GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH
181 GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
182 clocks = <&mstp2_clks R8A7740_CLK_INTCA>;
183 power-domains = <&pd_a4s>;
186 ether: ethernet@e9a00000 {
187 compatible = "renesas,gether-r8a7740";
188 reg = <0xe9a00000 0x800>,
190 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
191 clocks = <&mstp3_clks R8A7740_CLK_GETHER>;
192 power-domains = <&pd_a4s>;
194 #address-cells = <1>;
200 #address-cells = <1>;
202 compatible = "renesas,iic-r8a7740", "renesas,rmobile-iic";
203 reg = <0xfff20000 0x425>;
204 interrupts = <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH
205 GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH
206 GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH
207 GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>;
208 clocks = <&mstp1_clks R8A7740_CLK_IIC0>;
209 power-domains = <&pd_a4r>;
214 #address-cells = <1>;
216 compatible = "renesas,iic-r8a7740", "renesas,rmobile-iic";
217 reg = <0xe6c20000 0x425>;
218 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH
219 GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH
220 GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH
221 GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
222 clocks = <&mstp3_clks R8A7740_CLK_IIC1>;
223 power-domains = <&pd_a3sp>;
227 scifa0: serial@e6c40000 {
228 compatible = "renesas,scifa-r8a7740", "renesas,scifa";
229 reg = <0xe6c40000 0x100>;
230 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
231 clocks = <&mstp2_clks R8A7740_CLK_SCIFA0>;
233 power-domains = <&pd_a3sp>;
237 scifa1: serial@e6c50000 {
238 compatible = "renesas,scifa-r8a7740", "renesas,scifa";
239 reg = <0xe6c50000 0x100>;
240 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
241 clocks = <&mstp2_clks R8A7740_CLK_SCIFA1>;
243 power-domains = <&pd_a3sp>;
247 scifa2: serial@e6c60000 {
248 compatible = "renesas,scifa-r8a7740", "renesas,scifa";
249 reg = <0xe6c60000 0x100>;
250 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
251 clocks = <&mstp2_clks R8A7740_CLK_SCIFA2>;
253 power-domains = <&pd_a3sp>;
257 scifa3: serial@e6c70000 {
258 compatible = "renesas,scifa-r8a7740", "renesas,scifa";
259 reg = <0xe6c70000 0x100>;
260 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
261 clocks = <&mstp2_clks R8A7740_CLK_SCIFA3>;
263 power-domains = <&pd_a3sp>;
267 scifa4: serial@e6c80000 {
268 compatible = "renesas,scifa-r8a7740", "renesas,scifa";
269 reg = <0xe6c80000 0x100>;
270 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
271 clocks = <&mstp2_clks R8A7740_CLK_SCIFA4>;
273 power-domains = <&pd_a3sp>;
277 scifa5: serial@e6cb0000 {
278 compatible = "renesas,scifa-r8a7740", "renesas,scifa";
279 reg = <0xe6cb0000 0x100>;
280 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
281 clocks = <&mstp2_clks R8A7740_CLK_SCIFA5>;
283 power-domains = <&pd_a3sp>;
287 scifa6: serial@e6cc0000 {
288 compatible = "renesas,scifa-r8a7740", "renesas,scifa";
289 reg = <0xe6cc0000 0x100>;
290 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
291 clocks = <&mstp2_clks R8A7740_CLK_SCIFA6>;
293 power-domains = <&pd_a3sp>;
297 scifa7: serial@e6cd0000 {
298 compatible = "renesas,scifa-r8a7740", "renesas,scifa";
299 reg = <0xe6cd0000 0x100>;
300 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
301 clocks = <&mstp2_clks R8A7740_CLK_SCIFA7>;
303 power-domains = <&pd_a3sp>;
307 scifb: serial@e6c30000 {
308 compatible = "renesas,scifb-r8a7740", "renesas,scifb";
309 reg = <0xe6c30000 0x100>;
310 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
311 clocks = <&mstp2_clks R8A7740_CLK_SCIFB>;
313 power-domains = <&pd_a3sp>;
317 pfc: pin-controller@e6050000 {
318 compatible = "renesas,pfc-r8a7740";
319 reg = <0xe6050000 0x8000>,
323 gpio-ranges = <&pfc 0 0 212>;
324 interrupts-extended =
325 <&irqpin0 0 0>, <&irqpin0 1 0>, <&irqpin0 2 0>, <&irqpin0 3 0>,
326 <&irqpin0 4 0>, <&irqpin0 5 0>, <&irqpin0 6 0>, <&irqpin0 7 0>,
327 <&irqpin1 0 0>, <&irqpin1 1 0>, <&irqpin1 2 0>, <&irqpin1 3 0>,
328 <&irqpin1 4 0>, <&irqpin1 5 0>, <&irqpin1 6 0>, <&irqpin1 7 0>,
329 <&irqpin2 0 0>, <&irqpin2 1 0>, <&irqpin2 2 0>, <&irqpin2 3 0>,
330 <&irqpin2 4 0>, <&irqpin2 5 0>, <&irqpin2 6 0>, <&irqpin2 7 0>,
331 <&irqpin3 0 0>, <&irqpin3 1 0>, <&irqpin3 2 0>, <&irqpin3 3 0>,
332 <&irqpin3 4 0>, <&irqpin3 5 0>, <&irqpin3 6 0>, <&irqpin3 7 0>;
333 power-domains = <&pd_c5>;
337 compatible = "renesas,tpu-r8a7740", "renesas,tpu";
338 reg = <0xe6600000 0x148>;
339 clocks = <&mstp3_clks R8A7740_CLK_TPU0>;
340 power-domains = <&pd_a3sp>;
345 mmcif0: mmc@e6bd0000 {
346 compatible = "renesas,mmcif-r8a7740", "renesas,sh-mmcif";
347 reg = <0xe6bd0000 0x100>;
348 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH
349 GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
350 clocks = <&mstp3_clks R8A7740_CLK_MMC>;
351 power-domains = <&pd_a3sp>;
356 compatible = "renesas,sdhi-r8a7740";
357 reg = <0xe6850000 0x100>;
358 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH
359 GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH
360 GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
361 clocks = <&mstp3_clks R8A7740_CLK_SDHI0>;
362 power-domains = <&pd_a3sp>;
369 compatible = "renesas,sdhi-r8a7740";
370 reg = <0xe6860000 0x100>;
371 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH
372 GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH
373 GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
374 clocks = <&mstp3_clks R8A7740_CLK_SDHI1>;
375 power-domains = <&pd_a3sp>;
382 compatible = "renesas,sdhi-r8a7740";
383 reg = <0xe6870000 0x100>;
384 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH
385 GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH
386 GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
387 clocks = <&mstp4_clks R8A7740_CLK_SDHI2>;
388 power-domains = <&pd_a3sp>;
394 sh_fsi2: sound@fe1f0000 {
395 #sound-dai-cells = <1>;
396 compatible = "renesas,fsi2-r8a7740", "renesas,sh_fsi2";
397 reg = <0xfe1f0000 0x400>;
398 interrupts = <GIC_SPI 9 0x4>;
399 clocks = <&mstp3_clks R8A7740_CLK_FSI>;
400 power-domains = <&pd_a4mp>;
404 tmu0: timer@fff80000 {
405 compatible = "renesas,tmu-r8a7740", "renesas,tmu";
406 reg = <0xfff80000 0x2c>;
407 interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
408 <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>,
409 <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>;
410 clocks = <&mstp1_clks R8A7740_CLK_TMU0>;
412 power-domains = <&pd_a4r>;
414 #renesas,channels = <3>;
419 tmu1: timer@fff90000 {
420 compatible = "renesas,tmu-r8a7740", "renesas,tmu";
421 reg = <0xfff90000 0x2c>;
422 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
423 <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>,
424 <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>;
425 clocks = <&mstp1_clks R8A7740_CLK_TMU1>;
427 power-domains = <&pd_a4r>;
429 #renesas,channels = <3>;
435 #address-cells = <1>;
439 /* External root clock */
441 compatible = "fixed-clock";
443 clock-frequency = <32768>;
446 compatible = "fixed-clock";
448 clock-frequency = <0>;
451 compatible = "fixed-clock";
453 clock-frequency = <0>;
456 compatible = "fixed-clock";
458 clock-frequency = <27000000>;
461 compatible = "fixed-clock";
463 clock-frequency = <0>;
466 compatible = "fixed-clock";
468 clock-frequency = <0>;
471 compatible = "fixed-clock";
473 clock-frequency = <0>;
476 compatible = "fixed-clock";
478 clock-frequency = <0>;
481 /* Special CPG clocks */
482 cpg_clocks: cpg_clocks@e6150000 {
483 compatible = "renesas,r8a7740-cpg-clocks";
484 reg = <0xe6150000 0x10000>;
485 clocks = <&extal1_clk>, <&extalr_clk>;
487 clock-output-names = "system", "pllc0", "pllc1",
490 "i", "zg", "b", "m1", "hp",
491 "hpp", "usbp", "s", "zb", "m3",
495 /* Variable factor clocks (DIV6) */
496 vclk1_clk: vclk1@e6150008 {
497 compatible = "renesas,r8a7740-div6-clock", "renesas,cpg-div6-clock";
498 reg = <0xe6150008 4>;
499 clocks = <&pllc1_div2_clk>, <0>, <&dv_clk>,
500 <&cpg_clocks R8A7740_CLK_USB24S>,
501 <&extal1_div2_clk>, <&extalr_clk>, <0>,
505 vclk2_clk: vclk2@e615000c {
506 compatible = "renesas,r8a7740-div6-clock", "renesas,cpg-div6-clock";
507 reg = <0xe615000c 4>;
508 clocks = <&pllc1_div2_clk>, <0>, <&dv_clk>,
509 <&cpg_clocks R8A7740_CLK_USB24S>,
510 <&extal1_div2_clk>, <&extalr_clk>, <0>,
514 fmsi_clk: fmsi@e6150010 {
515 compatible = "renesas,r8a7740-div6-clock", "renesas,cpg-div6-clock";
516 reg = <0xe6150010 4>;
517 clocks = <&pllc1_div2_clk>, <&fmsick_clk>, <0>, <0>;
520 fmso_clk: fmso@e6150014 {
521 compatible = "renesas,r8a7740-div6-clock", "renesas,cpg-div6-clock";
522 reg = <0xe6150014 4>;
523 clocks = <&pllc1_div2_clk>, <&fmsock_clk>, <0>, <0>;
526 fsia_clk: fsia@e6150018 {
527 compatible = "renesas,r8a7740-div6-clock", "renesas,cpg-div6-clock";
528 reg = <0xe6150018 4>;
529 clocks = <&pllc1_div2_clk>, <&fsiack_clk>, <0>, <0>;
532 sub_clk: sub@e6150080 {
533 compatible = "renesas,r8a7740-div6-clock", "renesas,cpg-div6-clock";
534 reg = <0xe6150080 4>;
535 clocks = <&pllc1_div2_clk>,
536 <&cpg_clocks R8A7740_CLK_USB24S>, <0>, <0>;
539 spu_clk: spu@e6150084 {
540 compatible = "renesas,r8a7740-div6-clock", "renesas,cpg-div6-clock";
541 reg = <0xe6150084 4>;
542 clocks = <&pllc1_div2_clk>,
543 <&cpg_clocks R8A7740_CLK_USB24S>, <0>, <0>;
546 vou_clk: vou@e6150088 {
547 compatible = "renesas,r8a7740-div6-clock", "renesas,cpg-div6-clock";
548 reg = <0xe6150088 4>;
549 clocks = <&pllc1_div2_clk>, <&extal1_clk>, <&dv_clk>,
553 stpro_clk: stpro@e615009c {
554 compatible = "renesas,r8a7740-div6-clock", "renesas,cpg-div6-clock";
555 reg = <0xe615009c 4>;
556 clocks = <&cpg_clocks R8A7740_CLK_PLLC0>;
560 /* Fixed factor clocks */
561 pllc1_div2_clk: pllc1_div2 {
562 compatible = "fixed-factor-clock";
563 clocks = <&cpg_clocks R8A7740_CLK_PLLC1>;
568 extal1_div2_clk: extal1_div2 {
569 compatible = "fixed-factor-clock";
570 clocks = <&extal1_clk>;
577 subck_clks: subck_clks@e6150080 {
578 compatible = "renesas,r8a7740-mstp-clocks", "renesas,cpg-mstp-clocks";
579 reg = <0xe6150080 4>;
580 clocks = <&sub_clk>, <&sub_clk>;
583 R8A7740_CLK_SUBCK R8A7740_CLK_SUBCK2
588 mstp1_clks: mstp1_clks@e6150134 {
589 compatible = "renesas,r8a7740-mstp-clocks", "renesas,cpg-mstp-clocks";
590 reg = <0xe6150134 4>, <0xe6150038 4>;
591 clocks = <&cpg_clocks R8A7740_CLK_S>,
592 <&cpg_clocks R8A7740_CLK_S>, <&sub_clk>,
593 <&cpg_clocks R8A7740_CLK_B>,
594 <&cpg_clocks R8A7740_CLK_HPP>, <&sub_clk>,
595 <&cpg_clocks R8A7740_CLK_B>;
598 R8A7740_CLK_CEU21 R8A7740_CLK_CEU20 R8A7740_CLK_TMU0
599 R8A7740_CLK_LCDC1 R8A7740_CLK_IIC0 R8A7740_CLK_TMU1
603 "ceu21", "ceu20", "tmu0", "lcdc1", "iic0",
606 mstp2_clks: mstp2_clks@e6150138 {
607 compatible = "renesas,r8a7740-mstp-clocks", "renesas,cpg-mstp-clocks";
608 reg = <0xe6150138 4>, <0xe6150040 4>;
609 clocks = <&sub_clk>, <&cpg_clocks R8A7740_CLK_HP>,
610 <&sub_clk>, <&cpg_clocks R8A7740_CLK_HP>,
611 <&cpg_clocks R8A7740_CLK_HP>,
612 <&cpg_clocks R8A7740_CLK_HP>,
613 <&cpg_clocks R8A7740_CLK_HP>,
614 <&sub_clk>, <&sub_clk>, <&sub_clk>,
615 <&sub_clk>, <&sub_clk>, <&sub_clk>,
619 R8A7740_CLK_SCIFA6 R8A7740_CLK_INTCA
621 R8A7740_CLK_DMAC1 R8A7740_CLK_DMAC2
622 R8A7740_CLK_DMAC3 R8A7740_CLK_USBDMAC
623 R8A7740_CLK_SCIFA5 R8A7740_CLK_SCIFB
624 R8A7740_CLK_SCIFA0 R8A7740_CLK_SCIFA1
625 R8A7740_CLK_SCIFA2 R8A7740_CLK_SCIFA3
630 "scifa7", "dmac1", "dmac2", "dmac3",
631 "usbdmac", "scifa5", "scifb", "scifa0", "scifa1",
632 "scifa2", "scifa3", "scifa4";
634 mstp3_clks: mstp3_clks@e615013c {
635 compatible = "renesas,r8a7740-mstp-clocks", "renesas,cpg-mstp-clocks";
636 reg = <0xe615013c 4>, <0xe6150048 4>;
637 clocks = <&cpg_clocks R8A7740_CLK_R>,
638 <&cpg_clocks R8A7740_CLK_HP>,
640 <&cpg_clocks R8A7740_CLK_HP>,
641 <&cpg_clocks R8A7740_CLK_HP>,
642 <&cpg_clocks R8A7740_CLK_HP>,
643 <&cpg_clocks R8A7740_CLK_HP>,
644 <&cpg_clocks R8A7740_CLK_HP>,
645 <&cpg_clocks R8A7740_CLK_HP>;
648 R8A7740_CLK_CMT1 R8A7740_CLK_FSI R8A7740_CLK_IIC1
649 R8A7740_CLK_USBF R8A7740_CLK_SDHI0 R8A7740_CLK_SDHI1
650 R8A7740_CLK_MMC R8A7740_CLK_GETHER R8A7740_CLK_TPU0
653 "cmt1", "fsi", "iic1", "usbf", "sdhi0", "sdhi1",
654 "mmc", "gether", "tpu0";
656 mstp4_clks: mstp4_clks@e6150140 {
657 compatible = "renesas,r8a7740-mstp-clocks", "renesas,cpg-mstp-clocks";
658 reg = <0xe6150140 4>, <0xe615004c 4>;
659 clocks = <&cpg_clocks R8A7740_CLK_HP>,
660 <&cpg_clocks R8A7740_CLK_HP>,
661 <&cpg_clocks R8A7740_CLK_HP>,
662 <&cpg_clocks R8A7740_CLK_HP>;
665 R8A7740_CLK_USBH R8A7740_CLK_SDHI2
666 R8A7740_CLK_USBFUNC R8A7740_CLK_USBPHY
669 "usbhost", "sdhi2", "usbfunc", "usphy";
673 sysc: system-controller@e6180000 {
674 compatible = "renesas,sysc-r8a7740", "renesas,sysc-rmobile";
675 reg = <0xe6180000 0x8000>, <0xe6188000 0x8000>;
679 #address-cells = <1>;
681 #power-domain-cells = <0>;
685 #power-domain-cells = <0>;
690 #power-domain-cells = <0>;
695 #power-domain-cells = <0>;
700 #address-cells = <1>;
702 #power-domain-cells = <0>;
706 #power-domain-cells = <0>;
712 #address-cells = <1>;
714 #power-domain-cells = <0>;
718 #power-domain-cells = <0>;
723 #power-domain-cells = <0>;
728 #power-domain-cells = <0>;
734 #power-domain-cells = <0>;