1 // SPDX-License-Identifier: GPL-2.0
3 * Device Tree Source for the r8a7742 SoC
5 * Copyright (C) 2020 Renesas Electronics Corp.
8 #include <dt-bindings/clock/r8a7742-cpg-mssr.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/interrupt-controller/irq.h>
11 #include <dt-bindings/power/r8a7742-sysc.h>
14 compatible = "renesas,r8a7742";
24 compatible = "arm,cortex-a15";
26 clock-frequency = <1400000000>;
27 clocks = <&cpg CPG_CORE R8A7742_CLK_Z>;
28 power-domains = <&sysc R8A7742_PD_CA15_CPU0>;
29 next-level-cache = <&L2_CA15>;
30 capacity-dmips-mhz = <1024>;
31 voltage-tolerance = <1>; /* 1% */
32 clock-latency = <300000>; /* 300 us */
34 /* kHz - uV - OPPs unknown yet */
35 operating-points = <1400000 1000000>,
45 compatible = "arm,cortex-a15";
47 clock-frequency = <1400000000>;
48 clocks = <&cpg CPG_CORE R8A7742_CLK_Z>;
49 power-domains = <&sysc R8A7742_PD_CA15_CPU1>;
50 next-level-cache = <&L2_CA15>;
51 capacity-dmips-mhz = <1024>;
52 voltage-tolerance = <1>; /* 1% */
53 clock-latency = <300000>; /* 300 us */
55 /* kHz - uV - OPPs unknown yet */
56 operating-points = <1400000 1000000>,
66 compatible = "arm,cortex-a15";
68 clock-frequency = <1400000000>;
69 clocks = <&cpg CPG_CORE R8A7742_CLK_Z>;
70 power-domains = <&sysc R8A7742_PD_CA15_CPU2>;
71 next-level-cache = <&L2_CA15>;
72 capacity-dmips-mhz = <1024>;
73 voltage-tolerance = <1>; /* 1% */
74 clock-latency = <300000>; /* 300 us */
76 /* kHz - uV - OPPs unknown yet */
77 operating-points = <1400000 1000000>,
87 compatible = "arm,cortex-a15";
89 clock-frequency = <1400000000>;
90 clocks = <&cpg CPG_CORE R8A7742_CLK_Z>;
91 power-domains = <&sysc R8A7742_PD_CA15_CPU3>;
92 next-level-cache = <&L2_CA15>;
93 capacity-dmips-mhz = <1024>;
94 voltage-tolerance = <1>; /* 1% */
95 clock-latency = <300000>; /* 300 us */
97 /* kHz - uV - OPPs unknown yet */
98 operating-points = <1400000 1000000>,
108 compatible = "arm,cortex-a7";
110 clock-frequency = <780000000>;
111 clocks = <&cpg CPG_CORE R8A7742_CLK_Z2>;
112 power-domains = <&sysc R8A7742_PD_CA7_CPU0>;
113 next-level-cache = <&L2_CA7>;
118 compatible = "arm,cortex-a7";
120 clock-frequency = <780000000>;
121 clocks = <&cpg CPG_CORE R8A7742_CLK_Z2>;
122 power-domains = <&sysc R8A7742_PD_CA7_CPU1>;
123 next-level-cache = <&L2_CA7>;
128 compatible = "arm,cortex-a7";
130 clock-frequency = <780000000>;
131 clocks = <&cpg CPG_CORE R8A7742_CLK_Z2>;
132 power-domains = <&sysc R8A7742_PD_CA7_CPU2>;
133 next-level-cache = <&L2_CA7>;
138 compatible = "arm,cortex-a7";
140 clock-frequency = <780000000>;
141 clocks = <&cpg CPG_CORE R8A7742_CLK_Z2>;
142 power-domains = <&sysc R8A7742_PD_CA7_CPU3>;
143 next-level-cache = <&L2_CA7>;
146 L2_CA15: cache-controller-0 {
147 compatible = "cache";
148 power-domains = <&sysc R8A7742_PD_CA15_SCU>;
153 L2_CA7: cache-controller-1 {
154 compatible = "cache";
155 power-domains = <&sysc R8A7742_PD_CA7_SCU>;
161 /* External root clock */
163 compatible = "fixed-clock";
165 /* This value must be overridden by the board. */
166 clock-frequency = <0>;
170 compatible = "arm,cortex-a15-pmu";
171 interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
172 <&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
173 <&gic GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
174 <&gic GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
175 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
179 compatible = "arm,cortex-a7-pmu";
180 interrupts-extended = <&gic GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>,
181 <&gic GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>,
182 <&gic GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
183 <&gic GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
184 interrupt-affinity = <&cpu4>, <&cpu5>, <&cpu6>, <&cpu7>;
187 /* External SCIF clock */
189 compatible = "fixed-clock";
191 /* This value must be overridden by the board. */
192 clock-frequency = <0>;
196 compatible = "simple-bus";
197 interrupt-parent = <&gic>;
199 #address-cells = <2>;
203 gpio0: gpio@e6050000 {
204 compatible = "renesas,gpio-r8a7742",
205 "renesas,rcar-gen2-gpio";
206 reg = <0 0xe6050000 0 0x50>;
207 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
210 gpio-ranges = <&pfc 0 0 32>;
211 #interrupt-cells = <2>;
212 interrupt-controller;
213 clocks = <&cpg CPG_MOD 912>;
214 power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
218 gpio1: gpio@e6051000 {
219 compatible = "renesas,gpio-r8a7742",
220 "renesas,rcar-gen2-gpio";
221 reg = <0 0xe6051000 0 0x50>;
222 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
225 gpio-ranges = <&pfc 0 32 30>;
226 #interrupt-cells = <2>;
227 interrupt-controller;
228 clocks = <&cpg CPG_MOD 911>;
229 power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
233 gpio2: gpio@e6052000 {
234 compatible = "renesas,gpio-r8a7742",
235 "renesas,rcar-gen2-gpio";
236 reg = <0 0xe6052000 0 0x50>;
237 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
240 gpio-ranges = <&pfc 0 64 30>;
241 #interrupt-cells = <2>;
242 interrupt-controller;
243 clocks = <&cpg CPG_MOD 910>;
244 power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
248 gpio3: gpio@e6053000 {
249 compatible = "renesas,gpio-r8a7742",
250 "renesas,rcar-gen2-gpio";
251 reg = <0 0xe6053000 0 0x50>;
252 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
255 gpio-ranges = <&pfc 0 96 32>;
256 #interrupt-cells = <2>;
257 interrupt-controller;
258 clocks = <&cpg CPG_MOD 909>;
259 power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
263 gpio4: gpio@e6054000 {
264 compatible = "renesas,gpio-r8a7742",
265 "renesas,rcar-gen2-gpio";
266 reg = <0 0xe6054000 0 0x50>;
267 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
270 gpio-ranges = <&pfc 0 128 32>;
271 #interrupt-cells = <2>;
272 interrupt-controller;
273 clocks = <&cpg CPG_MOD 908>;
274 power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
278 gpio5: gpio@e6055000 {
279 compatible = "renesas,gpio-r8a7742",
280 "renesas,rcar-gen2-gpio";
281 reg = <0 0xe6055000 0 0x50>;
282 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
285 gpio-ranges = <&pfc 0 160 32>;
286 #interrupt-cells = <2>;
287 interrupt-controller;
288 clocks = <&cpg CPG_MOD 907>;
289 power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
293 pfc: pin-controller@e6060000 {
294 compatible = "renesas,pfc-r8a7742";
295 reg = <0 0xe6060000 0 0x250>;
298 cpg: clock-controller@e6150000 {
299 compatible = "renesas,r8a7742-cpg-mssr";
300 reg = <0 0xe6150000 0 0x1000>;
301 clocks = <&extal_clk>, <&usb_extal_clk>;
302 clock-names = "extal", "usb_extal";
304 #power-domain-cells = <0>;
308 rst: reset-controller@e6160000 {
309 compatible = "renesas,r8a7742-rst";
310 reg = <0 0xe6160000 0 0x0100>;
313 sysc: system-controller@e6180000 {
314 compatible = "renesas,r8a7742-sysc";
315 reg = <0 0xe6180000 0 0x0200>;
316 #power-domain-cells = <1>;
319 irqc: interrupt-controller@e61c0000 {
320 compatible = "renesas,irqc-r8a7742", "renesas,irqc";
321 #interrupt-cells = <2>;
322 interrupt-controller;
323 reg = <0 0xe61c0000 0 0x200>;
324 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
325 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
326 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
327 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
328 clocks = <&cpg CPG_MOD 407>;
329 power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
333 icram0: sram@e63a0000 {
334 compatible = "mmio-sram";
335 reg = <0 0xe63a0000 0 0x12000>;
336 #address-cells = <1>;
338 ranges = <0 0 0xe63a0000 0x12000>;
341 icram1: sram@e63c0000 {
342 compatible = "mmio-sram";
343 reg = <0 0xe63c0000 0 0x1000>;
344 #address-cells = <1>;
346 ranges = <0 0 0xe63c0000 0x1000>;
349 compatible = "renesas,smp-sram";
354 icram2: sram@e6300000 {
355 compatible = "mmio-sram";
356 reg = <0 0xe6300000 0 0x40000>;
357 #address-cells = <1>;
359 ranges = <0 0 0xe6300000 0x40000>;
362 dmac0: dma-controller@e6700000 {
363 compatible = "renesas,dmac-r8a7742",
365 reg = <0 0xe6700000 0 0x20000>;
366 interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>,
367 <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>,
368 <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>,
369 <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>,
370 <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>,
371 <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
372 <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>,
373 <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>,
374 <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,
375 <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>,
376 <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>,
377 <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>,
378 <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>,
379 <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>,
380 <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>,
381 <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>;
382 interrupt-names = "error",
383 "ch0", "ch1", "ch2", "ch3",
384 "ch4", "ch5", "ch6", "ch7",
385 "ch8", "ch9", "ch10", "ch11",
386 "ch12", "ch13", "ch14";
387 clocks = <&cpg CPG_MOD 219>;
389 power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
395 dmac1: dma-controller@e6720000 {
396 compatible = "renesas,dmac-r8a7742",
398 reg = <0 0xe6720000 0 0x20000>;
399 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>,
400 <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>,
401 <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>,
402 <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>,
403 <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>,
404 <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>,
405 <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>,
406 <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>,
407 <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>,
408 <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>,
409 <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>,
410 <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>,
411 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
412 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
413 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
414 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>;
415 interrupt-names = "error",
416 "ch0", "ch1", "ch2", "ch3",
417 "ch4", "ch5", "ch6", "ch7",
418 "ch8", "ch9", "ch10", "ch11",
419 "ch12", "ch13", "ch14";
420 clocks = <&cpg CPG_MOD 218>;
422 power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
428 scifa0: serial@e6c40000 {
429 compatible = "renesas,scifa-r8a7742",
430 "renesas,rcar-gen2-scifa", "renesas,scifa";
431 reg = <0 0xe6c40000 0 0x40>;
432 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
433 clocks = <&cpg CPG_MOD 204>;
435 dmas = <&dmac0 0x21>, <&dmac0 0x22>,
436 <&dmac1 0x21>, <&dmac1 0x22>;
437 dma-names = "tx", "rx", "tx", "rx";
438 power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
443 scifa1: serial@e6c50000 {
444 compatible = "renesas,scifa-r8a7742",
445 "renesas,rcar-gen2-scifa", "renesas,scifa";
446 reg = <0 0xe6c50000 0 0x40>;
447 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
448 clocks = <&cpg CPG_MOD 203>;
450 dmas = <&dmac0 0x25>, <&dmac0 0x26>,
451 <&dmac1 0x25>, <&dmac1 0x26>;
452 dma-names = "tx", "rx", "tx", "rx";
453 power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
458 scifa2: serial@e6c60000 {
459 compatible = "renesas,scifa-r8a7742",
460 "renesas,rcar-gen2-scifa", "renesas,scifa";
461 reg = <0 0xe6c60000 0 0x40>;
462 interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;
463 clocks = <&cpg CPG_MOD 202>;
465 dmas = <&dmac0 0x27>, <&dmac0 0x28>,
466 <&dmac1 0x27>, <&dmac1 0x28>;
467 dma-names = "tx", "rx", "tx", "rx";
468 power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
473 scifb0: serial@e6c20000 {
474 compatible = "renesas,scifb-r8a7742",
475 "renesas,rcar-gen2-scifb", "renesas,scifb";
476 reg = <0 0xe6c20000 0 0x100>;
477 interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
478 clocks = <&cpg CPG_MOD 206>;
480 dmas = <&dmac0 0x3d>, <&dmac0 0x3e>,
481 <&dmac1 0x3d>, <&dmac1 0x3e>;
482 dma-names = "tx", "rx", "tx", "rx";
483 power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
488 scifb1: serial@e6c30000 {
489 compatible = "renesas,scifb-r8a7742",
490 "renesas,rcar-gen2-scifb", "renesas,scifb";
491 reg = <0 0xe6c30000 0 0x100>;
492 interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
493 clocks = <&cpg CPG_MOD 207>;
495 dmas = <&dmac0 0x19>, <&dmac0 0x1a>,
496 <&dmac1 0x19>, <&dmac1 0x1a>;
497 dma-names = "tx", "rx", "tx", "rx";
498 power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
503 scifb2: serial@e6ce0000 {
504 compatible = "renesas,scifb-r8a7742",
505 "renesas,rcar-gen2-scifb", "renesas,scifb";
506 reg = <0 0xe6ce0000 0 0x100>;
507 interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
508 clocks = <&cpg CPG_MOD 216>;
510 dmas = <&dmac0 0x1d>, <&dmac0 0x1e>,
511 <&dmac1 0x1d>, <&dmac1 0x1e>;
512 dma-names = "tx", "rx", "tx", "rx";
513 power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
518 scif0: serial@e6e60000 {
519 compatible = "renesas,scif-r8a7742",
520 "renesas,rcar-gen2-scif", "renesas,scif";
521 reg = <0 0xe6e60000 0 0x40>;
522 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
523 clocks = <&cpg CPG_MOD 721>,
524 <&cpg CPG_CORE R8A7742_CLK_ZS>, <&scif_clk>;
525 clock-names = "fck", "brg_int", "scif_clk";
526 dmas = <&dmac0 0x29>, <&dmac0 0x2a>,
527 <&dmac1 0x29>, <&dmac1 0x2a>;
528 dma-names = "tx", "rx", "tx", "rx";
529 power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
534 scif1: serial@e6e68000 {
535 compatible = "renesas,scif-r8a7742",
536 "renesas,rcar-gen2-scif", "renesas,scif";
537 reg = <0 0xe6e68000 0 0x40>;
538 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
539 clocks = <&cpg CPG_MOD 720>,
540 <&cpg CPG_CORE R8A7742_CLK_ZS>, <&scif_clk>;
541 clock-names = "fck", "brg_int", "scif_clk";
542 dmas = <&dmac0 0x2d>, <&dmac0 0x2e>,
543 <&dmac1 0x2d>, <&dmac1 0x2e>;
544 dma-names = "tx", "rx", "tx", "rx";
545 power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
550 scif2: serial@e6e56000 {
551 compatible = "renesas,scif-r8a7742",
552 "renesas,rcar-gen2-scif", "renesas,scif";
553 reg = <0 0xe6e56000 0 0x40>;
554 interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
555 clocks = <&cpg CPG_MOD 310>,
556 <&cpg CPG_CORE R8A7742_CLK_ZS>, <&scif_clk>;
557 clock-names = "fck", "brg_int", "scif_clk";
558 dmas = <&dmac0 0x2b>, <&dmac0 0x2c>,
559 <&dmac1 0x2b>, <&dmac1 0x2c>;
560 dma-names = "tx", "rx", "tx", "rx";
561 power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
566 hscif0: serial@e62c0000 {
567 compatible = "renesas,hscif-r8a7742",
568 "renesas,rcar-gen2-hscif", "renesas,hscif";
569 reg = <0 0xe62c0000 0 0x60>;
570 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
571 clocks = <&cpg CPG_MOD 717>,
572 <&cpg CPG_CORE R8A7742_CLK_ZS>, <&scif_clk>;
573 clock-names = "fck", "brg_int", "scif_clk";
574 dmas = <&dmac0 0x39>, <&dmac0 0x3a>,
575 <&dmac1 0x39>, <&dmac1 0x3a>;
576 dma-names = "tx", "rx", "tx", "rx";
577 power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
582 hscif1: serial@e62c8000 {
583 compatible = "renesas,hscif-r8a7742",
584 "renesas,rcar-gen2-hscif", "renesas,hscif";
585 reg = <0 0xe62c8000 0 0x60>;
586 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
587 clocks = <&cpg CPG_MOD 716>,
588 <&cpg CPG_CORE R8A7742_CLK_ZS>, <&scif_clk>;
589 clock-names = "fck", "brg_int", "scif_clk";
590 dmas = <&dmac0 0x4d>, <&dmac0 0x4e>,
591 <&dmac1 0x4d>, <&dmac1 0x4e>;
592 dma-names = "tx", "rx", "tx", "rx";
593 power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
598 mmcif1: mmc@ee220000 {
599 compatible = "renesas,mmcif-r8a7742",
601 reg = <0 0xee220000 0 0x80>;
602 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
603 clocks = <&cpg CPG_MOD 305>;
604 dmas = <&dmac0 0xe1>, <&dmac0 0xe2>,
605 <&dmac1 0xe1>, <&dmac1 0xe2>;
606 dma-names = "tx", "rx", "tx", "rx";
607 power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
611 max-frequency = <97500000>;
614 gic: interrupt-controller@f1001000 {
615 compatible = "arm,gic-400";
616 #interrupt-cells = <3>;
617 #address-cells = <0>;
618 interrupt-controller;
619 reg = <0 0xf1001000 0 0x1000>, <0 0xf1002000 0 0x2000>,
620 <0 0xf1004000 0 0x2000>, <0 0xf1006000 0 0x2000>;
621 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
622 clocks = <&cpg CPG_MOD 408>;
624 power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
628 prr: chipid@ff000044 {
629 compatible = "renesas,prr";
630 reg = <0 0xff000044 0 4>;
635 compatible = "arm,armv7-timer";
636 interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
637 <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
638 <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
639 <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
642 /* External USB clock - can be overridden by the board */
643 usb_extal_clk: usb_extal {
644 compatible = "fixed-clock";
646 clock-frequency = <48000000>;