2 * Device Tree Source for Renesas r8a7778
4 * Copyright (C) 2013 Renesas Solutions Corp.
5 * Copyright (C) 2013 Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
9 * Copyright (C) 2013 Renesas Solutions Corp.
10 * Copyright (C) 2013 Simon Horman
12 * This file is licensed under the terms of the GNU General Public License
13 * version 2. This program is licensed "as is" without any warranty of any
14 * kind, whether express or implied.
17 #include <dt-bindings/clock/r8a7778-clock.h>
18 #include <dt-bindings/interrupt-controller/arm-gic.h>
19 #include <dt-bindings/interrupt-controller/irq.h>
22 compatible = "renesas,r8a7778";
23 interrupt-parent = <&gic>;
33 compatible = "arm,cortex-a9";
35 clock-frequency = <800000000>;
47 compatible = "simple-bus";
50 ranges = <0 0 0x1c000000>;
53 ether: ethernet@fde00000 {
54 compatible = "renesas,ether-r8a7778";
55 reg = <0xfde00000 0x400>;
56 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
57 clocks = <&mstp1_clks R8A7778_CLK_ETHER>;
58 power-domains = <&cpg_clocks>;
65 gic: interrupt-controller@fe438000 {
66 compatible = "arm,pl390";
67 #interrupt-cells = <3>;
69 reg = <0xfe438000 0x1000>,
73 /* irqpin: IRQ0 - IRQ3 */
74 irqpin: interrupt-controller@fe78001c {
75 compatible = "renesas,intc-irqpin-r8a7778", "renesas,intc-irqpin";
76 #interrupt-cells = <2>;
78 status = "disabled"; /* default off */
84 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH
85 GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH
86 GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH
87 GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
88 sense-bitfield-width = <2>;
91 gpio0: gpio@ffc40000 {
92 compatible = "renesas,gpio-r8a7778", "renesas,rcar-gen1-gpio";
93 reg = <0xffc40000 0x2c>;
94 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
97 gpio-ranges = <&pfc 0 0 32>;
98 #interrupt-cells = <2>;
102 gpio1: gpio@ffc41000 {
103 compatible = "renesas,gpio-r8a7778", "renesas,rcar-gen1-gpio";
104 reg = <0xffc41000 0x2c>;
105 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
108 gpio-ranges = <&pfc 0 32 32>;
109 #interrupt-cells = <2>;
110 interrupt-controller;
113 gpio2: gpio@ffc42000 {
114 compatible = "renesas,gpio-r8a7778", "renesas,rcar-gen1-gpio";
115 reg = <0xffc42000 0x2c>;
116 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
119 gpio-ranges = <&pfc 0 64 32>;
120 #interrupt-cells = <2>;
121 interrupt-controller;
124 gpio3: gpio@ffc43000 {
125 compatible = "renesas,gpio-r8a7778", "renesas,rcar-gen1-gpio";
126 reg = <0xffc43000 0x2c>;
127 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
130 gpio-ranges = <&pfc 0 96 32>;
131 #interrupt-cells = <2>;
132 interrupt-controller;
135 gpio4: gpio@ffc44000 {
136 compatible = "renesas,gpio-r8a7778", "renesas,rcar-gen1-gpio";
137 reg = <0xffc44000 0x2c>;
138 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
141 gpio-ranges = <&pfc 0 128 27>;
142 #interrupt-cells = <2>;
143 interrupt-controller;
146 pfc: pin-controller@fffc0000 {
147 compatible = "renesas,pfc-r8a7778";
148 reg = <0xfffc0000 0x118>;
152 #address-cells = <1>;
154 compatible = "renesas,i2c-r8a7778", "renesas,rcar-gen1-i2c";
155 reg = <0xffc70000 0x1000>;
156 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
157 clocks = <&mstp0_clks R8A7778_CLK_I2C0>;
158 power-domains = <&cpg_clocks>;
163 #address-cells = <1>;
165 compatible = "renesas,i2c-r8a7778", "renesas,rcar-gen1-i2c";
166 reg = <0xffc71000 0x1000>;
167 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
168 clocks = <&mstp0_clks R8A7778_CLK_I2C1>;
169 power-domains = <&cpg_clocks>;
174 #address-cells = <1>;
176 compatible = "renesas,i2c-r8a7778", "renesas,rcar-gen1-i2c";
177 reg = <0xffc72000 0x1000>;
178 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
179 clocks = <&mstp0_clks R8A7778_CLK_I2C2>;
180 power-domains = <&cpg_clocks>;
185 #address-cells = <1>;
187 compatible = "renesas,i2c-r8a7778", "renesas,rcar-gen1-i2c";
188 reg = <0xffc73000 0x1000>;
189 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
190 clocks = <&mstp0_clks R8A7778_CLK_I2C3>;
191 power-domains = <&cpg_clocks>;
195 tmu0: timer@ffd80000 {
196 compatible = "renesas,tmu-r8a7778", "renesas,tmu";
197 reg = <0xffd80000 0x30>;
198 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
199 <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
200 <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
201 clocks = <&mstp0_clks R8A7778_CLK_TMU0>;
203 power-domains = <&cpg_clocks>;
205 #renesas,channels = <3>;
210 tmu1: timer@ffd81000 {
211 compatible = "renesas,tmu-r8a7778", "renesas,tmu";
212 reg = <0xffd81000 0x30>;
213 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>,
214 <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>,
215 <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
216 clocks = <&mstp0_clks R8A7778_CLK_TMU1>;
218 power-domains = <&cpg_clocks>;
220 #renesas,channels = <3>;
225 tmu2: timer@ffd82000 {
226 compatible = "renesas,tmu-r8a7778", "renesas,tmu";
227 reg = <0xffd82000 0x30>;
228 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
229 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
230 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
231 clocks = <&mstp0_clks R8A7778_CLK_TMU2>;
233 power-domains = <&cpg_clocks>;
235 #renesas,channels = <3>;
240 rcar_sound: sound@ffd90000 {
242 * #sound-dai-cells is required
244 * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>;
245 * Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>;
247 compatible = "renesas,rcar_sound-r8a7778", "renesas,rcar_sound-gen1";
248 reg = <0xffd90000 0x1000>, /* SRU */
249 <0xffd91000 0x240>, /* SSI */
250 <0xfffe0000 0x24>; /* ADG */
251 clocks = <&mstp3_clks R8A7778_CLK_SSI8>,
252 <&mstp3_clks R8A7778_CLK_SSI7>,
253 <&mstp3_clks R8A7778_CLK_SSI6>,
254 <&mstp3_clks R8A7778_CLK_SSI5>,
255 <&mstp3_clks R8A7778_CLK_SSI4>,
256 <&mstp0_clks R8A7778_CLK_SSI3>,
257 <&mstp0_clks R8A7778_CLK_SSI2>,
258 <&mstp0_clks R8A7778_CLK_SSI1>,
259 <&mstp0_clks R8A7778_CLK_SSI0>,
260 <&mstp5_clks R8A7778_CLK_SRU_SRC8>,
261 <&mstp5_clks R8A7778_CLK_SRU_SRC7>,
262 <&mstp5_clks R8A7778_CLK_SRU_SRC6>,
263 <&mstp5_clks R8A7778_CLK_SRU_SRC5>,
264 <&mstp5_clks R8A7778_CLK_SRU_SRC4>,
265 <&mstp5_clks R8A7778_CLK_SRU_SRC3>,
266 <&mstp5_clks R8A7778_CLK_SRU_SRC2>,
267 <&mstp5_clks R8A7778_CLK_SRU_SRC1>,
268 <&mstp5_clks R8A7778_CLK_SRU_SRC0>,
269 <&audio_clk_a>, <&audio_clk_b>, <&audio_clk_c>,
270 <&cpg_clocks R8A7778_CLK_S1>;
271 clock-names = "ssi.8", "ssi.7", "ssi.6", "ssi.5", "ssi.4",
272 "ssi.3", "ssi.2", "ssi.1", "ssi.0",
273 "src.8", "src.7", "src.6", "src.5", "src.4",
274 "src.3", "src.2", "src.1", "src.0",
275 "clk_a", "clk_b", "clk_c", "clk_i";
290 ssi3: ssi-3 { interrupts = <GIC_SPI 0x85 IRQ_TYPE_LEVEL_HIGH>; };
291 ssi4: ssi-4 { interrupts = <GIC_SPI 0x85 IRQ_TYPE_LEVEL_HIGH>; };
292 ssi5: ssi-5 { interrupts = <GIC_SPI 0x86 IRQ_TYPE_LEVEL_HIGH>; };
293 ssi6: ssi-6 { interrupts = <GIC_SPI 0x86 IRQ_TYPE_LEVEL_HIGH>; };
294 ssi7: ssi-7 { interrupts = <GIC_SPI 0x86 IRQ_TYPE_LEVEL_HIGH>; };
295 ssi8: ssi-8 { interrupts = <GIC_SPI 0x86 IRQ_TYPE_LEVEL_HIGH>; };
296 ssi9: ssi-9 { interrupts = <GIC_SPI 0x86 IRQ_TYPE_LEVEL_HIGH>; };
300 scif0: serial@ffe40000 {
301 compatible = "renesas,scif-r8a7778", "renesas,rcar-gen1-scif",
303 reg = <0xffe40000 0x100>;
304 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
305 clocks = <&mstp0_clks R8A7778_CLK_SCIF0>,
306 <&cpg_clocks R8A7778_CLK_S1>, <&scif_clk>;
307 clock-names = "fck", "brg_int", "scif_clk";
308 power-domains = <&cpg_clocks>;
312 scif1: serial@ffe41000 {
313 compatible = "renesas,scif-r8a7778", "renesas,rcar-gen1-scif",
315 reg = <0xffe41000 0x100>;
316 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
317 clocks = <&mstp0_clks R8A7778_CLK_SCIF1>,
318 <&cpg_clocks R8A7778_CLK_S1>, <&scif_clk>;
319 clock-names = "fck", "brg_int", "scif_clk";
320 power-domains = <&cpg_clocks>;
324 scif2: serial@ffe42000 {
325 compatible = "renesas,scif-r8a7778", "renesas,rcar-gen1-scif",
327 reg = <0xffe42000 0x100>;
328 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
329 clocks = <&mstp0_clks R8A7778_CLK_SCIF2>,
330 <&cpg_clocks R8A7778_CLK_S1>, <&scif_clk>;
331 clock-names = "fck", "brg_int", "scif_clk";
332 power-domains = <&cpg_clocks>;
336 scif3: serial@ffe43000 {
337 compatible = "renesas,scif-r8a7778", "renesas,rcar-gen1-scif",
339 reg = <0xffe43000 0x100>;
340 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
341 clocks = <&mstp0_clks R8A7778_CLK_SCIF3>,
342 <&cpg_clocks R8A7778_CLK_S1>, <&scif_clk>;
343 clock-names = "fck", "brg_int", "scif_clk";
344 power-domains = <&cpg_clocks>;
348 scif4: serial@ffe44000 {
349 compatible = "renesas,scif-r8a7778", "renesas,rcar-gen1-scif",
351 reg = <0xffe44000 0x100>;
352 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
353 clocks = <&mstp0_clks R8A7778_CLK_SCIF4>,
354 <&cpg_clocks R8A7778_CLK_S1>, <&scif_clk>;
355 clock-names = "fck", "brg_int", "scif_clk";
356 power-domains = <&cpg_clocks>;
360 scif5: serial@ffe45000 {
361 compatible = "renesas,scif-r8a7778", "renesas,rcar-gen1-scif",
363 reg = <0xffe45000 0x100>;
364 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
365 clocks = <&mstp0_clks R8A7778_CLK_SCIF5>,
366 <&cpg_clocks R8A7778_CLK_S1>, <&scif_clk>;
367 clock-names = "fck", "brg_int", "scif_clk";
368 power-domains = <&cpg_clocks>;
372 mmcif: mmc@ffe4e000 {
373 compatible = "renesas,mmcif-r8a7778", "renesas,sh-mmcif";
374 reg = <0xffe4e000 0x100>;
375 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
376 clocks = <&mstp3_clks R8A7778_CLK_MMC>;
377 power-domains = <&cpg_clocks>;
382 compatible = "renesas,sdhi-r8a7778";
383 reg = <0xffe4c000 0x100>;
384 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
385 clocks = <&mstp3_clks R8A7778_CLK_SDHI0>;
386 power-domains = <&cpg_clocks>;
391 compatible = "renesas,sdhi-r8a7778";
392 reg = <0xffe4d000 0x100>;
393 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
394 clocks = <&mstp3_clks R8A7778_CLK_SDHI1>;
395 power-domains = <&cpg_clocks>;
400 compatible = "renesas,sdhi-r8a7778";
401 reg = <0xffe4f000 0x100>;
402 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
403 clocks = <&mstp3_clks R8A7778_CLK_SDHI2>;
404 power-domains = <&cpg_clocks>;
408 hspi0: spi@fffc7000 {
409 compatible = "renesas,hspi-r8a7778", "renesas,hspi";
410 reg = <0xfffc7000 0x18>;
411 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
412 clocks = <&mstp0_clks R8A7778_CLK_HSPI>;
413 power-domains = <&cpg_clocks>;
414 #address-cells = <1>;
419 hspi1: spi@fffc8000 {
420 compatible = "renesas,hspi-r8a7778", "renesas,hspi";
421 reg = <0xfffc8000 0x18>;
422 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
423 clocks = <&mstp0_clks R8A7778_CLK_HSPI>;
424 power-domains = <&cpg_clocks>;
425 #address-cells = <1>;
430 hspi2: spi@fffc6000 {
431 compatible = "renesas,hspi-r8a7778", "renesas,hspi";
432 reg = <0xfffc6000 0x18>;
433 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
434 clocks = <&mstp0_clks R8A7778_CLK_HSPI>;
435 power-domains = <&cpg_clocks>;
436 #address-cells = <1>;
442 #address-cells = <1>;
446 /* External input clock */
448 compatible = "fixed-clock";
450 clock-frequency = <0>;
453 /* External SCIF clock */
455 compatible = "fixed-clock";
457 /* This value must be overridden by the board. */
458 clock-frequency = <0>;
461 /* Special CPG clocks */
462 cpg_clocks: cpg_clocks@ffc80000 {
463 compatible = "renesas,r8a7778-cpg-clocks";
464 reg = <0xffc80000 0x80>;
466 clocks = <&extal_clk>;
467 clock-output-names = "plla", "pllb", "b",
468 "out", "p", "s", "s1";
469 #power-domain-cells = <0>;
472 /* Audio clocks; frequencies are set by boards if applicable. */
473 audio_clk_a: audio_clk_a {
474 compatible = "fixed-clock";
477 audio_clk_b: audio_clk_b {
478 compatible = "fixed-clock";
481 audio_clk_c: audio_clk_c {
482 compatible = "fixed-clock";
486 /* Fixed ratio clocks */
488 compatible = "fixed-factor-clock";
489 clocks = <&cpg_clocks R8A7778_CLK_PLLA>;
495 compatible = "fixed-factor-clock";
496 clocks = <&cpg_clocks R8A7778_CLK_PLLA>;
502 compatible = "fixed-factor-clock";
503 clocks = <&cpg_clocks R8A7778_CLK_PLLA>;
509 compatible = "fixed-factor-clock";
510 clocks = <&cpg_clocks R8A7778_CLK_PLLA>;
516 compatible = "fixed-factor-clock";
517 clocks = <&cpg_clocks R8A7778_CLK_PLLB>;
524 mstp0_clks: mstp0_clks@ffc80030 {
525 compatible = "renesas,r8a7778-mstp-clocks", "renesas,cpg-mstp-clocks";
526 reg = <0xffc80030 4>;
527 clocks = <&cpg_clocks R8A7778_CLK_P>,
528 <&cpg_clocks R8A7778_CLK_P>,
529 <&cpg_clocks R8A7778_CLK_P>,
530 <&cpg_clocks R8A7778_CLK_P>,
531 <&cpg_clocks R8A7778_CLK_P>,
532 <&cpg_clocks R8A7778_CLK_P>,
533 <&cpg_clocks R8A7778_CLK_P>,
534 <&cpg_clocks R8A7778_CLK_P>,
535 <&cpg_clocks R8A7778_CLK_P>,
536 <&cpg_clocks R8A7778_CLK_P>,
537 <&cpg_clocks R8A7778_CLK_P>,
538 <&cpg_clocks R8A7778_CLK_P>,
539 <&cpg_clocks R8A7778_CLK_P>,
540 <&cpg_clocks R8A7778_CLK_P>,
541 <&cpg_clocks R8A7778_CLK_P>,
542 <&cpg_clocks R8A7778_CLK_P>,
543 <&cpg_clocks R8A7778_CLK_P>,
544 <&cpg_clocks R8A7778_CLK_P>,
545 <&cpg_clocks R8A7778_CLK_S>;
548 R8A7778_CLK_I2C0 R8A7778_CLK_I2C1
549 R8A7778_CLK_I2C2 R8A7778_CLK_I2C3
550 R8A7778_CLK_SCIF0 R8A7778_CLK_SCIF1
551 R8A7778_CLK_SCIF2 R8A7778_CLK_SCIF3
552 R8A7778_CLK_SCIF4 R8A7778_CLK_SCIF5
553 R8A7778_CLK_TMU0 R8A7778_CLK_TMU1
554 R8A7778_CLK_TMU2 R8A7778_CLK_SSI0
555 R8A7778_CLK_SSI1 R8A7778_CLK_SSI2
556 R8A7778_CLK_SSI3 R8A7778_CLK_SRU
560 "i2c0", "i2c1", "i2c2", "i2c3", "scif0",
561 "scif1", "scif2", "scif3", "scif4", "scif5",
562 "tmu0", "tmu1", "tmu2", "ssi0", "ssi1",
563 "ssi2", "ssi3", "sru", "hspi";
565 mstp1_clks: mstp1_clks@ffc80034 {
566 compatible = "renesas,r8a7778-mstp-clocks", "renesas,cpg-mstp-clocks";
567 reg = <0xffc80034 4>, <0xffc80044 4>;
568 clocks = <&cpg_clocks R8A7778_CLK_P>,
569 <&cpg_clocks R8A7778_CLK_S>,
570 <&cpg_clocks R8A7778_CLK_S>,
571 <&cpg_clocks R8A7778_CLK_P>;
574 R8A7778_CLK_ETHER R8A7778_CLK_VIN0
575 R8A7778_CLK_VIN1 R8A7778_CLK_USB
578 "ether", "vin0", "vin1", "usb";
580 mstp3_clks: mstp3_clks@ffc8003c {
581 compatible = "renesas,r8a7778-mstp-clocks", "renesas,cpg-mstp-clocks";
582 reg = <0xffc8003c 4>;
584 <&cpg_clocks R8A7778_CLK_P>,
585 <&cpg_clocks R8A7778_CLK_P>,
586 <&cpg_clocks R8A7778_CLK_P>,
587 <&cpg_clocks R8A7778_CLK_P>,
588 <&cpg_clocks R8A7778_CLK_P>,
589 <&cpg_clocks R8A7778_CLK_P>,
590 <&cpg_clocks R8A7778_CLK_P>,
591 <&cpg_clocks R8A7778_CLK_P>;
594 R8A7778_CLK_MMC R8A7778_CLK_SDHI0
595 R8A7778_CLK_SDHI1 R8A7778_CLK_SDHI2
596 R8A7778_CLK_SSI4 R8A7778_CLK_SSI5
597 R8A7778_CLK_SSI6 R8A7778_CLK_SSI7
601 "mmc", "sdhi0", "sdhi1", "sdhi2", "ssi4",
602 "ssi5", "ssi6", "ssi7", "ssi8";
604 mstp5_clks: mstp5_clks@ffc80054 {
605 compatible = "renesas,r8a7778-mstp-clocks", "renesas,cpg-mstp-clocks";
606 reg = <0xffc80054 4>;
607 clocks = <&cpg_clocks R8A7778_CLK_P>,
608 <&cpg_clocks R8A7778_CLK_P>,
609 <&cpg_clocks R8A7778_CLK_P>,
610 <&cpg_clocks R8A7778_CLK_P>,
611 <&cpg_clocks R8A7778_CLK_P>,
612 <&cpg_clocks R8A7778_CLK_P>,
613 <&cpg_clocks R8A7778_CLK_P>,
614 <&cpg_clocks R8A7778_CLK_P>,
615 <&cpg_clocks R8A7778_CLK_P>;
618 R8A7778_CLK_SRU_SRC0 R8A7778_CLK_SRU_SRC1
619 R8A7778_CLK_SRU_SRC2 R8A7778_CLK_SRU_SRC3
620 R8A7778_CLK_SRU_SRC4 R8A7778_CLK_SRU_SRC5
621 R8A7778_CLK_SRU_SRC6 R8A7778_CLK_SRU_SRC7
625 "sru-src0", "sru-src1", "sru-src2",
626 "sru-src3", "sru-src4", "sru-src5",
627 "sru-src6", "sru-src7", "sru-src8";
631 rst: reset-controller@ffcc0000 {
632 compatible = "renesas,r8a7778-reset-wdt";
633 reg = <0xffcc0000 0x40>;