1 // SPDX-License-Identifier: GPL-2.0
3 * Device Tree Source for the R-Car H1 (R8A77790) SoC
5 * Copyright (C) 2013 Renesas Solutions Corp.
6 * Copyright (C) 2013 Simon Horman
9 #include <dt-bindings/clock/r8a7779-clock.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/interrupt-controller/irq.h>
12 #include <dt-bindings/power/r8a7779-sysc.h>
15 compatible = "renesas,r8a7779";
16 interrupt-parent = <&gic>;
26 compatible = "arm,cortex-a9";
28 clock-frequency = <1000000000>;
29 clocks = <&cpg_clocks R8A7779_CLK_Z>;
33 compatible = "arm,cortex-a9";
35 clock-frequency = <1000000000>;
36 clocks = <&cpg_clocks R8A7779_CLK_Z>;
37 power-domains = <&sysc R8A7779_PD_ARM1>;
41 compatible = "arm,cortex-a9";
43 clock-frequency = <1000000000>;
44 clocks = <&cpg_clocks R8A7779_CLK_Z>;
45 power-domains = <&sysc R8A7779_PD_ARM2>;
49 compatible = "arm,cortex-a9";
51 clock-frequency = <1000000000>;
52 clocks = <&cpg_clocks R8A7779_CLK_Z>;
53 power-domains = <&sysc R8A7779_PD_ARM3>;
63 gic: interrupt-controller@f0001000 {
64 compatible = "arm,cortex-a9-gic";
65 #interrupt-cells = <3>;
67 reg = <0xf0001000 0x1000>,
72 compatible = "arm,cortex-a9-twd-timer";
73 reg = <0xf0000600 0x20>;
74 interrupts = <GIC_PPI 13
75 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>;
76 clocks = <&cpg_clocks R8A7779_CLK_ZS>;
79 gpio0: gpio@ffc40000 {
80 compatible = "renesas,gpio-r8a7779", "renesas,rcar-gen1-gpio";
81 reg = <0xffc40000 0x2c>;
82 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
85 gpio-ranges = <&pfc 0 0 32>;
86 #interrupt-cells = <2>;
90 gpio1: gpio@ffc41000 {
91 compatible = "renesas,gpio-r8a7779", "renesas,rcar-gen1-gpio";
92 reg = <0xffc41000 0x2c>;
93 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
96 gpio-ranges = <&pfc 0 32 32>;
97 #interrupt-cells = <2>;
101 gpio2: gpio@ffc42000 {
102 compatible = "renesas,gpio-r8a7779", "renesas,rcar-gen1-gpio";
103 reg = <0xffc42000 0x2c>;
104 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
107 gpio-ranges = <&pfc 0 64 32>;
108 #interrupt-cells = <2>;
109 interrupt-controller;
112 gpio3: gpio@ffc43000 {
113 compatible = "renesas,gpio-r8a7779", "renesas,rcar-gen1-gpio";
114 reg = <0xffc43000 0x2c>;
115 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
118 gpio-ranges = <&pfc 0 96 32>;
119 #interrupt-cells = <2>;
120 interrupt-controller;
123 gpio4: gpio@ffc44000 {
124 compatible = "renesas,gpio-r8a7779", "renesas,rcar-gen1-gpio";
125 reg = <0xffc44000 0x2c>;
126 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
129 gpio-ranges = <&pfc 0 128 32>;
130 #interrupt-cells = <2>;
131 interrupt-controller;
134 gpio5: gpio@ffc45000 {
135 compatible = "renesas,gpio-r8a7779", "renesas,rcar-gen1-gpio";
136 reg = <0xffc45000 0x2c>;
137 interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
140 gpio-ranges = <&pfc 0 160 32>;
141 #interrupt-cells = <2>;
142 interrupt-controller;
145 gpio6: gpio@ffc46000 {
146 compatible = "renesas,gpio-r8a7779", "renesas,rcar-gen1-gpio";
147 reg = <0xffc46000 0x2c>;
148 interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
151 gpio-ranges = <&pfc 0 192 9>;
152 #interrupt-cells = <2>;
153 interrupt-controller;
156 irqpin0: interrupt-controller@fe78001c {
157 compatible = "renesas,intc-irqpin-r8a7779", "renesas,intc-irqpin";
158 #interrupt-cells = <2>;
160 interrupt-controller;
161 reg = <0xfe78001c 4>,
167 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH
168 GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH
169 GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH
170 GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
171 sense-bitfield-width = <2>;
175 #address-cells = <1>;
177 compatible = "renesas,i2c-r8a7779", "renesas,rcar-gen1-i2c";
178 reg = <0xffc70000 0x1000>;
179 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
180 clocks = <&mstp0_clks R8A7779_CLK_I2C0>;
181 power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
186 #address-cells = <1>;
188 compatible = "renesas,i2c-r8a7779", "renesas,rcar-gen1-i2c";
189 reg = <0xffc71000 0x1000>;
190 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
191 clocks = <&mstp0_clks R8A7779_CLK_I2C1>;
192 power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
197 #address-cells = <1>;
199 compatible = "renesas,i2c-r8a7779", "renesas,rcar-gen1-i2c";
200 reg = <0xffc72000 0x1000>;
201 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
202 clocks = <&mstp0_clks R8A7779_CLK_I2C2>;
203 power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
208 #address-cells = <1>;
210 compatible = "renesas,i2c-r8a7779", "renesas,rcar-gen1-i2c";
211 reg = <0xffc73000 0x1000>;
212 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
213 clocks = <&mstp0_clks R8A7779_CLK_I2C3>;
214 power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
218 scif0: serial@ffe40000 {
219 compatible = "renesas,scif-r8a7779", "renesas,rcar-gen1-scif",
221 reg = <0xffe40000 0x100>;
222 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
223 clocks = <&mstp0_clks R8A7779_CLK_SCIF0>,
224 <&cpg_clocks R8A7779_CLK_S1>, <&scif_clk>;
225 clock-names = "fck", "brg_int", "scif_clk";
226 power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
230 scif1: serial@ffe41000 {
231 compatible = "renesas,scif-r8a7779", "renesas,rcar-gen1-scif",
233 reg = <0xffe41000 0x100>;
234 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
235 clocks = <&mstp0_clks R8A7779_CLK_SCIF1>,
236 <&cpg_clocks R8A7779_CLK_S1>, <&scif_clk>;
237 clock-names = "fck", "brg_int", "scif_clk";
238 power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
242 scif2: serial@ffe42000 {
243 compatible = "renesas,scif-r8a7779", "renesas,rcar-gen1-scif",
245 reg = <0xffe42000 0x100>;
246 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
247 clocks = <&mstp0_clks R8A7779_CLK_SCIF2>,
248 <&cpg_clocks R8A7779_CLK_S1>, <&scif_clk>;
249 clock-names = "fck", "brg_int", "scif_clk";
250 power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
254 scif3: serial@ffe43000 {
255 compatible = "renesas,scif-r8a7779", "renesas,rcar-gen1-scif",
257 reg = <0xffe43000 0x100>;
258 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
259 clocks = <&mstp0_clks R8A7779_CLK_SCIF3>,
260 <&cpg_clocks R8A7779_CLK_S1>, <&scif_clk>;
261 clock-names = "fck", "brg_int", "scif_clk";
262 power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
266 scif4: serial@ffe44000 {
267 compatible = "renesas,scif-r8a7779", "renesas,rcar-gen1-scif",
269 reg = <0xffe44000 0x100>;
270 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
271 clocks = <&mstp0_clks R8A7779_CLK_SCIF4>,
272 <&cpg_clocks R8A7779_CLK_S1>, <&scif_clk>;
273 clock-names = "fck", "brg_int", "scif_clk";
274 power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
278 scif5: serial@ffe45000 {
279 compatible = "renesas,scif-r8a7779", "renesas,rcar-gen1-scif",
281 reg = <0xffe45000 0x100>;
282 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
283 clocks = <&mstp0_clks R8A7779_CLK_SCIF5>,
284 <&cpg_clocks R8A7779_CLK_S1>, <&scif_clk>;
285 clock-names = "fck", "brg_int", "scif_clk";
286 power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
290 pfc: pin-controller@fffc0000 {
291 compatible = "renesas,pfc-r8a7779";
292 reg = <0xfffc0000 0x23c>;
296 compatible = "renesas,thermal-r8a7779", "renesas,rcar-thermal";
297 reg = <0xffc48000 0x38>;
300 tmu0: timer@ffd80000 {
301 compatible = "renesas,tmu-r8a7779", "renesas,tmu";
302 reg = <0xffd80000 0x30>;
303 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
304 <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
305 <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
306 clocks = <&mstp0_clks R8A7779_CLK_TMU0>;
308 power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
310 #renesas,channels = <3>;
315 tmu1: timer@ffd81000 {
316 compatible = "renesas,tmu-r8a7779", "renesas,tmu";
317 reg = <0xffd81000 0x30>;
318 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>,
319 <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>,
320 <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
321 clocks = <&mstp0_clks R8A7779_CLK_TMU1>;
323 power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
325 #renesas,channels = <3>;
330 tmu2: timer@ffd82000 {
331 compatible = "renesas,tmu-r8a7779", "renesas,tmu";
332 reg = <0xffd82000 0x30>;
333 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
334 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
335 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
336 clocks = <&mstp0_clks R8A7779_CLK_TMU2>;
338 power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
340 #renesas,channels = <3>;
345 sata: sata@fc600000 {
346 compatible = "renesas,sata-r8a7779", "renesas,rcar-sata";
347 reg = <0xfc600000 0x200000>;
348 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
349 clocks = <&mstp1_clks R8A7779_CLK_SATA>;
350 power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
355 compatible = "renesas,sdhi-r8a7779",
356 "renesas,rcar-gen1-sdhi";
357 reg = <0xffe4c000 0x100>;
358 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
359 clocks = <&mstp3_clks R8A7779_CLK_SDHI0>;
360 power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
365 compatible = "renesas,sdhi-r8a7779",
366 "renesas,rcar-gen1-sdhi";
367 reg = <0xffe4d000 0x100>;
368 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
369 clocks = <&mstp3_clks R8A7779_CLK_SDHI1>;
370 power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
375 compatible = "renesas,sdhi-r8a7779",
376 "renesas,rcar-gen1-sdhi";
377 reg = <0xffe4e000 0x100>;
378 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
379 clocks = <&mstp3_clks R8A7779_CLK_SDHI2>;
380 power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
385 compatible = "renesas,sdhi-r8a7779",
386 "renesas,rcar-gen1-sdhi";
387 reg = <0xffe4f000 0x100>;
388 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
389 clocks = <&mstp3_clks R8A7779_CLK_SDHI3>;
390 power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
394 hspi0: spi@fffc7000 {
395 compatible = "renesas,hspi-r8a7779", "renesas,hspi";
396 reg = <0xfffc7000 0x18>;
397 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
398 #address-cells = <1>;
400 clocks = <&mstp0_clks R8A7779_CLK_HSPI>;
401 power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
405 hspi1: spi@fffc8000 {
406 compatible = "renesas,hspi-r8a7779", "renesas,hspi";
407 reg = <0xfffc8000 0x18>;
408 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
409 #address-cells = <1>;
411 clocks = <&mstp0_clks R8A7779_CLK_HSPI>;
412 power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
416 hspi2: spi@fffc6000 {
417 compatible = "renesas,hspi-r8a7779", "renesas,hspi";
418 reg = <0xfffc6000 0x18>;
419 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
420 #address-cells = <1>;
422 clocks = <&mstp0_clks R8A7779_CLK_HSPI>;
423 power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
427 du: display@fff80000 {
428 compatible = "renesas,du-r8a7779";
429 reg = <0xfff80000 0x40000>;
430 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
431 clocks = <&mstp1_clks R8A7779_CLK_DU>;
432 power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
436 #address-cells = <1>;
441 du_out_rgb0: endpoint {
446 du_out_rgb1: endpoint {
453 #address-cells = <1>;
457 /* External root clock */
459 compatible = "fixed-clock";
461 /* This value must be overriden by the board. */
462 clock-frequency = <0>;
465 /* External SCIF clock */
467 compatible = "fixed-clock";
469 /* This value must be overridden by the board. */
470 clock-frequency = <0>;
473 /* Special CPG clocks */
474 cpg_clocks: clocks@ffc80000 {
475 compatible = "renesas,r8a7779-cpg-clocks";
476 reg = <0xffc80000 0x30>;
477 clocks = <&extal_clk>;
479 clock-output-names = "plla", "z", "zs", "s",
480 "s1", "p", "b", "out";
481 #power-domain-cells = <0>;
484 /* Fixed factor clocks */
486 compatible = "fixed-factor-clock";
487 clocks = <&cpg_clocks R8A7779_CLK_PLLA>;
493 compatible = "fixed-factor-clock";
494 clocks = <&cpg_clocks R8A7779_CLK_PLLA>;
500 compatible = "fixed-factor-clock";
501 clocks = <&cpg_clocks R8A7779_CLK_PLLA>;
507 compatible = "fixed-factor-clock";
508 clocks = <&cpg_clocks R8A7779_CLK_PLLA>;
515 mstp0_clks: clocks@ffc80030 {
516 compatible = "renesas,r8a7779-mstp-clocks",
517 "renesas,cpg-mstp-clocks";
518 reg = <0xffc80030 4>;
519 clocks = <&cpg_clocks R8A7779_CLK_S>,
520 <&cpg_clocks R8A7779_CLK_P>,
521 <&cpg_clocks R8A7779_CLK_P>,
522 <&cpg_clocks R8A7779_CLK_P>,
523 <&cpg_clocks R8A7779_CLK_S>,
524 <&cpg_clocks R8A7779_CLK_S>,
525 <&cpg_clocks R8A7779_CLK_P>,
526 <&cpg_clocks R8A7779_CLK_P>,
527 <&cpg_clocks R8A7779_CLK_P>,
528 <&cpg_clocks R8A7779_CLK_P>,
529 <&cpg_clocks R8A7779_CLK_P>,
530 <&cpg_clocks R8A7779_CLK_P>,
531 <&cpg_clocks R8A7779_CLK_P>,
532 <&cpg_clocks R8A7779_CLK_P>,
533 <&cpg_clocks R8A7779_CLK_P>,
534 <&cpg_clocks R8A7779_CLK_P>;
537 R8A7779_CLK_HSPI R8A7779_CLK_TMU2
538 R8A7779_CLK_TMU1 R8A7779_CLK_TMU0
539 R8A7779_CLK_HSCIF1 R8A7779_CLK_HSCIF0
540 R8A7779_CLK_SCIF5 R8A7779_CLK_SCIF4
541 R8A7779_CLK_SCIF3 R8A7779_CLK_SCIF2
542 R8A7779_CLK_SCIF1 R8A7779_CLK_SCIF0
543 R8A7779_CLK_I2C3 R8A7779_CLK_I2C2
544 R8A7779_CLK_I2C1 R8A7779_CLK_I2C0
547 "hspi", "tmu2", "tmu1", "tmu0", "hscif1",
548 "hscif0", "scif5", "scif4", "scif3", "scif2",
549 "scif1", "scif0", "i2c3", "i2c2", "i2c1",
552 mstp1_clks: clocks@ffc80034 {
553 compatible = "renesas,r8a7779-mstp-clocks",
554 "renesas,cpg-mstp-clocks";
555 reg = <0xffc80034 4>, <0xffc80044 4>;
556 clocks = <&cpg_clocks R8A7779_CLK_P>,
557 <&cpg_clocks R8A7779_CLK_P>,
558 <&cpg_clocks R8A7779_CLK_S>,
559 <&cpg_clocks R8A7779_CLK_S>,
560 <&cpg_clocks R8A7779_CLK_S>,
561 <&cpg_clocks R8A7779_CLK_S>,
562 <&cpg_clocks R8A7779_CLK_P>,
563 <&cpg_clocks R8A7779_CLK_P>,
564 <&cpg_clocks R8A7779_CLK_P>,
565 <&cpg_clocks R8A7779_CLK_S>;
568 R8A7779_CLK_USB01 R8A7779_CLK_USB2
569 R8A7779_CLK_DU R8A7779_CLK_VIN2
570 R8A7779_CLK_VIN1 R8A7779_CLK_VIN0
571 R8A7779_CLK_ETHER R8A7779_CLK_SATA
572 R8A7779_CLK_PCIE R8A7779_CLK_VIN3
581 mstp3_clks: clocks@ffc8003c {
582 compatible = "renesas,r8a7779-mstp-clocks",
583 "renesas,cpg-mstp-clocks";
584 reg = <0xffc8003c 4>;
585 clocks = <&s4_clk>, <&s4_clk>, <&s4_clk>, <&s4_clk>,
586 <&s4_clk>, <&s4_clk>;
589 R8A7779_CLK_SDHI3 R8A7779_CLK_SDHI2
590 R8A7779_CLK_SDHI1 R8A7779_CLK_SDHI0
591 R8A7779_CLK_MMC1 R8A7779_CLK_MMC0
594 "sdhi3", "sdhi2", "sdhi1", "sdhi0",
599 prr: chipid@ff000044 {
600 compatible = "renesas,prr";
601 reg = <0xff000044 4>;
604 rst: reset-controller@ffcc0000 {
605 compatible = "renesas,r8a7779-reset-wdt";
606 reg = <0xffcc0000 0x48>;
609 sysc: system-controller@ffd85000 {
610 compatible = "renesas,r8a7779-sysc";
611 reg = <0xffd85000 0x0200>;
612 #power-domain-cells = <1>;