sys/gnu/dts/arm/r8a7794.dtsi

   1 /*
   2  * Device Tree Source for the r8a7794 SoC
   3  *
   4  * Copyright (C) 2014 Renesas Electronics Corporation
   5  * Copyright (C) 2014 Ulrich Hecht
   6  *
   7  * This file is licensed under the terms of the GNU General Public License
   8  * version 2.  This program is licensed "as is" without any warranty of any
   9  * kind, whether express or implied.
  10  */
  11
  12 #include <dt-bindings/clock/r8a7794-clock.h>
  13 #include <dt-bindings/interrupt-controller/arm-gic.h>
  14 #include <dt-bindings/interrupt-controller/irq.h>
  15 #include <dt-bindings/power/r8a7794-sysc.h>
  16
  17 / {
  18         compatible = "renesas,r8a7794";
  19         interrupt-parent = <&gic>;
  20         #address-cells = <2>;
  21         #size-cells = <2>;
  22
  23         aliases {
  24                 i2c0 = &i2c0;
  25                 i2c1 = &i2c1;
  26                 i2c2 = &i2c2;
  27                 i2c3 = &i2c3;
  28                 i2c4 = &i2c4;
  29                 i2c5 = &i2c5;
  30                 i2c6 = &i2c6;
  31                 i2c7 = &i2c7;
  32                 spi0 = &qspi;
  33                 vin0 = &vin0;
  34                 vin1 = &vin1;
  35         };
  36
  37         cpus {
  38                 #address-cells = <1>;
  39                 #size-cells = <0>;
  40
  41                 cpu0: cpu@0 {
  42                         device_type = "cpu";
  43                         compatible = "arm,cortex-a7";
  44                         reg = <0>;
  45                         clock-frequency = <1000000000>;
  46                         power-domains = <&sysc R8A7794_PD_CA7_CPU0>;
  47                         next-level-cache = <&L2_CA7>;
  48                 };
  49
  50                 cpu1: cpu@1 {
  51                         device_type = "cpu";
  52                         compatible = "arm,cortex-a7";
  53                         reg = <1>;
  54                         clock-frequency = <1000000000>;
  55                         power-domains = <&sysc R8A7794_PD_CA7_CPU1>;
  56                         next-level-cache = <&L2_CA7>;
  57                 };
  58
  59                 L2_CA7: cache-controller@0 {
  60                         compatible = "cache";
  61                         reg = <0>;
  62                         power-domains = <&sysc R8A7794_PD_CA7_SCU>;
  63                         cache-unified;
  64                         cache-level = <2>;
  65                 };
  66         };
  67
  68         gic: interrupt-controller@f1001000 {
  69                 compatible = "arm,gic-400";
  70                 #interrupt-cells = <3>;
  71                 #address-cells = <0>;
  72                 interrupt-controller;
  73                 reg = <0 0xf1001000 0 0x1000>,
  74                         <0 0xf1002000 0 0x2000>,
  75                         <0 0xf1004000 0 0x2000>,
  76                         <0 0xf1006000 0 0x2000>;
  77                 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
  78         };
  79
  80         gpio0: gpio@e6050000 {
  81                 compatible = "renesas,gpio-r8a7794", "renesas,gpio-rcar";
  82                 reg = <0 0xe6050000 0 0x50>;
  83                 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
  84                 #gpio-cells = <2>;
  85                 gpio-controller;
  86                 gpio-ranges = <&pfc 0 0 32>;
  87                 #interrupt-cells = <2>;
  88                 interrupt-controller;
  89                 clocks = <&mstp9_clks R8A7794_CLK_GPIO0>;
  90                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
  91         };
  92
  93         gpio1: gpio@e6051000 {
  94                 compatible = "renesas,gpio-r8a7794", "renesas,gpio-rcar";
  95                 reg = <0 0xe6051000 0 0x50>;
  96                 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
  97                 #gpio-cells = <2>;
  98                 gpio-controller;
  99                 gpio-ranges = <&pfc 0 32 26>;
 100                 #interrupt-cells = <2>;
 101                 interrupt-controller;
 102                 clocks = <&mstp9_clks R8A7794_CLK_GPIO1>;
 103                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 104         };
 105
 106         gpio2: gpio@e6052000 {
 107                 compatible = "renesas,gpio-r8a7794", "renesas,gpio-rcar";
 108                 reg = <0 0xe6052000 0 0x50>;
 109                 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
 110                 #gpio-cells = <2>;
 111                 gpio-controller;
 112                 gpio-ranges = <&pfc 0 64 32>;
 113                 #interrupt-cells = <2>;
 114                 interrupt-controller;
 115                 clocks = <&mstp9_clks R8A7794_CLK_GPIO2>;
 116                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 117         };
 118
 119         gpio3: gpio@e6053000 {
 120                 compatible = "renesas,gpio-r8a7794", "renesas,gpio-rcar";
 121                 reg = <0 0xe6053000 0 0x50>;
 122                 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
 123                 #gpio-cells = <2>;
 124                 gpio-controller;
 125                 gpio-ranges = <&pfc 0 96 32>;
 126                 #interrupt-cells = <2>;
 127                 interrupt-controller;
 128                 clocks = <&mstp9_clks R8A7794_CLK_GPIO3>;
 129                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 130         };
 131
 132         gpio4: gpio@e6054000 {
 133                 compatible = "renesas,gpio-r8a7794", "renesas,gpio-rcar";
 134                 reg = <0 0xe6054000 0 0x50>;
 135                 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
 136                 #gpio-cells = <2>;
 137                 gpio-controller;
 138                 gpio-ranges = <&pfc 0 128 32>;
 139                 #interrupt-cells = <2>;
 140                 interrupt-controller;
 141                 clocks = <&mstp9_clks R8A7794_CLK_GPIO4>;
 142                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 143         };
 144
 145         gpio5: gpio@e6055000 {
 146                 compatible = "renesas,gpio-r8a7794", "renesas,gpio-rcar";
 147                 reg = <0 0xe6055000 0 0x50>;
 148                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
 149                 #gpio-cells = <2>;
 150                 gpio-controller;
 151                 gpio-ranges = <&pfc 0 160 28>;
 152                 #interrupt-cells = <2>;
 153                 interrupt-controller;
 154                 clocks = <&mstp9_clks R8A7794_CLK_GPIO5>;
 155                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 156         };
 157
 158         gpio6: gpio@e6055400 {
 159                 compatible = "renesas,gpio-r8a7794", "renesas,gpio-rcar";
 160                 reg = <0 0xe6055400 0 0x50>;
 161                 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 162                 #gpio-cells = <2>;
 163                 gpio-controller;
 164                 gpio-ranges = <&pfc 0 192 26>;
 165                 #interrupt-cells = <2>;
 166                 interrupt-controller;
 167                 clocks = <&mstp9_clks R8A7794_CLK_GPIO6>;
 168                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 169         };
 170
 171         cmt0: timer@ffca0000 {
 172                 compatible = "renesas,cmt-48-gen2";
 173                 reg = <0 0xffca0000 0 0x1004>;
 174                 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
 175                              <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
 176                 clocks = <&mstp1_clks R8A7794_CLK_CMT0>;
 177                 clock-names = "fck";
 178                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 179
 180                 renesas,channels-mask = <0x60>;
 181
 182                 status = "disabled";
 183         };
 184
 185         cmt1: timer@e6130000 {
 186                 compatible = "renesas,cmt-48-gen2";
 187                 reg = <0 0xe6130000 0 0x1004>;
 188                 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
 189                              <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
 190                              <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
 191                              <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
 192                              <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
 193                              <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
 194                              <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
 195                              <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
 196                 clocks = <&mstp3_clks R8A7794_CLK_CMT1>;
 197                 clock-names = "fck";
 198                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 199
 200                 renesas,channels-mask = <0xff>;
 201
 202                 status = "disabled";
 203         };
 204
 205         timer {
 206                 compatible = "arm,armv7-timer";
 207                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
 208                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
 209                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
 210                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
 211         };
 212
 213         irqc0: interrupt-controller@e61c0000 {
 214                 compatible = "renesas,irqc-r8a7794", "renesas,irqc";
 215                 #interrupt-cells = <2>;
 216                 interrupt-controller;
 217                 reg = <0 0xe61c0000 0 0x200>;
 218                 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 219                              <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
 220                              <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
 221                              <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
 222                              <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
 223                              <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
 224                              <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
 225                              <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
 226                              <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
 227                              <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
 228                 clocks = <&mstp4_clks R8A7794_CLK_IRQC>;
 229                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 230         };
 231
 232         pfc: pin-controller@e6060000 {
 233                 compatible = "renesas,pfc-r8a7794";
 234                 reg = <0 0xe6060000 0 0x11c>;
 235         };
 236
 237         dmac0: dma-controller@e6700000 {
 238                 compatible = "renesas,dmac-r8a7794", "renesas,rcar-dmac";
 239                 reg = <0 0xe6700000 0 0x20000>;
 240                 interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH
 241                               GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH
 242                               GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH
 243                               GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH
 244                               GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH
 245                               GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH
 246                               GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH
 247                               GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH
 248                               GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH
 249                               GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH
 250                               GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH
 251                               GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH
 252                               GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH
 253                               GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH
 254                               GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH
 255                               GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>;
 256                 interrupt-names = "error",
 257                                 "ch0", "ch1", "ch2", "ch3",
 258                                 "ch4", "ch5", "ch6", "ch7",
 259                                 "ch8", "ch9", "ch10", "ch11",
 260                                 "ch12", "ch13", "ch14";
 261                 clocks = <&mstp2_clks R8A7794_CLK_SYS_DMAC0>;
 262                 clock-names = "fck";
 263                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 264                 #dma-cells = <1>;
 265                 dma-channels = <15>;
 266         };
 267
 268         dmac1: dma-controller@e6720000 {
 269                 compatible = "renesas,dmac-r8a7794", "renesas,rcar-dmac";
 270                 reg = <0 0xe6720000 0 0x20000>;
 271                 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH
 272                               GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH
 273                               GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH
 274                               GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH
 275                               GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH
 276                               GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH
 277                               GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH
 278                               GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH
 279                               GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH
 280                               GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH
 281                               GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH
 282                               GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH
 283                               GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH
 284                               GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH
 285                               GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH
 286                               GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>;
 287                 interrupt-names = "error",
 288                                 "ch0", "ch1", "ch2", "ch3",
 289                                 "ch4", "ch5", "ch6", "ch7",
 290                                 "ch8", "ch9", "ch10", "ch11",
 291                                 "ch12", "ch13", "ch14";
 292                 clocks = <&mstp2_clks R8A7794_CLK_SYS_DMAC1>;
 293                 clock-names = "fck";
 294                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 295                 #dma-cells = <1>;
 296                 dma-channels = <15>;
 297         };
 298
 299         audma0: dma-controller@ec700000 {
 300                 compatible = "renesas,dmac-r8a7794", "renesas,rcar-dmac";
 301                 reg = <0 0xec700000 0 0x10000>;
 302                 interrupts =    <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH
 303                                  GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH
 304                                  GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH
 305                                  GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH
 306                                  GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH
 307                                  GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH
 308                                  GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH
 309                                  GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH
 310                                  GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH
 311                                  GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH
 312                                  GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH
 313                                  GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH
 314                                  GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH
 315                                  GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>;
 316                 interrupt-names = "error",
 317                                   "ch0", "ch1", "ch2", "ch3", "ch4", "ch5",
 318                                   "ch6", "ch7", "ch8", "ch9", "ch10", "ch11",
 319                                   "ch12";
 320                 clocks = <&mstp5_clks R8A7794_CLK_AUDIO_DMAC0>;
 321                 clock-names = "fck";
 322                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 323                 #dma-cells = <1>;
 324                 dma-channels = <13>;
 325         };
 326
 327         scifa0: serial@e6c40000 {
 328                 compatible = "renesas,scifa-r8a7794",
 329                              "renesas,rcar-gen2-scifa", "renesas,scifa";
 330                 reg = <0 0xe6c40000 0 64>;
 331                 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
 332                 clocks = <&mstp2_clks R8A7794_CLK_SCIFA0>;
 333                 clock-names = "fck";
 334                 dmas = <&dmac0 0x21>, <&dmac0 0x22>,
 335                        <&dmac1 0x21>, <&dmac1 0x22>;
 336                 dma-names = "tx", "rx", "tx", "rx";
 337                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 338                 status = "disabled";
 339         };
 340
 341         scifa1: serial@e6c50000 {
 342                 compatible = "renesas,scifa-r8a7794",
 343                              "renesas,rcar-gen2-scifa", "renesas,scifa";
 344                 reg = <0 0xe6c50000 0 64>;
 345                 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
 346                 clocks = <&mstp2_clks R8A7794_CLK_SCIFA1>;
 347                 clock-names = "fck";
 348                 dmas = <&dmac0 0x25>, <&dmac0 0x26>,
 349                        <&dmac1 0x25>, <&dmac1 0x26>;
 350                 dma-names = "tx", "rx", "tx", "rx";
 351                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 352                 status = "disabled";
 353         };
 354
 355         scifa2: serial@e6c60000 {
 356                 compatible = "renesas,scifa-r8a7794",
 357                              "renesas,rcar-gen2-scifa", "renesas,scifa";
 358                 reg = <0 0xe6c60000 0 64>;
 359                 interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;
 360                 clocks = <&mstp2_clks R8A7794_CLK_SCIFA2>;
 361                 clock-names = "fck";
 362                 dmas = <&dmac0 0x27>, <&dmac0 0x28>,
 363                        <&dmac1 0x27>, <&dmac1 0x28>;
 364                 dma-names = "tx", "rx", "tx", "rx";
 365                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 366                 status = "disabled";
 367         };
 368
 369         scifa3: serial@e6c70000 {
 370                 compatible = "renesas,scifa-r8a7794",
 371                              "renesas,rcar-gen2-scifa", "renesas,scifa";
 372                 reg = <0 0xe6c70000 0 64>;
 373                 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
 374                 clocks = <&mstp11_clks R8A7794_CLK_SCIFA3>;
 375                 clock-names = "fck";
 376                 dmas = <&dmac0 0x1b>, <&dmac0 0x1c>,
 377                        <&dmac1 0x1b>, <&dmac1 0x1c>;
 378                 dma-names = "tx", "rx", "tx", "rx";
 379                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 380                 status = "disabled";
 381         };
 382
 383         scifa4: serial@e6c78000 {
 384                 compatible = "renesas,scifa-r8a7794",
 385                              "renesas,rcar-gen2-scifa", "renesas,scifa";
 386                 reg = <0 0xe6c78000 0 64>;
 387                 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
 388                 clocks = <&mstp11_clks R8A7794_CLK_SCIFA4>;
 389                 clock-names = "fck";
 390                 dmas = <&dmac0 0x1f>, <&dmac0 0x20>,
 391                        <&dmac1 0x1f>, <&dmac1 0x20>;
 392                 dma-names = "tx", "rx", "tx", "rx";
 393                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 394                 status = "disabled";
 395         };
 396
 397         scifa5: serial@e6c80000 {
 398                 compatible = "renesas,scifa-r8a7794",
 399                              "renesas,rcar-gen2-scifa", "renesas,scifa";
 400                 reg = <0 0xe6c80000 0 64>;
 401                 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
 402                 clocks = <&mstp11_clks R8A7794_CLK_SCIFA5>;
 403                 clock-names = "fck";
 404                 dmas = <&dmac0 0x23>, <&dmac0 0x24>,
 405                        <&dmac1 0x23>, <&dmac1 0x24>;
 406                 dma-names = "tx", "rx", "tx", "rx";
 407                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 408                 status = "disabled";
 409         };
 410
 411         scifb0: serial@e6c20000 {
 412                 compatible = "renesas,scifb-r8a7794",
 413                              "renesas,rcar-gen2-scifb", "renesas,scifb";
 414                 reg = <0 0xe6c20000 0 0x100>;
 415                 interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
 416                 clocks = <&mstp2_clks R8A7794_CLK_SCIFB0>;
 417                 clock-names = "fck";
 418                 dmas = <&dmac0 0x3d>, <&dmac0 0x3e>,
 419                        <&dmac1 0x3d>, <&dmac1 0x3e>;
 420                 dma-names = "tx", "rx", "tx", "rx";
 421                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 422                 status = "disabled";
 423         };
 424
 425         scifb1: serial@e6c30000 {
 426                 compatible = "renesas,scifb-r8a7794",
 427                              "renesas,rcar-gen2-scifb", "renesas,scifb";
 428                 reg = <0 0xe6c30000 0 0x100>;
 429                 interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
 430                 clocks = <&mstp2_clks R8A7794_CLK_SCIFB1>;
 431                 clock-names = "fck";
 432                 dmas = <&dmac0 0x19>, <&dmac0 0x1a>,
 433                        <&dmac1 0x19>, <&dmac1 0x1a>;
 434                 dma-names = "tx", "rx", "tx", "rx";
 435                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 436                 status = "disabled";
 437         };
 438
 439         scifb2: serial@e6ce0000 {
 440                 compatible = "renesas,scifb-r8a7794",
 441                              "renesas,rcar-gen2-scifb", "renesas,scifb";
 442                 reg = <0 0xe6ce0000 0 0x100>;
 443                 interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
 444                 clocks = <&mstp2_clks R8A7794_CLK_SCIFB2>;
 445                 clock-names = "fck";
 446                 dmas = <&dmac0 0x1d>, <&dmac0 0x1e>,
 447                        <&dmac1 0x1d>, <&dmac1 0x1e>;
 448                 dma-names = "tx", "rx", "tx", "rx";
 449                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 450                 status = "disabled";
 451         };
 452
 453         scif0: serial@e6e60000 {
 454                 compatible = "renesas,scif-r8a7794", "renesas,rcar-gen2-scif",
 455                              "renesas,scif";
 456                 reg = <0 0xe6e60000 0 64>;
 457                 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
 458                 clocks = <&mstp7_clks R8A7794_CLK_SCIF0>, <&zs_clk>,
 459                          <&scif_clk>;
 460                 clock-names = "fck", "brg_int", "scif_clk";
 461                 dmas = <&dmac0 0x29>, <&dmac0 0x2a>,
 462                        <&dmac1 0x29>, <&dmac1 0x2a>;
 463                 dma-names = "tx", "rx", "tx", "rx";
 464                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 465                 status = "disabled";
 466         };
 467
 468         scif1: serial@e6e68000 {
 469                 compatible = "renesas,scif-r8a7794", "renesas,rcar-gen2-scif",
 470                              "renesas,scif";
 471                 reg = <0 0xe6e68000 0 64>;
 472                 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
 473                 clocks = <&mstp7_clks R8A7794_CLK_SCIF1>, <&zs_clk>,
 474                          <&scif_clk>;
 475                 clock-names = "fck", "brg_int", "scif_clk";
 476                 dmas = <&dmac0 0x2d>, <&dmac0 0x2e>,
 477                        <&dmac1 0x2d>, <&dmac1 0x2e>;
 478                 dma-names = "tx", "rx", "tx", "rx";
 479                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 480                 status = "disabled";
 481         };
 482
 483         scif2: serial@e6e58000 {
 484                 compatible = "renesas,scif-r8a7794", "renesas,rcar-gen2-scif",
 485                              "renesas,scif";
 486                 reg = <0 0xe6e58000 0 64>;
 487                 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
 488                 clocks = <&mstp7_clks R8A7794_CLK_SCIF2>, <&zs_clk>,
 489                          <&scif_clk>;
 490                 clock-names = "fck", "brg_int", "scif_clk";
 491                 dmas = <&dmac0 0x2b>, <&dmac0 0x2c>,
 492                        <&dmac1 0x2b>, <&dmac1 0x2c>;
 493                 dma-names = "tx", "rx", "tx", "rx";
 494                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 495                 status = "disabled";
 496         };
 497
 498         scif3: serial@e6ea8000 {
 499                 compatible = "renesas,scif-r8a7794", "renesas,rcar-gen2-scif",
 500                              "renesas,scif";
 501                 reg = <0 0xe6ea8000 0 64>;
 502                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 503                 clocks = <&mstp7_clks R8A7794_CLK_SCIF3>, <&zs_clk>,
 504                          <&scif_clk>;
 505                 clock-names = "fck", "brg_int", "scif_clk";
 506                 dmas = <&dmac0 0x2f>, <&dmac0 0x30>,
 507                        <&dmac1 0x2f>, <&dmac1 0x30>;
 508                 dma-names = "tx", "rx", "tx", "rx";
 509                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 510                 status = "disabled";
 511         };
 512
 513         scif4: serial@e6ee0000 {
 514                 compatible = "renesas,scif-r8a7794", "renesas,rcar-gen2-scif",
 515                              "renesas,scif";
 516                 reg = <0 0xe6ee0000 0 64>;
 517                 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
 518                 clocks = <&mstp7_clks R8A7794_CLK_SCIF4>, <&zs_clk>,
 519                          <&scif_clk>;
 520                 clock-names = "fck", "brg_int", "scif_clk";
 521                 dmas = <&dmac0 0xfb>, <&dmac0 0xfc>,
 522                        <&dmac1 0xfb>, <&dmac1 0xfc>;
 523                 dma-names = "tx", "rx", "tx", "rx";
 524                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 525                 status = "disabled";
 526         };
 527
 528         scif5: serial@e6ee8000 {
 529                 compatible = "renesas,scif-r8a7794", "renesas,rcar-gen2-scif",
 530                              "renesas,scif";
 531                 reg = <0 0xe6ee8000 0 64>;
 532                 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
 533                 clocks = <&mstp7_clks R8A7794_CLK_SCIF5>, <&zs_clk>,
 534                          <&scif_clk>;
 535                 clock-names = "fck", "brg_int", "scif_clk";
 536                 dmas = <&dmac0 0xfd>, <&dmac0 0xfe>,
 537                        <&dmac1 0xfd>, <&dmac1 0xfe>;
 538                 dma-names = "tx", "rx", "tx", "rx";
 539                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 540                 status = "disabled";
 541         };
 542
 543         hscif0: serial@e62c0000 {
 544                 compatible = "renesas,hscif-r8a7794",
 545                              "renesas,rcar-gen2-hscif", "renesas,hscif";
 546                 reg = <0 0xe62c0000 0 96>;
 547                 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
 548                 clocks = <&mstp7_clks R8A7794_CLK_HSCIF0>, <&zs_clk>,
 549                          <&scif_clk>;
 550                 clock-names = "fck", "brg_int", "scif_clk";
 551                 dmas = <&dmac0 0x39>, <&dmac0 0x3a>,
 552                        <&dmac1 0x39>, <&dmac1 0x3a>;
 553                 dma-names = "tx", "rx", "tx", "rx";
 554                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 555                 status = "disabled";
 556         };
 557
 558         hscif1: serial@e62c8000 {
 559                 compatible = "renesas,hscif-r8a7794",
 560                              "renesas,rcar-gen2-hscif", "renesas,hscif";
 561                 reg = <0 0xe62c8000 0 96>;
 562                 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
 563                 clocks = <&mstp7_clks R8A7794_CLK_HSCIF1>, <&zs_clk>,
 564                          <&scif_clk>;
 565                 clock-names = "fck", "brg_int", "scif_clk";
 566                 dmas = <&dmac0 0x4d>, <&dmac0 0x4e>,
 567                        <&dmac1 0x4d>, <&dmac1 0x4e>;
 568                 dma-names = "tx", "rx", "tx", "rx";
 569                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 570                 status = "disabled";
 571         };
 572
 573         hscif2: serial@e62d0000 {
 574                 compatible = "renesas,hscif-r8a7794",
 575                              "renesas,rcar-gen2-hscif", "renesas,hscif";
 576                 reg = <0 0xe62d0000 0 96>;
 577                 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
 578                 clocks = <&mstp7_clks R8A7794_CLK_HSCIF2>, <&zs_clk>,
 579                          <&scif_clk>;
 580                 clock-names = "fck", "brg_int", "scif_clk";
 581                 dmas = <&dmac0 0x3b>, <&dmac0 0x3c>,
 582                        <&dmac1 0x3b>, <&dmac1 0x3c>;
 583                 dma-names = "tx", "rx", "tx", "rx";
 584                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 585                 status = "disabled";
 586         };
 587
 588         ether: ethernet@ee700000 {
 589                 compatible = "renesas,ether-r8a7794";
 590                 reg = <0 0xee700000 0 0x400>;
 591                 interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
 592                 clocks = <&mstp8_clks R8A7794_CLK_ETHER>;
 593                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 594                 phy-mode = "rmii";
 595                 #address-cells = <1>;
 596                 #size-cells = <0>;
 597                 status = "disabled";
 598         };
 599
 600         avb: ethernet@e6800000 {
 601                 compatible = "renesas,etheravb-r8a7794",
 602                              "renesas,etheravb-rcar-gen2";
 603                 reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>;
 604                 interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
 605                 clocks = <&mstp8_clks R8A7794_CLK_ETHERAVB>;
 606                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 607                 #address-cells = <1>;
 608                 #size-cells = <0>;
 609                 status = "disabled";
 610         };
 611
 612         /* The memory map in the User's Manual maps the cores to bus numbers */
 613         i2c0: i2c@e6508000 {
 614                 compatible = "renesas,i2c-r8a7794", "renesas,rcar-gen2-i2c";
 615                 reg = <0 0xe6508000 0 0x40>;
 616                 interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
 617                 clocks = <&mstp9_clks R8A7794_CLK_I2C0>;
 618                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 619                 #address-cells = <1>;
 620                 #size-cells = <0>;
 621                 i2c-scl-internal-delay-ns = <6>;
 622                 status = "disabled";
 623         };
 624
 625         i2c1: i2c@e6518000 {
 626                 compatible = "renesas,i2c-r8a7794", "renesas,rcar-gen2-i2c";
 627                 reg = <0 0xe6518000 0 0x40>;
 628                 interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
 629                 clocks = <&mstp9_clks R8A7794_CLK_I2C1>;
 630                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 631                 #address-cells = <1>;
 632                 #size-cells = <0>;
 633                 i2c-scl-internal-delay-ns = <6>;
 634                 status = "disabled";
 635         };
 636
 637         i2c2: i2c@e6530000 {
 638                 compatible = "renesas,i2c-r8a7794", "renesas,rcar-gen2-i2c";
 639                 reg = <0 0xe6530000 0 0x40>;
 640                 interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
 641                 clocks = <&mstp9_clks R8A7794_CLK_I2C2>;
 642                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 643                 #address-cells = <1>;
 644                 #size-cells = <0>;
 645                 i2c-scl-internal-delay-ns = <6>;
 646                 status = "disabled";
 647         };
 648
 649         i2c3: i2c@e6540000 {
 650                 compatible = "renesas,i2c-r8a7794", "renesas,rcar-gen2-i2c";
 651                 reg = <0 0xe6540000 0 0x40>;
 652                 interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
 653                 clocks = <&mstp9_clks R8A7794_CLK_I2C3>;
 654                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 655                 #address-cells = <1>;
 656                 #size-cells = <0>;
 657                 i2c-scl-internal-delay-ns = <6>;
 658                 status = "disabled";
 659         };
 660
 661         i2c4: i2c@e6520000 {
 662                 compatible = "renesas,i2c-r8a7794", "renesas,rcar-gen2-i2c";
 663                 reg = <0 0xe6520000 0 0x40>;
 664                 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
 665                 clocks = <&mstp9_clks R8A7794_CLK_I2C4>;
 666                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 667                 #address-cells = <1>;
 668                 #size-cells = <0>;
 669                 i2c-scl-internal-delay-ns = <6>;
 670                 status = "disabled";
 671         };
 672
 673         i2c5: i2c@e6528000 {
 674                 compatible = "renesas,i2c-r8a7794", "renesas,rcar-gen2-i2c";
 675                 reg = <0 0xe6528000 0 0x40>;
 676                 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
 677                 clocks = <&mstp9_clks R8A7794_CLK_I2C5>;
 678                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 679                 #address-cells = <1>;
 680                 #size-cells = <0>;
 681                 i2c-scl-internal-delay-ns = <6>;
 682                 status = "disabled";
 683         };
 684
 685         i2c6: i2c@e6500000 {
 686                 compatible = "renesas,iic-r8a7794", "renesas,rcar-gen2-iic",
 687                              "renesas,rmobile-iic";
 688                 reg = <0 0xe6500000 0 0x425>;
 689                 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
 690                 clocks = <&mstp3_clks R8A7794_CLK_IIC0>;
 691                 dmas = <&dmac0 0x61>, <&dmac0 0x62>,
 692                        <&dmac1 0x61>, <&dmac1 0x62>;
 693                 dma-names = "tx", "rx", "tx", "rx";
 694                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 695                 #address-cells = <1>;
 696                 #size-cells = <0>;
 697                 status = "disabled";
 698         };
 699
 700         i2c7: i2c@e6510000 {
 701                 compatible = "renesas,iic-r8a7794", "renesas,rcar-gen2-iic",
 702                              "renesas,rmobile-iic";
 703                 reg = <0 0xe6510000 0 0x425>;
 704                 interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>;
 705                 clocks = <&mstp3_clks R8A7794_CLK_IIC1>;
 706                 dmas = <&dmac0 0x65>, <&dmac0 0x66>,
 707                        <&dmac1 0x65>, <&dmac1 0x66>;
 708                 dma-names = "tx", "rx", "tx", "rx";
 709                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 710                 #address-cells = <1>;
 711                 #size-cells = <0>;
 712                 status = "disabled";
 713         };
 714
 715         mmcif0: mmc@ee200000 {
 716                 compatible = "renesas,mmcif-r8a7794", "renesas,sh-mmcif";
 717                 reg = <0 0xee200000 0 0x80>;
 718                 interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
 719                 clocks = <&mstp3_clks R8A7794_CLK_MMCIF0>;
 720                 dmas = <&dmac0 0xd1>, <&dmac0 0xd2>,
 721                        <&dmac1 0xd1>, <&dmac1 0xd2>;
 722                 dma-names = "tx", "rx", "tx", "rx";
 723                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 724                 reg-io-width = <4>;
 725                 status = "disabled";
 726         };
 727
 728         sdhi0: sd@ee100000 {
 729                 compatible = "renesas,sdhi-r8a7794";
 730                 reg = <0 0xee100000 0 0x328>;
 731                 interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
 732                 clocks = <&mstp3_clks R8A7794_CLK_SDHI0>;
 733                 dmas = <&dmac0 0xcd>, <&dmac0 0xce>,
 734                        <&dmac1 0xcd>, <&dmac1 0xce>;
 735                 dma-names = "tx", "rx", "tx", "rx";
 736                 max-frequency = <195000000>;
 737                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 738                 status = "disabled";
 739         };
 740
 741         sdhi1: sd@ee140000 {
 742                 compatible = "renesas,sdhi-r8a7794";
 743                 reg = <0 0xee140000 0 0x100>;
 744                 interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
 745                 clocks = <&mstp3_clks R8A7794_CLK_SDHI1>;
 746                 dmas = <&dmac0 0xc1>, <&dmac0 0xc2>,
 747                        <&dmac1 0xc1>, <&dmac1 0xc2>;
 748                 dma-names = "tx", "rx", "tx", "rx";
 749                 max-frequency = <97500000>;
 750                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 751                 status = "disabled";
 752         };
 753
 754         sdhi2: sd@ee160000 {
 755                 compatible = "renesas,sdhi-r8a7794";
 756                 reg = <0 0xee160000 0 0x100>;
 757                 interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
 758                 clocks = <&mstp3_clks R8A7794_CLK_SDHI2>;
 759                 dmas = <&dmac0 0xd3>, <&dmac0 0xd4>,
 760                        <&dmac1 0xd3>, <&dmac1 0xd4>;
 761                 dma-names = "tx", "rx", "tx", "rx";
 762                 max-frequency = <97500000>;
 763                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 764                 status = "disabled";
 765         };
 766
 767         qspi: spi@e6b10000 {
 768                 compatible = "renesas,qspi-r8a7794", "renesas,qspi";
 769                 reg = <0 0xe6b10000 0 0x2c>;
 770                 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
 771                 clocks = <&mstp9_clks R8A7794_CLK_QSPI_MOD>;
 772                 dmas = <&dmac0 0x17>, <&dmac0 0x18>,
 773                        <&dmac1 0x17>, <&dmac1 0x18>;
 774                 dma-names = "tx", "rx", "tx", "rx";
 775                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 776                 num-cs = <1>;
 777                 #address-cells = <1>;
 778                 #size-cells = <0>;
 779                 status = "disabled";
 780         };
 781
 782         vin0: video@e6ef0000 {
 783                 compatible = "renesas,vin-r8a7794";
 784                 reg = <0 0xe6ef0000 0 0x1000>;
 785                 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
 786                 clocks = <&mstp8_clks R8A7794_CLK_VIN0>;
 787                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 788                 status = "disabled";
 789         };
 790
 791         vin1: video@e6ef1000 {
 792                 compatible = "renesas,vin-r8a7794";
 793                 reg = <0 0xe6ef1000 0 0x1000>;
 794                 interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
 795                 clocks = <&mstp8_clks R8A7794_CLK_VIN1>;
 796                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 797                 status = "disabled";
 798         };
 799
 800         pci0: pci@ee090000 {
 801                 compatible = "renesas,pci-r8a7794", "renesas,pci-rcar-gen2";
 802                 device_type = "pci";
 803                 reg = <0 0xee090000 0 0xc00>,
 804                       <0 0xee080000 0 0x1100>;
 805                 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
 806                 clocks = <&mstp7_clks R8A7794_CLK_EHCI>;
 807                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 808                 status = "disabled";
 809
 810                 bus-range = <0 0>;
 811                 #address-cells = <3>;
 812                 #size-cells = <2>;
 813                 #interrupt-cells = <1>;
 814                 ranges = <0x02000000 0 0xee080000 0 0xee080000 0 0x00010000>;
 815                 interrupt-map-mask = <0xff00 0 0 0x7>;
 816                 interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH
 817                                  0x0800 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH
 818                                  0x1000 0 0 2 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
 819
 820                 usb@0,1 {
 821                         reg = <0x800 0 0 0 0>;
 822                         device_type = "pci";
 823                         phys = <&usb0 0>;
 824                         phy-names = "usb";
 825                 };
 826
 827                 usb@0,2 {
 828                         reg = <0x1000 0 0 0 0>;
 829                         device_type = "pci";
 830                         phys = <&usb0 0>;
 831                         phy-names = "usb";
 832                 };
 833         };
 834
 835         pci1: pci@ee0d0000 {
 836                 compatible = "renesas,pci-r8a7794", "renesas,pci-rcar-gen2";
 837                 device_type = "pci";
 838                 reg = <0 0xee0d0000 0 0xc00>,
 839                       <0 0xee0c0000 0 0x1100>;
 840                 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
 841                 clocks = <&mstp7_clks R8A7794_CLK_EHCI>;
 842                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 843                 status = "disabled";
 844
 845                 bus-range = <1 1>;
 846                 #address-cells = <3>;
 847                 #size-cells = <2>;
 848                 #interrupt-cells = <1>;
 849                 ranges = <0x02000000 0 0xee0c0000 0 0xee0c0000 0 0x00010000>;
 850                 interrupt-map-mask = <0xff00 0 0 0x7>;
 851                 interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH
 852                                  0x0800 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH
 853                                  0x1000 0 0 2 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
 854
 855                 usb@0,1 {
 856                         reg = <0x800 0 0 0 0>;
 857                         device_type = "pci";
 858                         phys = <&usb2 0>;
 859                         phy-names = "usb";
 860                 };
 861
 862                 usb@0,2 {
 863                         reg = <0x1000 0 0 0 0>;
 864                         device_type = "pci";
 865                         phys = <&usb2 0>;
 866                         phy-names = "usb";
 867                 };
 868         };
 869
 870         hsusb: usb@e6590000 {
 871                 compatible = "renesas,usbhs-r8a7794", "renesas,rcar-gen2-usbhs";
 872                 reg = <0 0xe6590000 0 0x100>;
 873                 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
 874                 clocks = <&mstp7_clks R8A7794_CLK_HSUSB>;
 875                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 876                 renesas,buswait = <4>;
 877                 phys = <&usb0 1>;
 878                 phy-names = "usb";
 879                 status = "disabled";
 880         };
 881
 882         usbphy: usb-phy@e6590100 {
 883                 compatible = "renesas,usb-phy-r8a7794",
 884                              "renesas,rcar-gen2-usb-phy";
 885                 reg = <0 0xe6590100 0 0x100>;
 886                 #address-cells = <1>;
 887                 #size-cells = <0>;
 888                 clocks = <&mstp7_clks R8A7794_CLK_HSUSB>;
 889                 clock-names = "usbhs";
 890                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 891                 status = "disabled";
 892
 893                 usb0: usb-channel@0 {
 894                         reg = <0>;
 895                         #phy-cells = <1>;
 896                 };
 897                 usb2: usb-channel@2 {
 898                         reg = <2>;
 899                         #phy-cells = <1>;
 900                 };
 901         };
 902
 903         vsp1@fe928000 {
 904                 compatible = "renesas,vsp1";
 905                 reg = <0 0xfe928000 0 0x8000>;
 906                 interrupts = <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>;
 907                 clocks = <&mstp1_clks R8A7794_CLK_VSP1_S>;
 908                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 909         };
 910
 911         vsp1@fe930000 {
 912                 compatible = "renesas,vsp1";
 913                 reg = <0 0xfe930000 0 0x8000>;
 914                 interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
 915                 clocks = <&mstp1_clks R8A7794_CLK_VSP1_DU0>;
 916                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 917         };
 918
 919         du: display@feb00000 {
 920                 compatible = "renesas,du-r8a7794";
 921                 reg = <0 0xfeb00000 0 0x40000>;
 922                 reg-names = "du";
 923                 interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
 924                              <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
 925                 clocks = <&mstp7_clks R8A7794_CLK_DU0>,
 926                          <&mstp7_clks R8A7794_CLK_DU0>;
 927                 clock-names = "du.0", "du.1";
 928                 status = "disabled";
 929
 930                 ports {
 931                         #address-cells = <1>;
 932                         #size-cells = <0>;
 933
 934                         port@0 {
 935                                 reg = <0>;
 936                                 du_out_rgb0: endpoint {
 937                                 };
 938                         };
 939                         port@1 {
 940                                 reg = <1>;
 941                                 du_out_rgb1: endpoint {
 942                                 };
 943                         };
 944                 };
 945         };
 946
 947         can0: can@e6e80000 {
 948                 compatible = "renesas,can-r8a7794", "renesas,rcar-gen2-can";
 949                 reg = <0 0xe6e80000 0 0x1000>;
 950                 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
 951                 clocks = <&mstp9_clks R8A7794_CLK_RCAN0>,
 952                          <&cpg_clocks R8A7794_CLK_RCAN>, <&can_clk>;
 953                 clock-names = "clkp1", "clkp2", "can_clk";
 954                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 955                 status = "disabled";
 956         };
 957
 958         can1: can@e6e88000 {
 959                 compatible = "renesas,can-r8a7794", "renesas,rcar-gen2-can";
 960                 reg = <0 0xe6e88000 0 0x1000>;
 961                 interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
 962                 clocks = <&mstp9_clks R8A7794_CLK_RCAN1>,
 963                          <&cpg_clocks R8A7794_CLK_RCAN>, <&can_clk>;
 964                 clock-names = "clkp1", "clkp2", "can_clk";
 965                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 966                 status = "disabled";
 967         };
 968
 969         clocks {
 970                 #address-cells = <2>;
 971                 #size-cells = <2>;
 972                 ranges;
 973
 974                 /* External root clock */
 975                 extal_clk: extal {
 976                         compatible = "fixed-clock";
 977                         #clock-cells = <0>;
 978                         /* This value must be overriden by the board. */
 979                         clock-frequency = <0>;
 980                 };
 981
 982                 /* External USB clock - can be overridden by the board */
 983                 usb_extal_clk: usb_extal {
 984                         compatible = "fixed-clock";
 985                         #clock-cells = <0>;
 986                         clock-frequency = <48000000>;
 987                 };
 988
 989                 /* External CAN clock */
 990                 can_clk: can {
 991                         compatible = "fixed-clock";
 992                         #clock-cells = <0>;
 993                         /* This value must be overridden by the board. */
 994                         clock-frequency = <0>;
 995                 };
 996
 997                 /* External SCIF clock */
 998                 scif_clk: scif {
 999                         compatible = "fixed-clock";
1000                         #clock-cells = <0>;
1001                         /* This value must be overridden by the board. */
1002                         clock-frequency = <0>;
1003                 };
1004
1005                 /*
1006                  * The external audio clocks are configured  as 0 Hz fixed
1007                  * frequency clocks by default.  Boards that provide audio
1008                  * clocks should override them.
1009                  */
1010                 audio_clka: audio_clka {
1011                         compatible = "fixed-clock";
1012                         #clock-cells = <0>;
1013                         clock-frequency = <0>;
1014                 };
1015                 audio_clkb: audio_clkb {
1016                         compatible = "fixed-clock";
1017                         #clock-cells = <0>;
1018                         clock-frequency = <0>;
1019                 };
1020                 audio_clkc: audio_clkc {
1021                         compatible = "fixed-clock";
1022                         #clock-cells = <0>;
1023                         clock-frequency = <0>;
1024                 };
1025
1026                 /* Special CPG clocks */
1027                 cpg_clocks: cpg_clocks@e6150000 {
1028                         compatible = "renesas,r8a7794-cpg-clocks",
1029                                      "renesas,rcar-gen2-cpg-clocks";
1030                         reg = <0 0xe6150000 0 0x1000>;
1031                         clocks = <&extal_clk &usb_extal_clk>;
1032                         #clock-cells = <1>;
1033                         clock-output-names = "main", "pll0", "pll1", "pll3",
1034                                              "lb", "qspi", "sdh", "sd0", "rcan";
1035                         #power-domain-cells = <0>;
1036                 };
1037                 /* Variable factor clocks */
1038                 sd2_clk: sd2@e6150078 {
1039                         compatible = "renesas,r8a7794-div6-clock", "renesas,cpg-div6-clock";
1040                         reg = <0 0xe6150078 0 4>;
1041                         clocks = <&pll1_div2_clk>;
1042                         #clock-cells = <0>;
1043                 };
1044                 sd3_clk: sd3@e615026c {
1045                         compatible = "renesas,r8a7794-div6-clock", "renesas,cpg-div6-clock";
1046                         reg = <0 0xe615026c 0 4>;
1047                         clocks = <&pll1_div2_clk>;
1048                         #clock-cells = <0>;
1049                 };
1050                 mmc0_clk: mmc0@e6150240 {
1051                         compatible = "renesas,r8a7794-div6-clock", "renesas,cpg-div6-clock";
1052                         reg = <0 0xe6150240 0 4>;
1053                         clocks = <&pll1_div2_clk>;
1054                         #clock-cells = <0>;
1055                 };
1056
1057                 /* Fixed factor clocks */
1058                 pll1_div2_clk: pll1_div2 {
1059                         compatible = "fixed-factor-clock";
1060                         clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
1061                         #clock-cells = <0>;
1062                         clock-div = <2>;
1063                         clock-mult = <1>;
1064                 };
1065                 zg_clk: zg {
1066                         compatible = "fixed-factor-clock";
1067                         clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
1068                         #clock-cells = <0>;
1069                         clock-div = <6>;
1070                         clock-mult = <1>;
1071                 };
1072                 zx_clk: zx {
1073                         compatible = "fixed-factor-clock";
1074                         clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
1075                         #clock-cells = <0>;
1076                         clock-div = <3>;
1077                         clock-mult = <1>;
1078                 };
1079                 zs_clk: zs {
1080                         compatible = "fixed-factor-clock";
1081                         clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
1082                         #clock-cells = <0>;
1083                         clock-div = <6>;
1084                         clock-mult = <1>;
1085                 };
1086                 hp_clk: hp {
1087                         compatible = "fixed-factor-clock";
1088                         clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
1089                         #clock-cells = <0>;
1090                         clock-div = <12>;
1091                         clock-mult = <1>;
1092                 };
1093                 i_clk: i {
1094                         compatible = "fixed-factor-clock";
1095                         clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
1096                         #clock-cells = <0>;
1097                         clock-div = <2>;
1098                         clock-mult = <1>;
1099                 };
1100                 b_clk: b {
1101                         compatible = "fixed-factor-clock";
1102                         clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
1103                         #clock-cells = <0>;
1104                         clock-div = <12>;
1105                         clock-mult = <1>;
1106                 };
1107                 p_clk: p {
1108                         compatible = "fixed-factor-clock";
1109                         clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
1110                         #clock-cells = <0>;
1111                         clock-div = <24>;
1112                         clock-mult = <1>;
1113                 };
1114                 cl_clk: cl {
1115                         compatible = "fixed-factor-clock";
1116                         clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
1117                         #clock-cells = <0>;
1118                         clock-div = <48>;
1119                         clock-mult = <1>;
1120                 };
1121                 m2_clk: m2 {
1122                         compatible = "fixed-factor-clock";
1123                         clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
1124                         #clock-cells = <0>;
1125                         clock-div = <8>;
1126                         clock-mult = <1>;
1127                 };
1128                 rclk_clk: rclk {
1129                         compatible = "fixed-factor-clock";
1130                         clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
1131                         #clock-cells = <0>;
1132                         clock-div = <(48 * 1024)>;
1133                         clock-mult = <1>;
1134                 };
1135                 oscclk_clk: oscclk {
1136                         compatible = "fixed-factor-clock";
1137                         clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
1138                         #clock-cells = <0>;
1139                         clock-div = <(12 * 1024)>;
1140                         clock-mult = <1>;
1141                 };
1142                 zb3_clk: zb3 {
1143                         compatible = "fixed-factor-clock";
1144                         clocks = <&cpg_clocks R8A7794_CLK_PLL3>;
1145                         #clock-cells = <0>;
1146                         clock-div = <4>;
1147                         clock-mult = <1>;
1148                 };
1149                 zb3d2_clk: zb3d2 {
1150                         compatible = "fixed-factor-clock";
1151                         clocks = <&cpg_clocks R8A7794_CLK_PLL3>;
1152                         #clock-cells = <0>;
1153                         clock-div = <8>;
1154                         clock-mult = <1>;
1155                 };
1156                 ddr_clk: ddr {
1157                         compatible = "fixed-factor-clock";
1158                         clocks = <&cpg_clocks R8A7794_CLK_PLL3>;
1159                         #clock-cells = <0>;
1160                         clock-div = <8>;
1161                         clock-mult = <1>;
1162                 };
1163                 mp_clk: mp {
1164                         compatible = "fixed-factor-clock";
1165                         clocks = <&pll1_div2_clk>;
1166                         #clock-cells = <0>;
1167                         clock-div = <15>;
1168                         clock-mult = <1>;
1169                 };
1170                 cp_clk: cp {
1171                         compatible = "fixed-factor-clock";
1172                         clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
1173                         #clock-cells = <0>;
1174                         clock-div = <48>;
1175                         clock-mult = <1>;
1176                 };
1177
1178                 acp_clk: acp {
1179                         compatible = "fixed-factor-clock";
1180                         clocks = <&extal_clk>;
1181                         #clock-cells = <0>;
1182                         clock-div = <2>;
1183                         clock-mult = <1>;
1184                 };
1185
1186                 /* Gate clocks */
1187                 mstp0_clks: mstp0_clks@e6150130 {
1188                         compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";
1189                         reg = <0 0xe6150130 0 4>, <0 0xe6150030 0 4>;
1190                         clocks = <&mp_clk>;
1191                         #clock-cells = <1>;
1192                         clock-indices = <R8A7794_CLK_MSIOF0>;
1193                         clock-output-names = "msiof0";
1194                 };
1195                 mstp1_clks: mstp1_clks@e6150134 {
1196                         compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";
1197                         reg = <0 0xe6150134 0 4>, <0 0xe6150038 0 4>;
1198                         clocks = <&zs_clk>, <&zs_clk>, <&p_clk>, <&zg_clk>, <&zs_clk>,
1199                                  <&zs_clk>, <&p_clk>, <&p_clk>, <&rclk_clk>, <&cp_clk>,
1200                                  <&zs_clk>, <&zs_clk>;
1201                         #clock-cells = <1>;
1202                         clock-indices = <
1203                                 R8A7794_CLK_VCP0 R8A7794_CLK_VPC0 R8A7794_CLK_TMU1
1204                                 R8A7794_CLK_3DG R8A7794_CLK_2DDMAC R8A7794_CLK_FDP1_0
1205                                 R8A7794_CLK_TMU3 R8A7794_CLK_TMU2 R8A7794_CLK_CMT0
1206                                 R8A7794_CLK_TMU0 R8A7794_CLK_VSP1_DU0 R8A7794_CLK_VSP1_S
1207                         >;
1208                         clock-output-names =
1209                                 "vcp0", "vpc0", "tmu1", "3dg", "2ddmac", "fdp1-0",
1210                                 "tmu3", "tmu2", "cmt0", "tmu0", "vsp1-du0", "vsps";
1211                 };
1212                 mstp2_clks: mstp2_clks@e6150138 {
1213                         compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";
1214                         reg = <0 0xe6150138 0 4>, <0 0xe6150040 0 4>;
1215                         clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>,
1216                                  <&mp_clk>, <&mp_clk>, <&mp_clk>,
1217                                  <&zs_clk>, <&zs_clk>;
1218                         #clock-cells = <1>;
1219                         clock-indices = <
1220                                 R8A7794_CLK_SCIFA2 R8A7794_CLK_SCIFA1 R8A7794_CLK_SCIFA0
1221                                 R8A7794_CLK_MSIOF2 R8A7794_CLK_SCIFB0 R8A7794_CLK_SCIFB1
1222                                 R8A7794_CLK_MSIOF1 R8A7794_CLK_SCIFB2
1223                                 R8A7794_CLK_SYS_DMAC1 R8A7794_CLK_SYS_DMAC0
1224                         >;
1225                         clock-output-names =
1226                                 "scifa2", "scifa1", "scifa0", "msiof2", "scifb0",
1227                                 "scifb1", "msiof1", "scifb2",
1228                                 "sys-dmac1", "sys-dmac0";
1229                 };
1230                 mstp3_clks: mstp3_clks@e615013c {
1231                         compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";
1232                         reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>;
1233                         clocks = <&sd3_clk>, <&sd2_clk>, <&cpg_clocks R8A7794_CLK_SD0>,
1234                                  <&mmc0_clk>, <&hp_clk>, <&hp_clk>, <&rclk_clk>,
1235                                  <&hp_clk>, <&hp_clk>;
1236                         #clock-cells = <1>;
1237                         clock-indices = <
1238                                 R8A7794_CLK_SDHI2 R8A7794_CLK_SDHI1 R8A7794_CLK_SDHI0
1239                                 R8A7794_CLK_MMCIF0 R8A7794_CLK_IIC0
1240                                 R8A7794_CLK_IIC1 R8A7794_CLK_CMT1
1241                                 R8A7794_CLK_USBDMAC0 R8A7794_CLK_USBDMAC1
1242                         >;
1243                         clock-output-names =
1244                                 "sdhi2", "sdhi1", "sdhi0",
1245                                 "mmcif0", "i2c6", "i2c7",
1246                                 "cmt1", "usbdmac0", "usbdmac1";
1247                 };
1248                 mstp4_clks: mstp4_clks@e6150140 {
1249                         compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";
1250                         reg = <0 0xe6150140 0 4>, <0 0xe615004c 0 4>;
1251                         clocks = <&cp_clk>;
1252                         #clock-cells = <1>;
1253                         clock-indices = <R8A7794_CLK_IRQC>;
1254                         clock-output-names = "irqc";
1255                 };
1256                 mstp5_clks: mstp5_clks@e6150144 {
1257                         compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";
1258                         reg = <0 0xe6150144 0 4>, <0 0xe615003c 0 4>;
1259                         clocks = <&hp_clk>, <&p_clk>;
1260                         #clock-cells = <1>;
1261                         clock-indices = <R8A7794_CLK_AUDIO_DMAC0
1262                                          R8A7794_CLK_PWM>;
1263                         clock-output-names = "audmac0", "pwm";
1264                 };
1265                 mstp7_clks: mstp7_clks@e615014c {
1266                         compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";
1267                         reg = <0 0xe615014c 0 4>, <0 0xe61501c4 0 4>;
1268                         clocks = <&mp_clk>, <&hp_clk>,
1269                                  <&zs_clk>, <&p_clk>, <&p_clk>, <&zs_clk>,
1270                                  <&zs_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>,
1271                                  <&zx_clk>;
1272                         #clock-cells = <1>;
1273                         clock-indices = <
1274                                 R8A7794_CLK_EHCI R8A7794_CLK_HSUSB
1275                                 R8A7794_CLK_HSCIF2 R8A7794_CLK_SCIF5
1276                                 R8A7794_CLK_SCIF4 R8A7794_CLK_HSCIF1 R8A7794_CLK_HSCIF0
1277                                 R8A7794_CLK_SCIF3 R8A7794_CLK_SCIF2 R8A7794_CLK_SCIF1
1278                                 R8A7794_CLK_SCIF0 R8A7794_CLK_DU0
1279                         >;
1280                         clock-output-names =
1281                                 "ehci", "hsusb",
1282                                 "hscif2", "scif5", "scif4", "hscif1", "hscif0",
1283                                 "scif3", "scif2", "scif1", "scif0", "du0";
1284                 };
1285                 mstp8_clks: mstp8_clks@e6150990 {
1286                         compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";
1287                         reg = <0 0xe6150990 0 4>, <0 0xe61509a0 0 4>;
1288                         clocks = <&zg_clk>, <&zg_clk>, <&hp_clk>, <&p_clk>;
1289                         #clock-cells = <1>;
1290                         clock-indices = <
1291                                 R8A7794_CLK_VIN1 R8A7794_CLK_VIN0
1292                                 R8A7794_CLK_ETHERAVB R8A7794_CLK_ETHER
1293                         >;
1294                         clock-output-names =
1295                                 "vin1", "vin0", "etheravb", "ether";
1296                 };
1297                 mstp9_clks: mstp9_clks@e6150994 {
1298                         compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";
1299                         reg = <0 0xe6150994 0 4>, <0 0xe61509a4 0 4>;
1300                         clocks = <&cp_clk>, <&cp_clk>, <&cp_clk>, <&cp_clk>,
1301                                  <&cp_clk>, <&cp_clk>, <&cp_clk>, <&p_clk>,
1302                                  <&p_clk>, <&cpg_clocks R8A7794_CLK_QSPI>,
1303                                  <&hp_clk>, <&hp_clk>, <&hp_clk>, <&hp_clk>,
1304                                  <&hp_clk>, <&hp_clk>;
1305                         #clock-cells = <1>;
1306                         clock-indices = <R8A7794_CLK_GPIO6 R8A7794_CLK_GPIO5
1307                                          R8A7794_CLK_GPIO4 R8A7794_CLK_GPIO3
1308                                          R8A7794_CLK_GPIO2 R8A7794_CLK_GPIO1
1309                                          R8A7794_CLK_GPIO0 R8A7794_CLK_RCAN1
1310                                          R8A7794_CLK_RCAN0 R8A7794_CLK_QSPI_MOD
1311                                          R8A7794_CLK_I2C5 R8A7794_CLK_I2C4
1312                                          R8A7794_CLK_I2C3 R8A7794_CLK_I2C2
1313                                          R8A7794_CLK_I2C1 R8A7794_CLK_I2C0>;
1314                         clock-output-names =
1315                                 "gpio6", "gpio5", "gpio4", "gpio3", "gpio2",
1316                                 "gpio1", "gpio0", "rcan1", "rcan0", "qspi_mod",
1317                                 "i2c5", "i2c4", "i2c3", "i2c2", "i2c1", "i2c0";
1318                 };
1319                 mstp10_clks: mstp10_clks@e6150998 {
1320                         compatible = "renesas,r8a7794-mstp-clocks",
1321                                      "renesas,cpg-mstp-clocks";
1322                         reg = <0 0xe6150998 0 4>, <0 0xe61509a8 0 4>;
1323                         clocks = <&p_clk>,
1324                                  <&mstp10_clks R8A7794_CLK_SSI_ALL>,
1325                                  <&mstp10_clks R8A7794_CLK_SSI_ALL>,
1326                                  <&mstp10_clks R8A7794_CLK_SSI_ALL>,
1327                                  <&mstp10_clks R8A7794_CLK_SSI_ALL>,
1328                                  <&mstp10_clks R8A7794_CLK_SSI_ALL>,
1329                                  <&mstp10_clks R8A7794_CLK_SSI_ALL>,
1330                                  <&mstp10_clks R8A7794_CLK_SSI_ALL>,
1331                                  <&mstp10_clks R8A7794_CLK_SSI_ALL>,
1332                                  <&mstp10_clks R8A7794_CLK_SSI_ALL>,
1333                                  <&mstp10_clks R8A7794_CLK_SSI_ALL>,
1334                                  <&p_clk>,
1335                                  <&mstp10_clks R8A7794_CLK_SCU_ALL>,
1336                                  <&mstp10_clks R8A7794_CLK_SCU_ALL>,
1337                                  <&mstp10_clks R8A7794_CLK_SCU_ALL>,
1338                                  <&mstp10_clks R8A7794_CLK_SCU_ALL>,
1339                                  <&mstp10_clks R8A7794_CLK_SCU_ALL>,
1340                                  <&mstp10_clks R8A7794_CLK_SCU_ALL>,
1341                                  <&mstp10_clks R8A7794_CLK_SCU_ALL>,
1342                                  <&mstp10_clks R8A7794_CLK_SCU_ALL>,
1343                                  <&mstp10_clks R8A7794_CLK_SCU_ALL>,
1344                                  <&mstp10_clks R8A7794_CLK_SCU_ALL>;
1345                         #clock-cells = <1>;
1346                         clock-indices = <R8A7794_CLK_SSI_ALL
1347                                          R8A7794_CLK_SSI9 R8A7794_CLK_SSI8
1348                                          R8A7794_CLK_SSI7 R8A7794_CLK_SSI6
1349                                          R8A7794_CLK_SSI5 R8A7794_CLK_SSI4
1350                                          R8A7794_CLK_SSI3 R8A7794_CLK_SSI2
1351                                          R8A7794_CLK_SSI1 R8A7794_CLK_SSI0
1352                                          R8A7794_CLK_SCU_ALL
1353                                          R8A7794_CLK_SCU_DVC1
1354                                          R8A7794_CLK_SCU_DVC0
1355                                          R8A7794_CLK_SCU_CTU1_MIX1
1356                                          R8A7794_CLK_SCU_CTU0_MIX0
1357                                          R8A7794_CLK_SCU_SRC6
1358                                          R8A7794_CLK_SCU_SRC5
1359                                          R8A7794_CLK_SCU_SRC4
1360                                          R8A7794_CLK_SCU_SRC3
1361                                          R8A7794_CLK_SCU_SRC2
1362                                          R8A7794_CLK_SCU_SRC1>;
1363                         clock-output-names = "ssi-all", "ssi9", "ssi8", "ssi7",
1364                                              "ssi6", "ssi5", "ssi4", "ssi3",
1365                                              "ssi2", "ssi1", "ssi0",
1366                                              "scu-all", "scu-dvc1", "scu-dvc0",
1367                                              "scu-ctu1-mix1", "scu-ctu0-mix0",
1368                                              "scu-src6", "scu-src5", "scu-src4",
1369                                              "scu-src3", "scu-src2", "scu-src1";
1370                 };
1371                 mstp11_clks: mstp11_clks@e615099c {
1372                         compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";
1373                         reg = <0 0xe615099c 0 4>, <0 0xe61509ac 0 4>;
1374                         clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>;
1375                         #clock-cells = <1>;
1376                         clock-indices = <
1377                                 R8A7794_CLK_SCIFA3 R8A7794_CLK_SCIFA4 R8A7794_CLK_SCIFA5
1378                         >;
1379                         clock-output-names = "scifa3", "scifa4", "scifa5";
1380                 };
1381         };
1382
1383         rst: reset-controller@e6160000 {
1384                 compatible = "renesas,r8a7794-rst";
1385                 reg = <0 0xe6160000 0 0x0100>;
1386         };
1387
1388         prr: chipid@ff000044 {
1389                 compatible = "renesas,prr";
1390                 reg = <0 0xff000044 0 4>;
1391         };
1392
1393         sysc: system-controller@e6180000 {
1394                 compatible = "renesas,r8a7794-sysc";
1395                 reg = <0 0xe6180000 0 0x0200>;
1396                 #power-domain-cells = <1>;
1397         };
1398
1399         ipmmu_sy0: mmu@e6280000 {
1400                 compatible = "renesas,ipmmu-r8a7794", "renesas,ipmmu-vmsa";
1401                 reg = <0 0xe6280000 0 0x1000>;
1402                 interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>,
1403                              <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>;
1404                 #iommu-cells = <1>;
1405                 status = "disabled";
1406         };
1407
1408         ipmmu_sy1: mmu@e6290000 {
1409                 compatible = "renesas,ipmmu-r8a7794", "renesas,ipmmu-vmsa";
1410                 reg = <0 0xe6290000 0 0x1000>;
1411                 interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
1412                 #iommu-cells = <1>;
1413                 status = "disabled";
1414         };
1415
1416         ipmmu_ds: mmu@e6740000 {
1417                 compatible = "renesas,ipmmu-r8a7794", "renesas,ipmmu-vmsa";
1418                 reg = <0 0xe6740000 0 0x1000>;
1419                 interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
1420                              <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>;
1421                 #iommu-cells = <1>;
1422                 status = "disabled";
1423         };
1424
1425         ipmmu_mp: mmu@ec680000 {
1426                 compatible = "renesas,ipmmu-r8a7794", "renesas,ipmmu-vmsa";
1427                 reg = <0 0xec680000 0 0x1000>;
1428                 interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
1429                 #iommu-cells = <1>;
1430                 status = "disabled";
1431         };
1432
1433         ipmmu_mx: mmu@fe951000 {
1434                 compatible = "renesas,ipmmu-r8a7794", "renesas,ipmmu-vmsa";
1435                 reg = <0 0xfe951000 0 0x1000>;
1436                 interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>,
1437                              <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
1438                 #iommu-cells = <1>;
1439                 status = "disabled";
1440         };
1441
1442         ipmmu_gp: mmu@e62a0000 {
1443                 compatible = "renesas,ipmmu-r8a7794", "renesas,ipmmu-vmsa";
1444                 reg = <0 0xe62a0000 0 0x1000>;
1445                 interrupts = <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
1446                              <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>;
1447                 #iommu-cells = <1>;
1448                 status = "disabled";
1449         };
1450
1451         rcar_sound: sound@ec500000 {
1452                 /*
1453                  * #sound-dai-cells is required
1454                  *
1455                  * Single DAI : #sound-dai-cells = <0>;         <&rcar_sound>;
1456                  * Multi  DAI : #sound-dai-cells = <1>;         <&rcar_sound N>;
1457                  */
1458                 compatible = "renesas,rcar_sound-r8a7794",
1459                              "renesas,rcar_sound-gen2";
1460                 reg =   <0 0xec500000 0 0x1000>, /* SCU */
1461                         <0 0xec5a0000 0 0x100>,  /* ADG */
1462                         <0 0xec540000 0 0x1000>, /* SSIU */
1463                         <0 0xec541000 0 0x280>,  /* SSI */
1464                         <0 0xec740000 0 0x200>;  /* Audio DMAC peri peri */
1465                 reg-names = "scu", "adg", "ssiu", "ssi", "audmapp";
1466
1467                 clocks = <&mstp10_clks R8A7794_CLK_SSI_ALL>,
1468                          <&mstp10_clks R8A7794_CLK_SSI9>,
1469                          <&mstp10_clks R8A7794_CLK_SSI8>,
1470                          <&mstp10_clks R8A7794_CLK_SSI7>,
1471                          <&mstp10_clks R8A7794_CLK_SSI6>,
1472                          <&mstp10_clks R8A7794_CLK_SSI5>,
1473                          <&mstp10_clks R8A7794_CLK_SSI4>,
1474                          <&mstp10_clks R8A7794_CLK_SSI3>,
1475                          <&mstp10_clks R8A7794_CLK_SSI2>,
1476                          <&mstp10_clks R8A7794_CLK_SSI1>,
1477                          <&mstp10_clks R8A7794_CLK_SSI0>,
1478                          <&mstp10_clks R8A7794_CLK_SCU_SRC6>,
1479                          <&mstp10_clks R8A7794_CLK_SCU_SRC5>,
1480                          <&mstp10_clks R8A7794_CLK_SCU_SRC4>,
1481                          <&mstp10_clks R8A7794_CLK_SCU_SRC3>,
1482                          <&mstp10_clks R8A7794_CLK_SCU_SRC2>,
1483                          <&mstp10_clks R8A7794_CLK_SCU_SRC1>,
1484                          <&mstp10_clks R8A7794_CLK_SCU_CTU0_MIX0>,
1485                          <&mstp10_clks R8A7794_CLK_SCU_CTU1_MIX1>,
1486                          <&mstp10_clks R8A7794_CLK_SCU_CTU0_MIX0>,
1487                          <&mstp10_clks R8A7794_CLK_SCU_CTU1_MIX1>,
1488                          <&mstp10_clks R8A7794_CLK_SCU_DVC0>,
1489                          <&mstp10_clks R8A7794_CLK_SCU_DVC1>,
1490                          <&audio_clka>, <&audio_clkb>, <&audio_clkc>,
1491                          <&m2_clk>;
1492                 clock-names = "ssi-all",
1493                               "ssi.9", "ssi.8", "ssi.7", "ssi.6", "ssi.5",
1494                               "ssi.4", "ssi.3", "ssi.2", "ssi.1", "ssi.0",
1495                               "src.6", "src.5", "src.4", "src.3", "src.2",
1496                               "src.1",
1497                               "ctu.0", "ctu.1",
1498                               "mix.0", "mix.1",
1499                               "dvc.0", "dvc.1",
1500                               "clk_a", "clk_b", "clk_c", "clk_i";
1501                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
1502
1503                 status = "disabled";
1504
1505                 rcar_sound,dvc {
1506                         dvc0: dvc-0 {
1507                                 dmas = <&audma0 0xbc>;
1508                                 dma-names = "tx";
1509                         };
1510                         dvc1: dvc-1 {
1511                                 dmas = <&audma0 0xbe>;
1512                                 dma-names = "tx";
1513                         };
1514                 };
1515
1516                 rcar_sound,mix {
1517                         mix0: mix-0 { };
1518                         mix1: mix-1 { };
1519                 };
1520
1521                 rcar_sound,ctu {
1522                         ctu00: ctu-0 { };
1523                         ctu01: ctu-1 { };
1524                         ctu02: ctu-2 { };
1525                         ctu03: ctu-3 { };
1526                         ctu10: ctu-4 { };
1527                         ctu11: ctu-5 { };
1528                         ctu12: ctu-6 { };
1529                         ctu13: ctu-7 { };
1530                 };
1531
1532                 rcar_sound,src {
1533                         src-0 {
1534                                 status = "disabled";
1535                         };
1536                         src1: src-1 {
1537                                 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1538                                 dmas = <&audma0 0x87>, <&audma0 0x9c>;
1539                                 dma-names = "rx", "tx";
1540                         };
1541                         src2: src-2 {
1542                                 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1543                                 dmas = <&audma0 0x89>, <&audma0 0x9e>;
1544                                 dma-names = "rx", "tx";
1545                         };
1546                         src3: src-3 {
1547                                 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1548                                 dmas = <&audma0 0x8b>, <&audma0 0xa0>;
1549                                 dma-names = "rx", "tx";
1550                         };
1551                         src4: src-4 {
1552                                 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1553                                 dmas = <&audma0 0x8d>, <&audma0 0xb0>;
1554                                 dma-names = "rx", "tx";
1555                         };
1556                         src5: src-5 {
1557                                 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1558                                 dmas = <&audma0 0x8f>, <&audma0 0xb2>;
1559                                 dma-names = "rx", "tx";
1560                         };
1561                         src6: src-6 {
1562                                 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1563                                 dmas = <&audma0 0x91>, <&audma0 0xb4>;
1564                                 dma-names = "rx", "tx";
1565                         };
1566                 };
1567
1568                 rcar_sound,ssi {
1569                         ssi0: ssi-0 {
1570                                 interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>;
1571                                 dmas = <&audma0 0x01>, <&audma0 0x02>,
1572                                        <&audma0 0x15>, <&audma0 0x16>;
1573                                 dma-names = "rx", "tx", "rxu", "txu";
1574                         };
1575                         ssi1: ssi-1 {
1576                                 interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>;
1577                                 dmas = <&audma0 0x03>, <&audma0 0x04>,
1578                                        <&audma0 0x49>, <&audma0 0x4a>;
1579                                 dma-names = "rx", "tx", "rxu", "txu";
1580                         };
1581                         ssi2: ssi-2 {
1582                                 interrupts = <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>;
1583                                 dmas = <&audma0 0x05>, <&audma0 0x06>,
1584                                        <&audma0 0x63>, <&audma0 0x64>;
1585                                 dma-names = "rx", "tx", "rxu", "txu";
1586                         };
1587                         ssi3: ssi-3 {
1588                                 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
1589                                 dmas = <&audma0 0x07>, <&audma0 0x08>,
1590                                        <&audma0 0x6f>, <&audma0 0x70>;
1591                                 dma-names = "rx", "tx", "rxu", "txu";
1592                         };
1593                         ssi4: ssi-4 {
1594                                 interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>;
1595                                 dmas = <&audma0 0x09>, <&audma0 0x0a>,
1596                                        <&audma0 0x71>, <&audma0 0x72>;
1597                                 dma-names = "rx", "tx", "rxu", "txu";
1598                         };
1599                         ssi5: ssi-5 {
1600                                 interrupts = <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>;
1601                                 dmas = <&audma0 0x0b>, <&audma0 0x0c>,
1602                                        <&audma0 0x73>, <&audma0 0x74>;
1603                                 dma-names = "rx", "tx", "rxu", "txu";
1604                         };
1605                         ssi6: ssi-6 {
1606                                 interrupts = <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>;
1607                                 dmas = <&audma0 0x0d>, <&audma0 0x0e>,
1608                                        <&audma0 0x75>, <&audma0 0x76>;
1609                                 dma-names = "rx", "tx", "rxu", "txu";
1610                         };
1611                         ssi7: ssi-7 {
1612                                 interrupts = <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>;
1613                                 dmas = <&audma0 0x0f>, <&audma0 0x10>,
1614                                        <&audma0 0x79>, <&audma0 0x7a>;
1615                                 dma-names = "rx", "tx", "rxu", "txu";
1616                         };
1617                         ssi8: ssi-8 {
1618                                 interrupts = <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>;
1619                                 dmas = <&audma0 0x11>, <&audma0 0x12>,
1620                                        <&audma0 0x7b>, <&audma0 0x7c>;
1621                                 dma-names = "rx", "tx", "rxu", "txu";
1622                         };
1623                         ssi9: ssi-9 {
1624                                 interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>;
1625                                 dmas = <&audma0 0x13>, <&audma0 0x14>,
1626                                        <&audma0 0x7d>, <&audma0 0x7e>;
1627                                 dma-names = "rx", "tx", "rxu", "txu";
1628                         };
1629                 };
1630         };
1631 };