2 * Device tree file for Phytec phyCORE-RK3288 SoM
3 * Copyright (C) 2017 PHYTEC Messtechnik GmbH
4 * Author: Wadim Egorov <w.egorov@phytec.de>
6 * This file is dual-licensed: you can use it either under the terms
7 * of the GPL or the X11 license, at your option. Note that this dual
8 * licensing only applies to this file, and not this project as a
11 * a) This file is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of the
14 * License, or (at your option) any later version.
16 * This file is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
23 * b) Permission is hereby granted, free of charge, to any person
24 * obtaining a copy of this software and associated documentation
25 * files (the "Software"), to deal in the Software without
26 * restriction, including without limitation the rights to use,
27 * copy, modify, merge, publish, distribute, sublicense, and/or
28 * sell copies of the Software, and to permit persons to whom the
29 * Software is furnished to do so, subject to the following
32 * The above copyright notice and this permission notice shall be
33 * included in all copies or substantial portions of the Software.
35 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
36 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
37 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
38 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
39 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
40 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
41 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
42 * OTHER DEALINGS IN THE SOFTWARE.
45 #include <dt-bindings/net/ti-dp83867.h>
46 #include "rk3288.dtsi"
49 model = "Phytec RK3288 phyCORE";
50 compatible = "phytec,rk3288-phycore-som", "rockchip,rk3288";
53 * Set the minimum memory size here and
54 * let the bootloader set the real size.
57 device_type = "memory";
58 reg = <0x0 0x0 0x0 0x8000000>;
66 ext_gmac: external-gmac-clock {
67 compatible = "fixed-clock";
69 clock-frequency = <125000000>;
70 clock-output-names = "ext_gmac";
74 compatible = "gpio-leds";
75 pinctrl-names = "default";
76 pinctrl-0 = <&user_led>;
80 gpios = <&gpio7 2 GPIO_ACTIVE_HIGH>;
81 linux,default-trigger = "heartbeat";
82 default-state = "keep";
86 vdd_emmc_io: vdd-emmc-io {
87 compatible = "regulator-fixed";
88 regulator-name = "vdd_emmc_io";
89 regulator-min-microvolt = <1800000>;
90 regulator-max-microvolt = <1800000>;
91 vin-supply = <&vdd_3v3_io>;
94 vdd_in_otg_out: vdd-in-otg-out {
95 compatible = "regulator-fixed";
96 regulator-name = "vdd_in_otg_out";
99 regulator-min-microvolt = <5000000>;
100 regulator-max-microvolt = <5000000>;
103 vdd_misc_1v8: vdd-misc-1v8 {
104 compatible = "regulator-fixed";
105 regulator-name = "vdd_misc_1v8";
108 regulator-min-microvolt = <1800000>;
109 regulator-max-microvolt = <1800000>;
119 pinctrl-names = "default";
120 pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_pwr &emmc_bus8>;
121 vmmc-supply = <&vdd_3v3_io>;
122 vqmmc-supply = <&vdd_emmc_io>;
126 assigned-clocks = <&cru SCLK_MAC>;
127 assigned-clock-parents = <&ext_gmac>;
128 clock_in_out = "input";
129 pinctrl-names = "default";
130 pinctrl-0 = <&rgmii_pins &phy_rst &phy_int>;
131 phy-handle = <&phy0>;
132 phy-supply = <&vdd_eth_2v5>;
133 phy-mode = "rgmii-id";
134 snps,reset-active-low;
135 snps,reset-delays-us = <0 10000 1000000>;
136 snps,reset-gpio = <&gpio4 8 GPIO_ACTIVE_HIGH>;
141 compatible = "snps,dwmac-mdio";
142 #address-cells = <1>;
145 phy0: ethernet-phy@0 {
146 compatible = "ethernet-phy-ieee802.3-c22";
148 interrupt-parent = <&gpio4>;
149 interrupts = <2 IRQ_TYPE_EDGE_FALLING>;
150 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
151 ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
152 ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
153 enet-phy-lane-no-swap;
154 ti,clk-output-sel = <DP83867_CLK_O_SEL_CHN_A_TCLK>;
160 ddc-i2c-bus = <&i2c5>;
165 sdcard-supply = <&vdd_io_sd>;
166 flash0-supply = <&vdd_emmc_io>;
167 flash1-supply = <&vdd_misc_1v8>;
168 gpio1830-supply = <&vdd_3v3_io>;
169 gpio30-supply = <&vdd_3v3_io>;
170 bb-supply = <&vdd_3v3_io>;
171 dvp-supply = <&vdd_3v3_io>;
172 lcdc-supply = <&vdd_3v3_io>;
173 wifi-supply = <&vdd_3v3_io>;
174 audio-supply = <&vdd_3v3_io>;
179 clock-frequency = <400000>;
182 compatible = "rockchip,rk818";
184 interrupt-parent = <&gpio0>;
185 interrupts = <4 IRQ_TYPE_LEVEL_LOW>;
186 pinctrl-names = "default";
187 pinctrl-0 = <&pmic_int>;
188 rockchip,system-power-controller;
192 vcc1-supply = <&vdd_sys>;
193 vcc2-supply = <&vdd_sys>;
194 vcc3-supply = <&vdd_sys>;
195 vcc4-supply = <&vdd_sys>;
196 boost-supply = <&vdd_in_otg_out>;
197 vcc6-supply = <&vdd_sys>;
198 vcc7-supply = <&vdd_misc_1v8>;
199 vcc8-supply = <&vdd_misc_1v8>;
200 vcc9-supply = <&vdd_3v3_io>;
201 vddio-supply = <&vdd_3v3_io>;
205 regulator-name = "vdd_log";
208 regulator-min-microvolt = <1100000>;
209 regulator-max-microvolt = <1100000>;
210 regulator-state-mem {
211 regulator-off-in-suspend;
216 regulator-name = "vdd_gpu";
219 regulator-min-microvolt = <800000>;
220 regulator-max-microvolt = <1250000>;
221 regulator-state-mem {
222 regulator-on-in-suspend;
223 regulator-suspend-microvolt = <1000000>;
228 regulator-name = "vcc_ddr";
231 regulator-state-mem {
232 regulator-on-in-suspend;
236 vdd_3v3_io: DCDC_REG4 {
237 regulator-name = "vdd_3v3_io";
240 regulator-min-microvolt = <3300000>;
241 regulator-max-microvolt = <3300000>;
242 regulator-state-mem {
243 regulator-on-in-suspend;
244 regulator-suspend-microvolt = <3300000>;
248 vdd_sys: DCDC_BOOST {
249 regulator-name = "vdd_sys";
252 regulator-min-microvolt = <5000000>;
253 regulator-max-microvolt = <5000000>;
254 regulator-state-mem {
255 regulator-on-in-suspend;
256 regulator-suspend-microvolt = <5000000>;
262 regulator-name = "vdd_sd";
265 regulator-state-mem {
266 regulator-off-in-suspend;
271 vdd_eth_2v5: LDO_REG2 {
272 regulator-name = "vdd_eth_2v5";
275 regulator-min-microvolt = <2500000>;
276 regulator-max-microvolt = <2500000>;
277 regulator-state-mem {
278 regulator-on-in-suspend;
279 regulator-suspend-microvolt = <2500000>;
285 regulator-name = "vdd_1v0";
288 regulator-min-microvolt = <1000000>;
289 regulator-max-microvolt = <1000000>;
290 regulator-state-mem {
291 regulator-on-in-suspend;
292 regulator-suspend-microvolt = <1000000>;
297 vdd_1v8_lcd_ldo: LDO_REG4 {
298 regulator-name = "vdd_1v8_lcd_ldo";
301 regulator-min-microvolt = <1800000>;
302 regulator-max-microvolt = <1800000>;
303 regulator-state-mem {
304 regulator-on-in-suspend;
305 regulator-suspend-microvolt = <1800000>;
310 vdd_1v0_lcd: LDO_REG6 {
311 regulator-name = "vdd_1v0_lcd";
314 regulator-min-microvolt = <1000000>;
315 regulator-max-microvolt = <1000000>;
316 regulator-state-mem {
317 regulator-on-in-suspend;
318 regulator-suspend-microvolt = <1000000>;
323 vdd_1v8_ldo: LDO_REG7 {
324 regulator-name = "vdd_1v8_ldo";
327 regulator-min-microvolt = <1800000>;
328 regulator-max-microvolt = <1800000>;
329 regulator-state-mem {
330 regulator-off-in-suspend;
331 regulator-suspend-microvolt = <1800000>;
336 vdd_io_sd: LDO_REG9 {
337 regulator-name = "vdd_io_sd";
340 regulator-min-microvolt = <1800000>;
341 regulator-max-microvolt = <3300000>;
342 regulator-state-mem {
343 regulator-off-in-suspend;
350 i2c_eeprom: eeprom@50 {
351 compatible = "atmel,24c32";
356 vdd_cpu: regulator@60 {
357 compatible = "fcs,fan53555";
359 fcs,suspend-voltage-selector = <1>;
362 regulator-enable-ramp-delay = <300>;
363 regulator-name = "vdd_cpu";
364 regulator-min-microvolt = <800000>;
365 regulator-max-microvolt = <1430000>;
366 regulator-ramp-delay = <8000>;
367 vin-supply = <&vdd_sys>;
372 pcfg_output_high: pcfg-output-high {
378 * We run eMMC at max speed; bump up drive strength.
379 * We also have external pulls, so disable the internal ones.
382 rockchip,pins = <3 18 RK_FUNC_2 &pcfg_pull_none_12ma>;
386 rockchip,pins = <3 16 RK_FUNC_2 &pcfg_pull_none_12ma>;
389 emmc_bus8: emmc-bus8 {
390 rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_none_12ma>,
391 <3 1 RK_FUNC_2 &pcfg_pull_none_12ma>,
392 <3 2 RK_FUNC_2 &pcfg_pull_none_12ma>,
393 <3 3 RK_FUNC_2 &pcfg_pull_none_12ma>,
394 <3 4 RK_FUNC_2 &pcfg_pull_none_12ma>,
395 <3 5 RK_FUNC_2 &pcfg_pull_none_12ma>,
396 <3 6 RK_FUNC_2 &pcfg_pull_none_12ma>,
397 <3 7 RK_FUNC_2 &pcfg_pull_none_12ma>;
403 rockchip,pins = <4 2 RK_FUNC_GPIO &pcfg_pull_up>;
407 rockchip,pins = <4 8 RK_FUNC_GPIO &pcfg_output_high>;
413 rockchip,pins = <7 2 RK_FUNC_GPIO &pcfg_output_high>;
419 rockchip,pins = <RK_GPIO0 4 RK_FUNC_GPIO &pcfg_pull_up>;
422 /* Pin for switching state between sleep and non-sleep state */
423 pmic_sleep: pmic-sleep {
424 rockchip,pins = <RK_GPIO0 0 RK_FUNC_GPIO &pcfg_pull_up>;
435 vref-supply = <&vdd_1v8_ldo>;
441 serial_flash: flash@0 {
442 compatible = "micron,n25q128a13", "jedec,spi-nor";
444 spi-max-frequency = <50000000>;
446 #address-cells = <1>;
454 rockchip,hw-tshut-mode = <0>;
455 rockchip,hw-tshut-polarity = <0>;