sys/gnu/dts/arm/rk3288.dtsi

   1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
   2
   3 #include <dt-bindings/gpio/gpio.h>
   4 #include <dt-bindings/interrupt-controller/irq.h>
   5 #include <dt-bindings/interrupt-controller/arm-gic.h>
   6 #include <dt-bindings/pinctrl/rockchip.h>
   7 #include <dt-bindings/clock/rk3288-cru.h>
   8 #include <dt-bindings/power/rk3288-power.h>
   9 #include <dt-bindings/thermal/thermal.h>
  10 #include <dt-bindings/soc/rockchip,boot-mode.h>
  11
  12 / {
  13         #address-cells = <2>;
  14         #size-cells = <2>;
  15
  16         compatible = "rockchip,rk3288";
  17
  18         interrupt-parent = <&gic>;
  19
  20         aliases {
  21                 ethernet0 = &gmac;
  22                 i2c0 = &i2c0;
  23                 i2c1 = &i2c1;
  24                 i2c2 = &i2c2;
  25                 i2c3 = &i2c3;
  26                 i2c4 = &i2c4;
  27                 i2c5 = &i2c5;
  28                 mshc0 = &emmc;
  29                 mshc1 = &sdmmc;
  30                 mshc2 = &sdio0;
  31                 mshc3 = &sdio1;
  32                 serial0 = &uart0;
  33                 serial1 = &uart1;
  34                 serial2 = &uart2;
  35                 serial3 = &uart3;
  36                 serial4 = &uart4;
  37                 spi0 = &spi0;
  38                 spi1 = &spi1;
  39                 spi2 = &spi2;
  40         };
  41
  42         arm-pmu {
  43                 compatible = "arm,cortex-a12-pmu";
  44                 interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>,
  45                              <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
  46                              <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
  47                              <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
  48                 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
  49         };
  50
  51         cpus {
  52                 #address-cells = <1>;
  53                 #size-cells = <0>;
  54                 enable-method = "rockchip,rk3066-smp";
  55                 rockchip,pmu = <&pmu>;
  56
  57                 cpu0: cpu@500 {
  58                         device_type = "cpu";
  59                         compatible = "arm,cortex-a12";
  60                         reg = <0x500>;
  61                         resets = <&cru SRST_CORE0>;
  62                         operating-points-v2 = <&cpu_opp_table>;
  63                         #cooling-cells = <2>; /* min followed by max */
  64                         clock-latency = <40000>;
  65                         clocks = <&cru ARMCLK>;
  66                         dynamic-power-coefficient = <370>;
  67                 };
  68                 cpu1: cpu@501 {
  69                         device_type = "cpu";
  70                         compatible = "arm,cortex-a12";
  71                         reg = <0x501>;
  72                         resets = <&cru SRST_CORE1>;
  73                         operating-points-v2 = <&cpu_opp_table>;
  74                         #cooling-cells = <2>; /* min followed by max */
  75                         clock-latency = <40000>;
  76                         clocks = <&cru ARMCLK>;
  77                         dynamic-power-coefficient = <370>;
  78                 };
  79                 cpu2: cpu@502 {
  80                         device_type = "cpu";
  81                         compatible = "arm,cortex-a12";
  82                         reg = <0x502>;
  83                         resets = <&cru SRST_CORE2>;
  84                         operating-points-v2 = <&cpu_opp_table>;
  85                         #cooling-cells = <2>; /* min followed by max */
  86                         clock-latency = <40000>;
  87                         clocks = <&cru ARMCLK>;
  88                         dynamic-power-coefficient = <370>;
  89                 };
  90                 cpu3: cpu@503 {
  91                         device_type = "cpu";
  92                         compatible = "arm,cortex-a12";
  93                         reg = <0x503>;
  94                         resets = <&cru SRST_CORE3>;
  95                         operating-points-v2 = <&cpu_opp_table>;
  96                         #cooling-cells = <2>; /* min followed by max */
  97                         clock-latency = <40000>;
  98                         clocks = <&cru ARMCLK>;
  99                         dynamic-power-coefficient = <370>;
 100                 };
 101         };
 102
 103         cpu_opp_table: cpu-opp-table {
 104                 compatible = "operating-points-v2";
 105                 opp-shared;
 106
 107                 opp-126000000 {
 108                         opp-hz = /bits/ 64 <126000000>;
 109                         opp-microvolt = <900000>;
 110                 };
 111                 opp-216000000 {
 112                         opp-hz = /bits/ 64 <216000000>;
 113                         opp-microvolt = <900000>;
 114                 };
 115                 opp-312000000 {
 116                         opp-hz = /bits/ 64 <312000000>;
 117                         opp-microvolt = <900000>;
 118                 };
 119                 opp-408000000 {
 120                         opp-hz = /bits/ 64 <408000000>;
 121                         opp-microvolt = <900000>;
 122                 };
 123                 opp-600000000 {
 124                         opp-hz = /bits/ 64 <600000000>;
 125                         opp-microvolt = <900000>;
 126                 };
 127                 opp-696000000 {
 128                         opp-hz = /bits/ 64 <696000000>;
 129                         opp-microvolt = <950000>;
 130                 };
 131                 opp-816000000 {
 132                         opp-hz = /bits/ 64 <816000000>;
 133                         opp-microvolt = <1000000>;
 134                 };
 135                 opp-1008000000 {
 136                         opp-hz = /bits/ 64 <1008000000>;
 137                         opp-microvolt = <1050000>;
 138                 };
 139                 opp-1200000000 {
 140                         opp-hz = /bits/ 64 <1200000000>;
 141                         opp-microvolt = <1100000>;
 142                 };
 143                 opp-1416000000 {
 144                         opp-hz = /bits/ 64 <1416000000>;
 145                         opp-microvolt = <1200000>;
 146                 };
 147                 opp-1512000000 {
 148                         opp-hz = /bits/ 64 <1512000000>;
 149                         opp-microvolt = <1300000>;
 150                 };
 151                 opp-1608000000 {
 152                         opp-hz = /bits/ 64 <1608000000>;
 153                         opp-microvolt = <1350000>;
 154                 };
 155         };
 156
 157         amba: bus {
 158                 compatible = "simple-bus";
 159                 #address-cells = <2>;
 160                 #size-cells = <2>;
 161                 ranges;
 162
 163                 dmac_peri: dma-controller@ff250000 {
 164                         compatible = "arm,pl330", "arm,primecell";
 165                         reg = <0x0 0xff250000 0x0 0x4000>;
 166                         interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
 167                                      <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
 168                         #dma-cells = <1>;
 169                         arm,pl330-broken-no-flushp;
 170                         clocks = <&cru ACLK_DMAC2>;
 171                         clock-names = "apb_pclk";
 172                 };
 173
 174                 dmac_bus_ns: dma-controller@ff600000 {
 175                         compatible = "arm,pl330", "arm,primecell";
 176                         reg = <0x0 0xff600000 0x0 0x4000>;
 177                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 178                                      <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 179                         #dma-cells = <1>;
 180                         arm,pl330-broken-no-flushp;
 181                         clocks = <&cru ACLK_DMAC1>;
 182                         clock-names = "apb_pclk";
 183                         status = "disabled";
 184                 };
 185
 186                 dmac_bus_s: dma-controller@ffb20000 {
 187                         compatible = "arm,pl330", "arm,primecell";
 188                         reg = <0x0 0xffb20000 0x0 0x4000>;
 189                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 190                                      <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 191                         #dma-cells = <1>;
 192                         arm,pl330-broken-no-flushp;
 193                         clocks = <&cru ACLK_DMAC1>;
 194                         clock-names = "apb_pclk";
 195                 };
 196         };
 197
 198         reserved-memory {
 199                 #address-cells = <2>;
 200                 #size-cells = <2>;
 201                 ranges;
 202
 203                 /*
 204                  * The rk3288 cannot use the memory area above 0xfe000000
 205                  * for dma operations for some reason. While there is
 206                  * probably a better solution available somewhere, we
 207                  * haven't found it yet and while devices with 2GB of ram
 208                  * are not affected, this issue prevents 4GB from booting.
 209                  * So to make these devices at least bootable, block
 210                  * this area for the time being until the real solution
 211                  * is found.
 212                  */
 213                 dma-unusable@fe000000 {
 214                         reg = <0x0 0xfe000000 0x0 0x1000000>;
 215                 };
 216         };
 217
 218         xin24m: oscillator {
 219                 compatible = "fixed-clock";
 220                 clock-frequency = <24000000>;
 221                 clock-output-names = "xin24m";
 222                 #clock-cells = <0>;
 223         };
 224
 225         timer {
 226                 compatible = "arm,armv7-timer";
 227                 arm,cpu-registers-not-fw-configured;
 228                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 229                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 230                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 231                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 232                 clock-frequency = <24000000>;
 233                 arm,no-tick-in-suspend;
 234         };
 235
 236         timer: timer@ff810000 {
 237                 compatible = "rockchip,rk3288-timer";
 238                 reg = <0x0 0xff810000 0x0 0x20>;
 239                 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
 240                 clocks = <&xin24m>, <&cru PCLK_TIMER>;
 241                 clock-names = "timer", "pclk";
 242         };
 243
 244         display-subsystem {
 245                 compatible = "rockchip,display-subsystem";
 246                 ports = <&vopl_out>, <&vopb_out>;
 247         };
 248
 249         sdmmc: mmc@ff0c0000 {
 250                 compatible = "rockchip,rk3288-dw-mshc";
 251                 max-frequency = <150000000>;
 252                 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
 253                          <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
 254                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 255                 fifo-depth = <0x100>;
 256                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 257                 reg = <0x0 0xff0c0000 0x0 0x4000>;
 258                 resets = <&cru SRST_MMC0>;
 259                 reset-names = "reset";
 260                 status = "disabled";
 261         };
 262
 263         sdio0: mmc@ff0d0000 {
 264                 compatible = "rockchip,rk3288-dw-mshc";
 265                 max-frequency = <150000000>;
 266                 clocks = <&cru HCLK_SDIO0>, <&cru SCLK_SDIO0>,
 267                          <&cru SCLK_SDIO0_DRV>, <&cru SCLK_SDIO0_SAMPLE>;
 268                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 269                 fifo-depth = <0x100>;
 270                 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
 271                 reg = <0x0 0xff0d0000 0x0 0x4000>;
 272                 resets = <&cru SRST_SDIO0>;
 273                 reset-names = "reset";
 274                 status = "disabled";
 275         };
 276
 277         sdio1: mmc@ff0e0000 {
 278                 compatible = "rockchip,rk3288-dw-mshc";
 279                 max-frequency = <150000000>;
 280                 clocks = <&cru HCLK_SDIO1>, <&cru SCLK_SDIO1>,
 281                          <&cru SCLK_SDIO1_DRV>, <&cru SCLK_SDIO1_SAMPLE>;
 282                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 283                 fifo-depth = <0x100>;
 284                 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
 285                 reg = <0x0 0xff0e0000 0x0 0x4000>;
 286                 resets = <&cru SRST_SDIO1>;
 287                 reset-names = "reset";
 288                 status = "disabled";
 289         };
 290
 291         emmc: mmc@ff0f0000 {
 292                 compatible = "rockchip,rk3288-dw-mshc";
 293                 max-frequency = <150000000>;
 294                 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
 295                          <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
 296                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 297                 fifo-depth = <0x100>;
 298                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 299                 reg = <0x0 0xff0f0000 0x0 0x4000>;
 300                 resets = <&cru SRST_EMMC>;
 301                 reset-names = "reset";
 302                 status = "disabled";
 303         };
 304
 305         saradc: saradc@ff100000 {
 306                 compatible = "rockchip,saradc";
 307                 reg = <0x0 0xff100000 0x0 0x100>;
 308                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 309                 #io-channel-cells = <1>;
 310                 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
 311                 clock-names = "saradc", "apb_pclk";
 312                 resets = <&cru SRST_SARADC>;
 313                 reset-names = "saradc-apb";
 314                 status = "disabled";
 315         };
 316
 317         spi0: spi@ff110000 {
 318                 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
 319                 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
 320                 clock-names = "spiclk", "apb_pclk";
 321                 dmas = <&dmac_peri 11>, <&dmac_peri 12>;
 322                 dma-names = "tx", "rx";
 323                 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
 324                 pinctrl-names = "default";
 325                 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
 326                 reg = <0x0 0xff110000 0x0 0x1000>;
 327                 #address-cells = <1>;
 328                 #size-cells = <0>;
 329                 status = "disabled";
 330         };
 331
 332         spi1: spi@ff120000 {
 333                 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
 334                 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
 335                 clock-names = "spiclk", "apb_pclk";
 336                 dmas = <&dmac_peri 13>, <&dmac_peri 14>;
 337                 dma-names = "tx", "rx";
 338                 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
 339                 pinctrl-names = "default";
 340                 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
 341                 reg = <0x0 0xff120000 0x0 0x1000>;
 342                 #address-cells = <1>;
 343                 #size-cells = <0>;
 344                 status = "disabled";
 345         };
 346
 347         spi2: spi@ff130000 {
 348                 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
 349                 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
 350                 clock-names = "spiclk", "apb_pclk";
 351                 dmas = <&dmac_peri 15>, <&dmac_peri 16>;
 352                 dma-names = "tx", "rx";
 353                 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
 354                 pinctrl-names = "default";
 355                 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
 356                 reg = <0x0 0xff130000 0x0 0x1000>;
 357                 #address-cells = <1>;
 358                 #size-cells = <0>;
 359                 status = "disabled";
 360         };
 361
 362         i2c1: i2c@ff140000 {
 363                 compatible = "rockchip,rk3288-i2c";
 364                 reg = <0x0 0xff140000 0x0 0x1000>;
 365                 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
 366                 #address-cells = <1>;
 367                 #size-cells = <0>;
 368                 clock-names = "i2c";
 369                 clocks = <&cru PCLK_I2C1>;
 370                 pinctrl-names = "default";
 371                 pinctrl-0 = <&i2c1_xfer>;
 372                 status = "disabled";
 373         };
 374
 375         i2c3: i2c@ff150000 {
 376                 compatible = "rockchip,rk3288-i2c";
 377                 reg = <0x0 0xff150000 0x0 0x1000>;
 378                 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
 379                 #address-cells = <1>;
 380                 #size-cells = <0>;
 381                 clock-names = "i2c";
 382                 clocks = <&cru PCLK_I2C3>;
 383                 pinctrl-names = "default";
 384                 pinctrl-0 = <&i2c3_xfer>;
 385                 status = "disabled";
 386         };
 387
 388         i2c4: i2c@ff160000 {
 389                 compatible = "rockchip,rk3288-i2c";
 390                 reg = <0x0 0xff160000 0x0 0x1000>;
 391                 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
 392                 #address-cells = <1>;
 393                 #size-cells = <0>;
 394                 clock-names = "i2c";
 395                 clocks = <&cru PCLK_I2C4>;
 396                 pinctrl-names = "default";
 397                 pinctrl-0 = <&i2c4_xfer>;
 398                 status = "disabled";
 399         };
 400
 401         i2c5: i2c@ff170000 {
 402                 compatible = "rockchip,rk3288-i2c";
 403                 reg = <0x0 0xff170000 0x0 0x1000>;
 404                 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
 405                 #address-cells = <1>;
 406                 #size-cells = <0>;
 407                 clock-names = "i2c";
 408                 clocks = <&cru PCLK_I2C5>;
 409                 pinctrl-names = "default";
 410                 pinctrl-0 = <&i2c5_xfer>;
 411                 status = "disabled";
 412         };
 413
 414         uart0: serial@ff180000 {
 415                 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
 416                 reg = <0x0 0xff180000 0x0 0x100>;
 417                 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
 418                 reg-shift = <2>;
 419                 reg-io-width = <4>;
 420                 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
 421                 clock-names = "baudclk", "apb_pclk";
 422                 dmas = <&dmac_peri 1>, <&dmac_peri 2>;
 423                 dma-names = "tx", "rx";
 424                 pinctrl-names = "default";
 425                 pinctrl-0 = <&uart0_xfer>;
 426                 status = "disabled";
 427         };
 428
 429         uart1: serial@ff190000 {
 430                 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
 431                 reg = <0x0 0xff190000 0x0 0x100>;
 432                 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
 433                 reg-shift = <2>;
 434                 reg-io-width = <4>;
 435                 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
 436                 clock-names = "baudclk", "apb_pclk";
 437                 dmas = <&dmac_peri 3>, <&dmac_peri 4>;
 438                 dma-names = "tx", "rx";
 439                 pinctrl-names = "default";
 440                 pinctrl-0 = <&uart1_xfer>;
 441                 status = "disabled";
 442         };
 443
 444         uart2: serial@ff690000 {
 445                 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
 446                 reg = <0x0 0xff690000 0x0 0x100>;
 447                 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
 448                 reg-shift = <2>;
 449                 reg-io-width = <4>;
 450                 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
 451                 clock-names = "baudclk", "apb_pclk";
 452                 pinctrl-names = "default";
 453                 pinctrl-0 = <&uart2_xfer>;
 454                 status = "disabled";
 455         };
 456
 457         uart3: serial@ff1b0000 {
 458                 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
 459                 reg = <0x0 0xff1b0000 0x0 0x100>;
 460                 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
 461                 reg-shift = <2>;
 462                 reg-io-width = <4>;
 463                 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
 464                 clock-names = "baudclk", "apb_pclk";
 465                 dmas = <&dmac_peri 7>, <&dmac_peri 8>;
 466                 dma-names = "tx", "rx";
 467                 pinctrl-names = "default";
 468                 pinctrl-0 = <&uart3_xfer>;
 469                 status = "disabled";
 470         };
 471
 472         uart4: serial@ff1c0000 {
 473                 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
 474                 reg = <0x0 0xff1c0000 0x0 0x100>;
 475                 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
 476                 reg-shift = <2>;
 477                 reg-io-width = <4>;
 478                 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
 479                 clock-names = "baudclk", "apb_pclk";
 480                 dmas = <&dmac_peri 9>, <&dmac_peri 10>;
 481                 dma-names = "tx", "rx";
 482                 pinctrl-names = "default";
 483                 pinctrl-0 = <&uart4_xfer>;
 484                 status = "disabled";
 485         };
 486
 487         thermal-zones {
 488                 reserve_thermal: reserve_thermal {
 489                         polling-delay-passive = <1000>; /* milliseconds */
 490                         polling-delay = <5000>; /* milliseconds */
 491
 492                         thermal-sensors = <&tsadc 0>;
 493                 };
 494
 495                 cpu_thermal: cpu_thermal {
 496                         polling-delay-passive = <100>; /* milliseconds */
 497                         polling-delay = <5000>; /* milliseconds */
 498
 499                         thermal-sensors = <&tsadc 1>;
 500
 501                         trips {
 502                                 cpu_alert0: cpu_alert0 {
 503                                         temperature = <70000>; /* millicelsius */
 504                                         hysteresis = <2000>; /* millicelsius */
 505                                         type = "passive";
 506                                 };
 507                                 cpu_alert1: cpu_alert1 {
 508                                         temperature = <75000>; /* millicelsius */
 509                                         hysteresis = <2000>; /* millicelsius */
 510                                         type = "passive";
 511                                 };
 512                                 cpu_crit: cpu_crit {
 513                                         temperature = <90000>; /* millicelsius */
 514                                         hysteresis = <2000>; /* millicelsius */
 515                                         type = "critical";
 516                                 };
 517                         };
 518
 519                         cooling-maps {
 520                                 map0 {
 521                                         trip = <&cpu_alert0>;
 522                                         cooling-device =
 523                                                 <&cpu0 THERMAL_NO_LIMIT 6>,
 524                                                 <&cpu1 THERMAL_NO_LIMIT 6>,
 525                                                 <&cpu2 THERMAL_NO_LIMIT 6>,
 526                                                 <&cpu3 THERMAL_NO_LIMIT 6>;
 527                                 };
 528                                 map1 {
 529                                         trip = <&cpu_alert1>;
 530                                         cooling-device =
 531                                                 <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 532                                                 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 533                                                 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 534                                                 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 535                                 };
 536                         };
 537                 };
 538
 539                 gpu_thermal: gpu_thermal {
 540                         polling-delay-passive = <100>; /* milliseconds */
 541                         polling-delay = <5000>; /* milliseconds */
 542
 543                         thermal-sensors = <&tsadc 2>;
 544
 545                         trips {
 546                                 gpu_alert0: gpu_alert0 {
 547                                         temperature = <70000>; /* millicelsius */
 548                                         hysteresis = <2000>; /* millicelsius */
 549                                         type = "passive";
 550                                 };
 551                                 gpu_crit: gpu_crit {
 552                                         temperature = <90000>; /* millicelsius */
 553                                         hysteresis = <2000>; /* millicelsius */
 554                                         type = "critical";
 555                                 };
 556                         };
 557
 558                         cooling-maps {
 559                                 map0 {
 560                                         trip = <&gpu_alert0>;
 561                                         cooling-device =
 562                                                 <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 563                                 };
 564                         };
 565                 };
 566         };
 567
 568         tsadc: tsadc@ff280000 {
 569                 compatible = "rockchip,rk3288-tsadc";
 570                 reg = <0x0 0xff280000 0x0 0x100>;
 571                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 572                 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
 573                 clock-names = "tsadc", "apb_pclk";
 574                 resets = <&cru SRST_TSADC>;
 575                 reset-names = "tsadc-apb";
 576                 pinctrl-names = "init", "default", "sleep";
 577                 pinctrl-0 = <&otp_gpio>;
 578                 pinctrl-1 = <&otp_out>;
 579                 pinctrl-2 = <&otp_gpio>;
 580                 #thermal-sensor-cells = <1>;
 581                 rockchip,grf = <&grf>;
 582                 rockchip,hw-tshut-temp = <95000>;
 583                 status = "disabled";
 584         };
 585
 586         gmac: ethernet@ff290000 {
 587                 compatible = "rockchip,rk3288-gmac";
 588                 reg = <0x0 0xff290000 0x0 0x10000>;
 589                 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,
 590                                 <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
 591                 interrupt-names = "macirq", "eth_wake_irq";
 592                 rockchip,grf = <&grf>;
 593                 clocks = <&cru SCLK_MAC>,
 594                         <&cru SCLK_MAC_RX>, <&cru SCLK_MAC_TX>,
 595                         <&cru SCLK_MACREF>, <&cru SCLK_MACREF_OUT>,
 596                         <&cru ACLK_GMAC>, <&cru PCLK_GMAC>;
 597                 clock-names = "stmmaceth",
 598                         "mac_clk_rx", "mac_clk_tx",
 599                         "clk_mac_ref", "clk_mac_refout",
 600                         "aclk_mac", "pclk_mac";
 601                 resets = <&cru SRST_MAC>;
 602                 reset-names = "stmmaceth";
 603                 status = "disabled";
 604         };
 605
 606         usb_host0_ehci: usb@ff500000 {
 607                 compatible = "generic-ehci";
 608                 reg = <0x0 0xff500000 0x0 0x100>;
 609                 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
 610                 clocks = <&cru HCLK_USBHOST0>;
 611                 phys = <&usbphy1>;
 612                 phy-names = "usb";
 613                 status = "disabled";
 614         };
 615
 616         /* NOTE: ohci@ff520000 doesn't actually work on hardware */
 617
 618         usb_host1: usb@ff540000 {
 619                 compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb",
 620                                 "snps,dwc2";
 621                 reg = <0x0 0xff540000 0x0 0x40000>;
 622                 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
 623                 clocks = <&cru HCLK_USBHOST1>;
 624                 clock-names = "otg";
 625                 dr_mode = "host";
 626                 phys = <&usbphy2>;
 627                 phy-names = "usb2-phy";
 628                 snps,reset-phy-on-wake;
 629                 status = "disabled";
 630         };
 631
 632         usb_otg: usb@ff580000 {
 633                 compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb",
 634                                 "snps,dwc2";
 635                 reg = <0x0 0xff580000 0x0 0x40000>;
 636                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 637                 clocks = <&cru HCLK_OTG0>;
 638                 clock-names = "otg";
 639                 dr_mode = "otg";
 640                 g-np-tx-fifo-size = <16>;
 641                 g-rx-fifo-size = <275>;
 642                 g-tx-fifo-size = <256 128 128 64 64 32>;
 643                 phys = <&usbphy0>;
 644                 phy-names = "usb2-phy";
 645                 status = "disabled";
 646         };
 647
 648         usb_hsic: usb@ff5c0000 {
 649                 compatible = "generic-ehci";
 650                 reg = <0x0 0xff5c0000 0x0 0x100>;
 651                 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
 652                 clocks = <&cru HCLK_HSIC>;
 653                 status = "disabled";
 654         };
 655
 656         i2c0: i2c@ff650000 {
 657                 compatible = "rockchip,rk3288-i2c";
 658                 reg = <0x0 0xff650000 0x0 0x1000>;
 659                 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
 660                 #address-cells = <1>;
 661                 #size-cells = <0>;
 662                 clock-names = "i2c";
 663                 clocks = <&cru PCLK_I2C0>;
 664                 pinctrl-names = "default";
 665                 pinctrl-0 = <&i2c0_xfer>;
 666                 status = "disabled";
 667         };
 668
 669         i2c2: i2c@ff660000 {
 670                 compatible = "rockchip,rk3288-i2c";
 671                 reg = <0x0 0xff660000 0x0 0x1000>;
 672                 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
 673                 #address-cells = <1>;
 674                 #size-cells = <0>;
 675                 clock-names = "i2c";
 676                 clocks = <&cru PCLK_I2C2>;
 677                 pinctrl-names = "default";
 678                 pinctrl-0 = <&i2c2_xfer>;
 679                 status = "disabled";
 680         };
 681
 682         pwm0: pwm@ff680000 {
 683                 compatible = "rockchip,rk3288-pwm";
 684                 reg = <0x0 0xff680000 0x0 0x10>;
 685                 #pwm-cells = <3>;
 686                 pinctrl-names = "default";
 687                 pinctrl-0 = <&pwm0_pin>;
 688                 clocks = <&cru PCLK_RKPWM>;
 689                 clock-names = "pwm";
 690                 status = "disabled";
 691         };
 692
 693         pwm1: pwm@ff680010 {
 694                 compatible = "rockchip,rk3288-pwm";
 695                 reg = <0x0 0xff680010 0x0 0x10>;
 696                 #pwm-cells = <3>;
 697                 pinctrl-names = "default";
 698                 pinctrl-0 = <&pwm1_pin>;
 699                 clocks = <&cru PCLK_RKPWM>;
 700                 clock-names = "pwm";
 701                 status = "disabled";
 702         };
 703
 704         pwm2: pwm@ff680020 {
 705                 compatible = "rockchip,rk3288-pwm";
 706                 reg = <0x0 0xff680020 0x0 0x10>;
 707                 #pwm-cells = <3>;
 708                 pinctrl-names = "default";
 709                 pinctrl-0 = <&pwm2_pin>;
 710                 clocks = <&cru PCLK_RKPWM>;
 711                 clock-names = "pwm";
 712                 status = "disabled";
 713         };
 714
 715         pwm3: pwm@ff680030 {
 716                 compatible = "rockchip,rk3288-pwm";
 717                 reg = <0x0 0xff680030 0x0 0x10>;
 718                 #pwm-cells = <3>;
 719                 pinctrl-names = "default";
 720                 pinctrl-0 = <&pwm3_pin>;
 721                 clocks = <&cru PCLK_RKPWM>;
 722                 clock-names = "pwm";
 723                 status = "disabled";
 724         };
 725
 726         bus_intmem: sram@ff700000 {
 727                 compatible = "mmio-sram";
 728                 reg = <0x0 0xff700000 0x0 0x18000>;
 729                 #address-cells = <1>;
 730                 #size-cells = <1>;
 731                 ranges = <0 0x0 0xff700000 0x18000>;
 732                 smp-sram@0 {
 733                         compatible = "rockchip,rk3066-smp-sram";
 734                         reg = <0x00 0x10>;
 735                 };
 736         };
 737
 738         pmu_sram: sram@ff720000 {
 739                 compatible = "rockchip,rk3288-pmu-sram", "mmio-sram";
 740                 reg = <0x0 0xff720000 0x0 0x1000>;
 741         };
 742
 743         pmu: power-management@ff730000 {
 744                 compatible = "rockchip,rk3288-pmu", "syscon", "simple-mfd";
 745                 reg = <0x0 0xff730000 0x0 0x100>;
 746
 747                 power: power-controller {
 748                         compatible = "rockchip,rk3288-power-controller";
 749                         #power-domain-cells = <1>;
 750                         #address-cells = <1>;
 751                         #size-cells = <0>;
 752
 753                         assigned-clocks = <&cru SCLK_EDP_24M>;
 754                         assigned-clock-parents = <&xin24m>;
 755
 756                         /*
 757                          * Note: Although SCLK_* are the working clocks
 758                          * of device without including on the NOC, needed for
 759                          * synchronous reset.
 760                          *
 761                          * The clocks on the which NOC:
 762                          * ACLK_IEP/ACLK_VIP/ACLK_VOP0 are on ACLK_VIO0_NIU.
 763                          * ACLK_ISP/ACLK_VOP1 are on ACLK_VIO1_NIU.
 764                          * ACLK_RGA is on ACLK_RGA_NIU.
 765                          * The others (HCLK_*,PLCK_*) are on HCLK_VIO_NIU.
 766                          *
 767                          * Which clock are device clocks:
 768                          *      clocks          devices
 769                          *      *_IEP           IEP:Image Enhancement Processor
 770                          *      *_ISP           ISP:Image Signal Processing
 771                          *      *_VIP           VIP:Video Input Processor
 772                          *      *_VOP*          VOP:Visual Output Processor
 773                          *      *_RGA           RGA
 774                          *      *_EDP*          EDP
 775                          *      *_LVDS_*        LVDS
 776                          *      *_HDMI          HDMI
 777                          *      *_MIPI_*        MIPI
 778                          */
 779                         pd_vio@RK3288_PD_VIO {
 780                                 reg = <RK3288_PD_VIO>;
 781                                 clocks = <&cru ACLK_IEP>,
 782                                          <&cru ACLK_ISP>,
 783                                          <&cru ACLK_RGA>,
 784                                          <&cru ACLK_VIP>,
 785                                          <&cru ACLK_VOP0>,
 786                                          <&cru ACLK_VOP1>,
 787                                          <&cru DCLK_VOP0>,
 788                                          <&cru DCLK_VOP1>,
 789                                          <&cru HCLK_IEP>,
 790                                          <&cru HCLK_ISP>,
 791                                          <&cru HCLK_RGA>,
 792                                          <&cru HCLK_VIP>,
 793                                          <&cru HCLK_VOP0>,
 794                                          <&cru HCLK_VOP1>,
 795                                          <&cru PCLK_EDP_CTRL>,
 796                                          <&cru PCLK_HDMI_CTRL>,
 797                                          <&cru PCLK_LVDS_PHY>,
 798                                          <&cru PCLK_MIPI_CSI>,
 799                                          <&cru PCLK_MIPI_DSI0>,
 800                                          <&cru PCLK_MIPI_DSI1>,
 801                                          <&cru SCLK_EDP_24M>,
 802                                          <&cru SCLK_EDP>,
 803                                          <&cru SCLK_ISP_JPE>,
 804                                          <&cru SCLK_ISP>,
 805                                          <&cru SCLK_RGA>;
 806                                 pm_qos = <&qos_vio0_iep>,
 807                                          <&qos_vio1_vop>,
 808                                          <&qos_vio1_isp_w0>,
 809                                          <&qos_vio1_isp_w1>,
 810                                          <&qos_vio0_vop>,
 811                                          <&qos_vio0_vip>,
 812                                          <&qos_vio2_rga_r>,
 813                                          <&qos_vio2_rga_w>,
 814                                          <&qos_vio1_isp_r>;
 815                         };
 816
 817                         /*
 818                          * Note: The following 3 are HEVC(H.265) clocks,
 819                          * and on the ACLK_HEVC_NIU (NOC).
 820                          */
 821                         pd_hevc@RK3288_PD_HEVC {
 822                                 reg = <RK3288_PD_HEVC>;
 823                                 clocks = <&cru ACLK_HEVC>,
 824                                          <&cru SCLK_HEVC_CABAC>,
 825                                          <&cru SCLK_HEVC_CORE>;
 826                                 pm_qos = <&qos_hevc_r>,
 827                                          <&qos_hevc_w>;
 828                         };
 829
 830                         /*
 831                          * Note: ACLK_VCODEC/HCLK_VCODEC are VCODEC
 832                          * (video endecoder & decoder) clocks that on the
 833                          * ACLK_VCODEC_NIU and HCLK_VCODEC_NIU (NOC).
 834                          */
 835                         pd_video@RK3288_PD_VIDEO {
 836                                 reg = <RK3288_PD_VIDEO>;
 837                                 clocks = <&cru ACLK_VCODEC>,
 838                                          <&cru HCLK_VCODEC>;
 839                                 pm_qos = <&qos_video>;
 840                         };
 841
 842                         /*
 843                          * Note: ACLK_GPU is the GPU clock,
 844                          * and on the ACLK_GPU_NIU (NOC).
 845                          */
 846                         pd_gpu@RK3288_PD_GPU {
 847                                 reg = <RK3288_PD_GPU>;
 848                                 clocks = <&cru ACLK_GPU>;
 849                                 pm_qos = <&qos_gpu_r>,
 850                                          <&qos_gpu_w>;
 851                         };
 852                 };
 853
 854                 reboot-mode {
 855                         compatible = "syscon-reboot-mode";
 856                         offset = <0x94>;
 857                         mode-normal = <BOOT_NORMAL>;
 858                         mode-recovery = <BOOT_RECOVERY>;
 859                         mode-bootloader = <BOOT_FASTBOOT>;
 860                         mode-loader = <BOOT_BL_DOWNLOAD>;
 861                 };
 862         };
 863
 864         sgrf: syscon@ff740000 {
 865                 compatible = "rockchip,rk3288-sgrf", "syscon";
 866                 reg = <0x0 0xff740000 0x0 0x1000>;
 867         };
 868
 869         cru: clock-controller@ff760000 {
 870                 compatible = "rockchip,rk3288-cru";
 871                 reg = <0x0 0xff760000 0x0 0x1000>;
 872                 rockchip,grf = <&grf>;
 873                 #clock-cells = <1>;
 874                 #reset-cells = <1>;
 875                 assigned-clocks = <&cru PLL_GPLL>, <&cru PLL_CPLL>,
 876                                   <&cru PLL_NPLL>, <&cru ACLK_CPU>,
 877                                   <&cru HCLK_CPU>, <&cru PCLK_CPU>,
 878                                   <&cru ACLK_PERI>, <&cru HCLK_PERI>,
 879                                   <&cru PCLK_PERI>;
 880                 assigned-clock-rates = <594000000>, <400000000>,
 881                                        <500000000>, <300000000>,
 882                                        <150000000>, <75000000>,
 883                                        <300000000>, <150000000>,
 884                                        <75000000>;
 885         };
 886
 887         grf: syscon@ff770000 {
 888                 compatible = "rockchip,rk3288-grf", "syscon", "simple-mfd";
 889                 reg = <0x0 0xff770000 0x0 0x1000>;
 890
 891                 edp_phy: edp-phy {
 892                         compatible = "rockchip,rk3288-dp-phy";
 893                         clocks = <&cru SCLK_EDP_24M>;
 894                         clock-names = "24m";
 895                         #phy-cells = <0>;
 896                         status = "disabled";
 897                 };
 898
 899                 io_domains: io-domains {
 900                         compatible = "rockchip,rk3288-io-voltage-domain";
 901                         status = "disabled";
 902                 };
 903
 904                 usbphy: usbphy {
 905                         compatible = "rockchip,rk3288-usb-phy";
 906                         #address-cells = <1>;
 907                         #size-cells = <0>;
 908                         status = "disabled";
 909
 910                         usbphy0: usb-phy@320 {
 911                                 #phy-cells = <0>;
 912                                 reg = <0x320>;
 913                                 clocks = <&cru SCLK_OTGPHY0>;
 914                                 clock-names = "phyclk";
 915                                 #clock-cells = <0>;
 916                                 resets = <&cru SRST_USBOTG_PHY>;
 917                                 reset-names = "phy-reset";
 918                         };
 919
 920                         usbphy1: usb-phy@334 {
 921                                 #phy-cells = <0>;
 922                                 reg = <0x334>;
 923                                 clocks = <&cru SCLK_OTGPHY1>;
 924                                 clock-names = "phyclk";
 925                                 #clock-cells = <0>;
 926                                 resets = <&cru SRST_USBHOST0_PHY>;
 927                                 reset-names = "phy-reset";
 928                         };
 929
 930                         usbphy2: usb-phy@348 {
 931                                 #phy-cells = <0>;
 932                                 reg = <0x348>;
 933                                 clocks = <&cru SCLK_OTGPHY2>;
 934                                 clock-names = "phyclk";
 935                                 #clock-cells = <0>;
 936                                 resets = <&cru SRST_USBHOST1_PHY>;
 937                                 reset-names = "phy-reset";
 938                         };
 939                 };
 940         };
 941
 942         wdt: watchdog@ff800000 {
 943                 compatible = "rockchip,rk3288-wdt", "snps,dw-wdt";
 944                 reg = <0x0 0xff800000 0x0 0x100>;
 945                 clocks = <&cru PCLK_WDT>;
 946                 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
 947                 status = "disabled";
 948         };
 949
 950         spdif: sound@ff88b0000 {
 951                 compatible = "rockchip,rk3288-spdif", "rockchip,rk3066-spdif";
 952                 reg = <0x0 0xff8b0000 0x0 0x10000>;
 953                 #sound-dai-cells = <0>;
 954                 clocks = <&cru SCLK_SPDIF8CH>, <&cru HCLK_SPDIF8CH>;
 955                 clock-names = "mclk", "hclk";
 956                 dmas = <&dmac_bus_s 3>;
 957                 dma-names = "tx";
 958                 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
 959                 pinctrl-names = "default";
 960                 pinctrl-0 = <&spdif_tx>;
 961                 rockchip,grf = <&grf>;
 962                 status = "disabled";
 963         };
 964
 965         i2s: i2s@ff890000 {
 966                 compatible = "rockchip,rk3288-i2s", "rockchip,rk3066-i2s";
 967                 reg = <0x0 0xff890000 0x0 0x10000>;
 968                 #sound-dai-cells = <0>;
 969                 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
 970                 clocks = <&cru SCLK_I2S0>, <&cru HCLK_I2S0>;
 971                 clock-names = "i2s_clk", "i2s_hclk";
 972                 dmas = <&dmac_bus_s 0>, <&dmac_bus_s 1>;
 973                 dma-names = "tx", "rx";
 974                 pinctrl-names = "default";
 975                 pinctrl-0 = <&i2s0_bus>;
 976                 rockchip,playback-channels = <8>;
 977                 rockchip,capture-channels = <2>;
 978                 status = "disabled";
 979         };
 980
 981         crypto: cypto-controller@ff8a0000 {
 982                 compatible = "rockchip,rk3288-crypto";
 983                 reg = <0x0 0xff8a0000 0x0 0x4000>;
 984                 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
 985                 clocks = <&cru ACLK_CRYPTO>, <&cru HCLK_CRYPTO>,
 986                          <&cru SCLK_CRYPTO>, <&cru ACLK_DMAC1>;
 987                 clock-names = "aclk", "hclk", "sclk", "apb_pclk";
 988                 resets = <&cru SRST_CRYPTO>;
 989                 reset-names = "crypto-rst";
 990                 status = "okay";
 991         };
 992
 993         iep_mmu: iommu@ff900800 {
 994                 compatible = "rockchip,iommu";
 995                 reg = <0x0 0xff900800 0x0 0x40>;
 996                 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
 997                 interrupt-names = "iep_mmu";
 998                 clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>;
 999                 clock-names = "aclk", "iface";
1000                 #iommu-cells = <0>;
1001                 status = "disabled";
1002         };
1003
1004         isp_mmu: iommu@ff914000 {
1005                 compatible = "rockchip,iommu";
1006                 reg = <0x0 0xff914000 0x0 0x100>, <0x0 0xff915000 0x0 0x100>;
1007                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1008                 interrupt-names = "isp_mmu";
1009                 clocks = <&cru ACLK_ISP>, <&cru HCLK_ISP>;
1010                 clock-names = "aclk", "iface";
1011                 #iommu-cells = <0>;
1012                 rockchip,disable-mmu-reset;
1013                 status = "disabled";
1014         };
1015
1016         rga: rga@ff920000 {
1017                 compatible = "rockchip,rk3288-rga";
1018                 reg = <0x0 0xff920000 0x0 0x180>;
1019                 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
1020                 clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA>;
1021                 clock-names = "aclk", "hclk", "sclk";
1022                 power-domains = <&power RK3288_PD_VIO>;
1023                 resets = <&cru SRST_RGA_CORE>, <&cru SRST_RGA_AXI>, <&cru SRST_RGA_AHB>;
1024                 reset-names = "core", "axi", "ahb";
1025         };
1026
1027         vopb: vop@ff930000 {
1028                 compatible = "rockchip,rk3288-vop";
1029                 reg = <0x0 0xff930000 0x0 0x19c>, <0x0 0xff931000 0x0 0x1000>;
1030                 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
1031                 clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>;
1032                 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
1033                 power-domains = <&power RK3288_PD_VIO>;
1034                 resets = <&cru SRST_LCDC0_AXI>, <&cru SRST_LCDC0_AHB>, <&cru SRST_LCDC0_DCLK>;
1035                 reset-names = "axi", "ahb", "dclk";
1036                 iommus = <&vopb_mmu>;
1037                 status = "disabled";
1038
1039                 vopb_out: port {
1040                         #address-cells = <1>;
1041                         #size-cells = <0>;
1042
1043                         vopb_out_hdmi: endpoint@0 {
1044                                 reg = <0>;
1045                                 remote-endpoint = <&hdmi_in_vopb>;
1046                         };
1047
1048                         vopb_out_edp: endpoint@1 {
1049                                 reg = <1>;
1050                                 remote-endpoint = <&edp_in_vopb>;
1051                         };
1052
1053                         vopb_out_mipi: endpoint@2 {
1054                                 reg = <2>;
1055                                 remote-endpoint = <&mipi_in_vopb>;
1056                         };
1057
1058                         vopb_out_lvds: endpoint@3 {
1059                                 reg = <3>;
1060                                 remote-endpoint = <&lvds_in_vopb>;
1061                         };
1062                 };
1063         };
1064
1065         vopb_mmu: iommu@ff930300 {
1066                 compatible = "rockchip,iommu";
1067                 reg = <0x0 0xff930300 0x0 0x100>;
1068                 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
1069                 interrupt-names = "vopb_mmu";
1070                 clocks = <&cru ACLK_VOP0>, <&cru HCLK_VOP0>;
1071                 clock-names = "aclk", "iface";
1072                 power-domains = <&power RK3288_PD_VIO>;
1073                 #iommu-cells = <0>;
1074                 status = "disabled";
1075         };
1076
1077         vopl: vop@ff940000 {
1078                 compatible = "rockchip,rk3288-vop";
1079                 reg = <0x0 0xff940000 0x0 0x19c>, <0x0 0xff941000 0x0 0x1000>;
1080                 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
1081                 clocks = <&cru ACLK_VOP1>, <&cru DCLK_VOP1>, <&cru HCLK_VOP1>;
1082                 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
1083                 power-domains = <&power RK3288_PD_VIO>;
1084                 resets = <&cru SRST_LCDC1_AXI>, <&cru SRST_LCDC1_AHB>, <&cru SRST_LCDC1_DCLK>;
1085                 reset-names = "axi", "ahb", "dclk";
1086                 iommus = <&vopl_mmu>;
1087                 status = "disabled";
1088
1089                 vopl_out: port {
1090                         #address-cells = <1>;
1091                         #size-cells = <0>;
1092
1093                         vopl_out_hdmi: endpoint@0 {
1094                                 reg = <0>;
1095                                 remote-endpoint = <&hdmi_in_vopl>;
1096                         };
1097
1098                         vopl_out_edp: endpoint@1 {
1099                                 reg = <1>;
1100                                 remote-endpoint = <&edp_in_vopl>;
1101                         };
1102
1103                         vopl_out_mipi: endpoint@2 {
1104                                 reg = <2>;
1105                                 remote-endpoint = <&mipi_in_vopl>;
1106                         };
1107
1108                         vopl_out_lvds: endpoint@3 {
1109                                 reg = <3>;
1110                                 remote-endpoint = <&lvds_in_vopl>;
1111                         };
1112                 };
1113         };
1114
1115         vopl_mmu: iommu@ff940300 {
1116                 compatible = "rockchip,iommu";
1117                 reg = <0x0 0xff940300 0x0 0x100>;
1118                 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
1119                 interrupt-names = "vopl_mmu";
1120                 clocks = <&cru ACLK_VOP1>, <&cru HCLK_VOP1>;
1121                 clock-names = "aclk", "iface";
1122                 power-domains = <&power RK3288_PD_VIO>;
1123                 #iommu-cells = <0>;
1124                 status = "disabled";
1125         };
1126
1127         mipi_dsi: mipi@ff960000 {
1128                 compatible = "rockchip,rk3288-mipi-dsi", "snps,dw-mipi-dsi";
1129                 reg = <0x0 0xff960000 0x0 0x4000>;
1130                 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
1131                 clocks = <&cru SCLK_MIPIDSI_24M>, <&cru PCLK_MIPI_DSI0>;
1132                 clock-names = "ref", "pclk";
1133                 power-domains = <&power RK3288_PD_VIO>;
1134                 rockchip,grf = <&grf>;
1135                 status = "disabled";
1136
1137                 ports {
1138                         mipi_in: port {
1139                                 #address-cells = <1>;
1140                                 #size-cells = <0>;
1141                                 mipi_in_vopb: endpoint@0 {
1142                                         reg = <0>;
1143                                         remote-endpoint = <&vopb_out_mipi>;
1144                                 };
1145                                 mipi_in_vopl: endpoint@1 {
1146                                         reg = <1>;
1147                                         remote-endpoint = <&vopl_out_mipi>;
1148                                 };
1149                         };
1150                 };
1151         };
1152
1153         lvds: lvds@ff96c000 {
1154                 compatible = "rockchip,rk3288-lvds";
1155                 reg = <0x0 0xff96c000 0x0 0x4000>;
1156                 clocks = <&cru PCLK_LVDS_PHY>;
1157                 clock-names = "pclk_lvds";
1158                 pinctrl-names = "lcdc";
1159                 pinctrl-0 = <&lcdc_ctl>;
1160                 power-domains = <&power RK3288_PD_VIO>;
1161                 rockchip,grf = <&grf>;
1162                 status = "disabled";
1163
1164                 ports {
1165                         #address-cells = <1>;
1166                         #size-cells = <0>;
1167
1168                         lvds_in: port@0 {
1169                                 reg = <0>;
1170
1171                                 #address-cells = <1>;
1172                                 #size-cells = <0>;
1173
1174                                 lvds_in_vopb: endpoint@0 {
1175                                         reg = <0>;
1176                                         remote-endpoint = <&vopb_out_lvds>;
1177                                 };
1178                                 lvds_in_vopl: endpoint@1 {
1179                                         reg = <1>;
1180                                         remote-endpoint = <&vopl_out_lvds>;
1181                                 };
1182                         };
1183                 };
1184         };
1185
1186         edp: dp@ff970000 {
1187                 compatible = "rockchip,rk3288-dp";
1188                 reg = <0x0 0xff970000 0x0 0x4000>;
1189                 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
1190                 clocks = <&cru SCLK_EDP>, <&cru PCLK_EDP_CTRL>;
1191                 clock-names = "dp", "pclk";
1192                 phys = <&edp_phy>;
1193                 phy-names = "dp";
1194                 resets = <&cru SRST_EDP>;
1195                 reset-names = "dp";
1196                 rockchip,grf = <&grf>;
1197                 status = "disabled";
1198
1199                 ports {
1200                         #address-cells = <1>;
1201                         #size-cells = <0>;
1202                         edp_in: port@0 {
1203                                 reg = <0>;
1204                                 #address-cells = <1>;
1205                                 #size-cells = <0>;
1206                                 edp_in_vopb: endpoint@0 {
1207                                         reg = <0>;
1208                                         remote-endpoint = <&vopb_out_edp>;
1209                                 };
1210                                 edp_in_vopl: endpoint@1 {
1211                                         reg = <1>;
1212                                         remote-endpoint = <&vopl_out_edp>;
1213                                 };
1214                         };
1215                 };
1216         };
1217
1218         hdmi: hdmi@ff980000 {
1219                 compatible = "rockchip,rk3288-dw-hdmi";
1220                 reg = <0x0 0xff980000 0x0 0x20000>;
1221                 reg-io-width = <4>;
1222                 #sound-dai-cells = <0>;
1223                 rockchip,grf = <&grf>;
1224                 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
1225                 clocks = <&cru  PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_HDCP>, <&cru SCLK_HDMI_CEC>;
1226                 clock-names = "iahb", "isfr", "cec";
1227                 power-domains = <&power RK3288_PD_VIO>;
1228                 status = "disabled";
1229
1230                 ports {
1231                         hdmi_in: port {
1232                                 #address-cells = <1>;
1233                                 #size-cells = <0>;
1234                                 hdmi_in_vopb: endpoint@0 {
1235                                         reg = <0>;
1236                                         remote-endpoint = <&vopb_out_hdmi>;
1237                                 };
1238                                 hdmi_in_vopl: endpoint@1 {
1239                                         reg = <1>;
1240                                         remote-endpoint = <&vopl_out_hdmi>;
1241                                 };
1242                         };
1243                 };
1244         };
1245
1246         vpu: video-codec@ff9a0000 {
1247                 compatible = "rockchip,rk3288-vpu";
1248                 reg = <0x0 0xff9a0000 0x0 0x800>;
1249                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
1250                              <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
1251                 interrupt-names = "vepu", "vdpu";
1252                 clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>;
1253                 clock-names = "aclk", "hclk";
1254                 iommus = <&vpu_mmu>;
1255                 power-domains = <&power RK3288_PD_VIDEO>;
1256         };
1257
1258         vpu_mmu: iommu@ff9a0800 {
1259                 compatible = "rockchip,iommu";
1260                 reg = <0x0 0xff9a0800 0x0 0x100>;
1261                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
1262                 interrupt-names = "vpu_mmu";
1263                 clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>;
1264                 clock-names = "aclk", "iface";
1265                 #iommu-cells = <0>;
1266                 power-domains = <&power RK3288_PD_VIDEO>;
1267         };
1268
1269         hevc_mmu: iommu@ff9c0440 {
1270                 compatible = "rockchip,iommu";
1271                 reg = <0x0 0xff9c0440 0x0 0x40>, <0x0 0xff9c0480 0x0 0x40>;
1272                 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
1273                 interrupt-names = "hevc_mmu";
1274                 clocks = <&cru ACLK_HEVC>, <&cru HCLK_HEVC>;
1275                 clock-names = "aclk", "iface";
1276                 #iommu-cells = <0>;
1277                 status = "disabled";
1278         };
1279
1280         gpu: gpu@ffa30000 {
1281                 compatible = "rockchip,rk3288-mali", "arm,mali-t760";
1282                 reg = <0x0 0xffa30000 0x0 0x10000>;
1283                 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
1284                              <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
1285                              <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
1286                 interrupt-names = "job", "mmu", "gpu";
1287                 clocks = <&cru ACLK_GPU>;
1288                 operating-points-v2 = <&gpu_opp_table>;
1289                 #cooling-cells = <2>; /* min followed by max */
1290                 power-domains = <&power RK3288_PD_GPU>;
1291                 status = "disabled";
1292         };
1293
1294         gpu_opp_table: gpu-opp-table {
1295                 compatible = "operating-points-v2";
1296
1297                 opp-100000000 {
1298                         opp-hz = /bits/ 64 <100000000>;
1299                         opp-microvolt = <950000>;
1300                 };
1301                 opp-200000000 {
1302                         opp-hz = /bits/ 64 <200000000>;
1303                         opp-microvolt = <950000>;
1304                 };
1305                 opp-300000000 {
1306                         opp-hz = /bits/ 64 <300000000>;
1307                         opp-microvolt = <1000000>;
1308                 };
1309                 opp-400000000 {
1310                         opp-hz = /bits/ 64 <400000000>;
1311                         opp-microvolt = <1100000>;
1312                 };
1313                 opp-600000000 {
1314                         opp-hz = /bits/ 64 <600000000>;
1315                         opp-microvolt = <1250000>;
1316                 };
1317         };
1318
1319         qos_gpu_r: qos@ffaa0000 {
1320                 compatible = "syscon";
1321                 reg = <0x0 0xffaa0000 0x0 0x20>;
1322         };
1323
1324         qos_gpu_w: qos@ffaa0080 {
1325                 compatible = "syscon";
1326                 reg = <0x0 0xffaa0080 0x0 0x20>;
1327         };
1328
1329         qos_vio1_vop: qos@ffad0000 {
1330                 compatible = "syscon";
1331                 reg = <0x0 0xffad0000 0x0 0x20>;
1332         };
1333
1334         qos_vio1_isp_w0: qos@ffad0100 {
1335                 compatible = "syscon";
1336                 reg = <0x0 0xffad0100 0x0 0x20>;
1337         };
1338
1339         qos_vio1_isp_w1: qos@ffad0180 {
1340                 compatible = "syscon";
1341                 reg = <0x0 0xffad0180 0x0 0x20>;
1342         };
1343
1344         qos_vio0_vop: qos@ffad0400 {
1345                 compatible = "syscon";
1346                 reg = <0x0 0xffad0400 0x0 0x20>;
1347         };
1348
1349         qos_vio0_vip: qos@ffad0480 {
1350                 compatible = "syscon";
1351                 reg = <0x0 0xffad0480 0x0 0x20>;
1352         };
1353
1354         qos_vio0_iep: qos@ffad0500 {
1355                 compatible = "syscon";
1356                 reg = <0x0 0xffad0500 0x0 0x20>;
1357         };
1358
1359         qos_vio2_rga_r: qos@ffad0800 {
1360                 compatible = "syscon";
1361                 reg = <0x0 0xffad0800 0x0 0x20>;
1362         };
1363
1364         qos_vio2_rga_w: qos@ffad0880 {
1365                 compatible = "syscon";
1366                 reg = <0x0 0xffad0880 0x0 0x20>;
1367         };
1368
1369         qos_vio1_isp_r: qos@ffad0900 {
1370                 compatible = "syscon";
1371                 reg = <0x0 0xffad0900 0x0 0x20>;
1372         };
1373
1374         qos_video: qos@ffae0000 {
1375                 compatible = "syscon";
1376                 reg = <0x0 0xffae0000 0x0 0x20>;
1377         };
1378
1379         qos_hevc_r: qos@ffaf0000 {
1380                 compatible = "syscon";
1381                 reg = <0x0 0xffaf0000 0x0 0x20>;
1382         };
1383
1384         qos_hevc_w: qos@ffaf0080 {
1385                 compatible = "syscon";
1386                 reg = <0x0 0xffaf0080 0x0 0x20>;
1387         };
1388
1389         efuse: efuse@ffb40000 {
1390                 compatible = "rockchip,rk3288-efuse";
1391                 reg = <0x0 0xffb40000 0x0 0x20>;
1392                 #address-cells = <1>;
1393                 #size-cells = <1>;
1394                 clocks = <&cru PCLK_EFUSE256>;
1395                 clock-names = "pclk_efuse";
1396
1397                 cpu_id: cpu-id@7 {
1398                         reg = <0x07 0x10>;
1399                 };
1400                 cpu_leakage: cpu_leakage@17 {
1401                         reg = <0x17 0x1>;
1402                 };
1403         };
1404
1405         gic: interrupt-controller@ffc01000 {
1406                 compatible = "arm,gic-400";
1407                 interrupt-controller;
1408                 #interrupt-cells = <3>;
1409                 #address-cells = <0>;
1410
1411                 reg = <0x0 0xffc01000 0x0 0x1000>,
1412                       <0x0 0xffc02000 0x0 0x2000>,
1413                       <0x0 0xffc04000 0x0 0x2000>,
1414                       <0x0 0xffc06000 0x0 0x2000>;
1415                 interrupts = <GIC_PPI 9 0xf04>;
1416         };
1417
1418         pinctrl: pinctrl {
1419                 compatible = "rockchip,rk3288-pinctrl";
1420                 rockchip,grf = <&grf>;
1421                 rockchip,pmu = <&pmu>;
1422                 #address-cells = <2>;
1423                 #size-cells = <2>;
1424                 ranges;
1425
1426                 gpio0: gpio0@ff750000 {
1427                         compatible = "rockchip,gpio-bank";
1428                         reg = <0x0 0xff750000 0x0 0x100>;
1429                         interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
1430                         clocks = <&cru PCLK_GPIO0>;
1431
1432                         gpio-controller;
1433                         #gpio-cells = <2>;
1434
1435                         interrupt-controller;
1436                         #interrupt-cells = <2>;
1437                 };
1438
1439                 gpio1: gpio1@ff780000 {
1440                         compatible = "rockchip,gpio-bank";
1441                         reg = <0x0 0xff780000 0x0 0x100>;
1442                         interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
1443                         clocks = <&cru PCLK_GPIO1>;
1444
1445                         gpio-controller;
1446                         #gpio-cells = <2>;
1447
1448                         interrupt-controller;
1449                         #interrupt-cells = <2>;
1450                 };
1451
1452                 gpio2: gpio2@ff790000 {
1453                         compatible = "rockchip,gpio-bank";
1454                         reg = <0x0 0xff790000 0x0 0x100>;
1455                         interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
1456                         clocks = <&cru PCLK_GPIO2>;
1457
1458                         gpio-controller;
1459                         #gpio-cells = <2>;
1460
1461                         interrupt-controller;
1462                         #interrupt-cells = <2>;
1463                 };
1464
1465                 gpio3: gpio3@ff7a0000 {
1466                         compatible = "rockchip,gpio-bank";
1467                         reg = <0x0 0xff7a0000 0x0 0x100>;
1468                         interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
1469                         clocks = <&cru PCLK_GPIO3>;
1470
1471                         gpio-controller;
1472                         #gpio-cells = <2>;
1473
1474                         interrupt-controller;
1475                         #interrupt-cells = <2>;
1476                 };
1477
1478                 gpio4: gpio4@ff7b0000 {
1479                         compatible = "rockchip,gpio-bank";
1480                         reg = <0x0 0xff7b0000 0x0 0x100>;
1481                         interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
1482                         clocks = <&cru PCLK_GPIO4>;
1483
1484                         gpio-controller;
1485                         #gpio-cells = <2>;
1486
1487                         interrupt-controller;
1488                         #interrupt-cells = <2>;
1489                 };
1490
1491                 gpio5: gpio5@ff7c0000 {
1492                         compatible = "rockchip,gpio-bank";
1493                         reg = <0x0 0xff7c0000 0x0 0x100>;
1494                         interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
1495                         clocks = <&cru PCLK_GPIO5>;
1496
1497                         gpio-controller;
1498                         #gpio-cells = <2>;
1499
1500                         interrupt-controller;
1501                         #interrupt-cells = <2>;
1502                 };
1503
1504                 gpio6: gpio6@ff7d0000 {
1505                         compatible = "rockchip,gpio-bank";
1506                         reg = <0x0 0xff7d0000 0x0 0x100>;
1507                         interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
1508                         clocks = <&cru PCLK_GPIO6>;
1509
1510                         gpio-controller;
1511                         #gpio-cells = <2>;
1512
1513                         interrupt-controller;
1514                         #interrupt-cells = <2>;
1515                 };
1516
1517                 gpio7: gpio7@ff7e0000 {
1518                         compatible = "rockchip,gpio-bank";
1519                         reg = <0x0 0xff7e0000 0x0 0x100>;
1520                         interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
1521                         clocks = <&cru PCLK_GPIO7>;
1522
1523                         gpio-controller;
1524                         #gpio-cells = <2>;
1525
1526                         interrupt-controller;
1527                         #interrupt-cells = <2>;
1528                 };
1529
1530                 gpio8: gpio8@ff7f0000 {
1531                         compatible = "rockchip,gpio-bank";
1532                         reg = <0x0 0xff7f0000 0x0 0x100>;
1533                         interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
1534                         clocks = <&cru PCLK_GPIO8>;
1535
1536                         gpio-controller;
1537                         #gpio-cells = <2>;
1538
1539                         interrupt-controller;
1540                         #interrupt-cells = <2>;
1541                 };
1542
1543                 hdmi {
1544                         hdmi_cec_c0: hdmi-cec-c0 {
1545                                 rockchip,pins = <7 RK_PC0 2 &pcfg_pull_none>;
1546                         };
1547
1548                         hdmi_cec_c7: hdmi-cec-c7 {
1549                                 rockchip,pins = <7 RK_PC7 4 &pcfg_pull_none>;
1550                         };
1551
1552                         hdmi_ddc: hdmi-ddc {
1553                                 rockchip,pins = <7 RK_PC3 2 &pcfg_pull_none>,
1554                                                 <7 RK_PC4 2 &pcfg_pull_none>;
1555                         };
1556
1557                         hdmi_ddc_unwedge: hdmi-ddc-unwedge {
1558                                 rockchip,pins = <7 RK_PC3 RK_FUNC_GPIO &pcfg_output_low>,
1559                                                 <7 RK_PC4 2 &pcfg_pull_none>;
1560                         };
1561                 };
1562
1563                 pcfg_output_low: pcfg-output-low {
1564                         output-low;
1565                 };
1566
1567                 pcfg_pull_up: pcfg-pull-up {
1568                         bias-pull-up;
1569                 };
1570
1571                 pcfg_pull_down: pcfg-pull-down {
1572                         bias-pull-down;
1573                 };
1574
1575                 pcfg_pull_none: pcfg-pull-none {
1576                         bias-disable;
1577                 };
1578
1579                 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
1580                         bias-disable;
1581                         drive-strength = <12>;
1582                 };
1583
1584                 sleep {
1585                         global_pwroff: global-pwroff {
1586                                 rockchip,pins = <0 RK_PA0 1 &pcfg_pull_none>;
1587                         };
1588
1589                         ddrio_pwroff: ddrio-pwroff {
1590                                 rockchip,pins = <0 RK_PA1 1 &pcfg_pull_none>;
1591                         };
1592
1593                         ddr0_retention: ddr0-retention {
1594                                 rockchip,pins = <0 RK_PA2 1 &pcfg_pull_up>;
1595                         };
1596
1597                         ddr1_retention: ddr1-retention {
1598                                 rockchip,pins = <0 RK_PA3 1 &pcfg_pull_up>;
1599                         };
1600                 };
1601
1602                 edp {
1603                         edp_hpd: edp-hpd {
1604                                 rockchip,pins = <7 RK_PB3 2 &pcfg_pull_down>;
1605                         };
1606                 };
1607
1608                 i2c0 {
1609                         i2c0_xfer: i2c0-xfer {
1610                                 rockchip,pins = <0 RK_PB7 1 &pcfg_pull_none>,
1611                                                 <0 RK_PC0 1 &pcfg_pull_none>;
1612                         };
1613                 };
1614
1615                 i2c1 {
1616                         i2c1_xfer: i2c1-xfer {
1617                                 rockchip,pins = <8 RK_PA4 1 &pcfg_pull_none>,
1618                                                 <8 RK_PA5 1 &pcfg_pull_none>;
1619                         };
1620                 };
1621
1622                 i2c2 {
1623                         i2c2_xfer: i2c2-xfer {
1624                                 rockchip,pins = <6 RK_PB1 1 &pcfg_pull_none>,
1625                                                 <6 RK_PB2 1 &pcfg_pull_none>;
1626                         };
1627                 };
1628
1629                 i2c3 {
1630                         i2c3_xfer: i2c3-xfer {
1631                                 rockchip,pins = <2 RK_PC0 1 &pcfg_pull_none>,
1632                                                 <2 RK_PC1 1 &pcfg_pull_none>;
1633                         };
1634                 };
1635
1636                 i2c4 {
1637                         i2c4_xfer: i2c4-xfer {
1638                                 rockchip,pins = <7 RK_PC1 1 &pcfg_pull_none>,
1639                                                 <7 RK_PC2 1 &pcfg_pull_none>;
1640                         };
1641                 };
1642
1643                 i2c5 {
1644                         i2c5_xfer: i2c5-xfer {
1645                                 rockchip,pins = <7 RK_PC3 1 &pcfg_pull_none>,
1646                                                 <7 RK_PC4 1 &pcfg_pull_none>;
1647                         };
1648                 };
1649
1650                 i2s0 {
1651                         i2s0_bus: i2s0-bus {
1652                                 rockchip,pins = <6 RK_PA0 1 &pcfg_pull_none>,
1653                                                 <6 RK_PA1 1 &pcfg_pull_none>,
1654                                                 <6 RK_PA2 1 &pcfg_pull_none>,
1655                                                 <6 RK_PA3 1 &pcfg_pull_none>,
1656                                                 <6 RK_PA4 1 &pcfg_pull_none>,
1657                                                 <6 RK_PB0 1 &pcfg_pull_none>;
1658                         };
1659                 };
1660
1661                 lcdc {
1662                         lcdc_ctl: lcdc-ctl {
1663                                 rockchip,pins = <1 RK_PD0 1 &pcfg_pull_none>,
1664                                                 <1 RK_PD1 1 &pcfg_pull_none>,
1665                                                 <1 RK_PD2 1 &pcfg_pull_none>,
1666                                                 <1 RK_PD3 1 &pcfg_pull_none>;
1667                         };
1668                 };
1669
1670                 sdmmc {
1671                         sdmmc_clk: sdmmc-clk {
1672                                 rockchip,pins = <6 RK_PC4 1 &pcfg_pull_none>;
1673                         };
1674
1675                         sdmmc_cmd: sdmmc-cmd {
1676                                 rockchip,pins = <6 RK_PC5 1 &pcfg_pull_up>;
1677                         };
1678
1679                         sdmmc_cd: sdmmc-cd {
1680                                 rockchip,pins = <6 RK_PC6 1 &pcfg_pull_up>;
1681                         };
1682
1683                         sdmmc_bus1: sdmmc-bus1 {
1684                                 rockchip,pins = <6 RK_PC0 1 &pcfg_pull_up>;
1685                         };
1686
1687                         sdmmc_bus4: sdmmc-bus4 {
1688                                 rockchip,pins = <6 RK_PC0 1 &pcfg_pull_up>,
1689                                                 <6 RK_PC1 1 &pcfg_pull_up>,
1690                                                 <6 RK_PC2 1 &pcfg_pull_up>,
1691                                                 <6 RK_PC3 1 &pcfg_pull_up>;
1692                         };
1693                 };
1694
1695                 sdio0 {
1696                         sdio0_bus1: sdio0-bus1 {
1697                                 rockchip,pins = <4 RK_PC4 1 &pcfg_pull_up>;
1698                         };
1699
1700                         sdio0_bus4: sdio0-bus4 {
1701                                 rockchip,pins = <4 RK_PC4 1 &pcfg_pull_up>,
1702                                                 <4 RK_PC5 1 &pcfg_pull_up>,
1703                                                 <4 RK_PC6 1 &pcfg_pull_up>,
1704                                                 <4 RK_PC7 1 &pcfg_pull_up>;
1705                         };
1706
1707                         sdio0_cmd: sdio0-cmd {
1708                                 rockchip,pins = <4 RK_PD0 1 &pcfg_pull_up>;
1709                         };
1710
1711                         sdio0_clk: sdio0-clk {
1712                                 rockchip,pins = <4 RK_PD1 1 &pcfg_pull_none>;
1713                         };
1714
1715                         sdio0_cd: sdio0-cd {
1716                                 rockchip,pins = <4 RK_PD2 1 &pcfg_pull_up>;
1717                         };
1718
1719                         sdio0_wp: sdio0-wp {
1720                                 rockchip,pins = <4 RK_PD3 1 &pcfg_pull_up>;
1721                         };
1722
1723                         sdio0_pwr: sdio0-pwr {
1724                                 rockchip,pins = <4 RK_PD4 1 &pcfg_pull_up>;
1725                         };
1726
1727                         sdio0_bkpwr: sdio0-bkpwr {
1728                                 rockchip,pins = <4 RK_PD5 1 &pcfg_pull_up>;
1729                         };
1730
1731                         sdio0_int: sdio0-int {
1732                                 rockchip,pins = <4 RK_PD6 1 &pcfg_pull_up>;
1733                         };
1734                 };
1735
1736                 sdio1 {
1737                         sdio1_bus1: sdio1-bus1 {
1738                                 rockchip,pins = <3 RK_PD0 4 &pcfg_pull_up>;
1739                         };
1740
1741                         sdio1_bus4: sdio1-bus4 {
1742                                 rockchip,pins = <3 RK_PD0 4 &pcfg_pull_up>,
1743                                                 <3 RK_PD1 4 &pcfg_pull_up>,
1744                                                 <3 RK_PD2 4 &pcfg_pull_up>,
1745                                                 <3 RK_PD3 4 &pcfg_pull_up>;
1746                         };
1747
1748                         sdio1_cd: sdio1-cd {
1749                                 rockchip,pins = <3 RK_PD4 4 &pcfg_pull_up>;
1750                         };
1751
1752                         sdio1_wp: sdio1-wp {
1753                                 rockchip,pins = <3 RK_PD5 4 &pcfg_pull_up>;
1754                         };
1755
1756                         sdio1_bkpwr: sdio1-bkpwr {
1757                                 rockchip,pins = <3 RK_PD6 4 &pcfg_pull_up>;
1758                         };
1759
1760                         sdio1_int: sdio1-int {
1761                                 rockchip,pins = <3 RK_PD7 4 &pcfg_pull_up>;
1762                         };
1763
1764                         sdio1_cmd: sdio1-cmd {
1765                                 rockchip,pins = <4 RK_PA6 4 &pcfg_pull_up>;
1766                         };
1767
1768                         sdio1_clk: sdio1-clk {
1769                                 rockchip,pins = <4 RK_PA7 4 &pcfg_pull_none>;
1770                         };
1771
1772                         sdio1_pwr: sdio1-pwr {
1773                                 rockchip,pins = <4 RK_PB1 4 &pcfg_pull_up>;
1774                         };
1775                 };
1776
1777                 emmc {
1778                         emmc_clk: emmc-clk {
1779                                 rockchip,pins = <3 RK_PC2 2 &pcfg_pull_none>;
1780                         };
1781
1782                         emmc_cmd: emmc-cmd {
1783                                 rockchip,pins = <3 RK_PC0 2 &pcfg_pull_up>;
1784                         };
1785
1786                         emmc_pwr: emmc-pwr {
1787                                 rockchip,pins = <3 RK_PB1 2 &pcfg_pull_up>;
1788                         };
1789
1790                         emmc_bus1: emmc-bus1 {
1791                                 rockchip,pins = <3 RK_PA0 2 &pcfg_pull_up>;
1792                         };
1793
1794                         emmc_bus4: emmc-bus4 {
1795                                 rockchip,pins = <3 RK_PA0 2 &pcfg_pull_up>,
1796                                                 <3 RK_PA1 2 &pcfg_pull_up>,
1797                                                 <3 RK_PA2 2 &pcfg_pull_up>,
1798                                                 <3 RK_PA3 2 &pcfg_pull_up>;
1799                         };
1800
1801                         emmc_bus8: emmc-bus8 {
1802                                 rockchip,pins = <3 RK_PA0 2 &pcfg_pull_up>,
1803                                                 <3 RK_PA1 2 &pcfg_pull_up>,
1804                                                 <3 RK_PA2 2 &pcfg_pull_up>,
1805                                                 <3 RK_PA3 2 &pcfg_pull_up>,
1806                                                 <3 RK_PA4 2 &pcfg_pull_up>,
1807                                                 <3 RK_PA5 2 &pcfg_pull_up>,
1808                                                 <3 RK_PA6 2 &pcfg_pull_up>,
1809                                                 <3 RK_PA7 2 &pcfg_pull_up>;
1810                         };
1811                 };
1812
1813                 spi0 {
1814                         spi0_clk: spi0-clk {
1815                                 rockchip,pins = <5 RK_PB4 1 &pcfg_pull_up>;
1816                         };
1817                         spi0_cs0: spi0-cs0 {
1818                                 rockchip,pins = <5 RK_PB5 1 &pcfg_pull_up>;
1819                         };
1820                         spi0_tx: spi0-tx {
1821                                 rockchip,pins = <5 RK_PB6 1 &pcfg_pull_up>;
1822                         };
1823                         spi0_rx: spi0-rx {
1824                                 rockchip,pins = <5 RK_PB7 1 &pcfg_pull_up>;
1825                         };
1826                         spi0_cs1: spi0-cs1 {
1827                                 rockchip,pins = <5 RK_PC0 1 &pcfg_pull_up>;
1828                         };
1829                 };
1830                 spi1 {
1831                         spi1_clk: spi1-clk {
1832                                 rockchip,pins = <7 RK_PB4 2 &pcfg_pull_up>;
1833                         };
1834                         spi1_cs0: spi1-cs0 {
1835                                 rockchip,pins = <7 RK_PB5 2 &pcfg_pull_up>;
1836                         };
1837                         spi1_rx: spi1-rx {
1838                                 rockchip,pins = <7 RK_PB6 2 &pcfg_pull_up>;
1839                         };
1840                         spi1_tx: spi1-tx {
1841                                 rockchip,pins = <7 RK_PB7 2 &pcfg_pull_up>;
1842                         };
1843                 };
1844
1845                 spi2 {
1846                         spi2_cs1: spi2-cs1 {
1847                                 rockchip,pins = <8 RK_PA3 1 &pcfg_pull_up>;
1848                         };
1849                         spi2_clk: spi2-clk {
1850                                 rockchip,pins = <8 RK_PA6 1 &pcfg_pull_up>;
1851                         };
1852                         spi2_cs0: spi2-cs0 {
1853                                 rockchip,pins = <8 RK_PA7 1 &pcfg_pull_up>;
1854                         };
1855                         spi2_rx: spi2-rx {
1856                                 rockchip,pins = <8 RK_PB0 1 &pcfg_pull_up>;
1857                         };
1858                         spi2_tx: spi2-tx {
1859                                 rockchip,pins = <8 RK_PB1 1 &pcfg_pull_up>;
1860                         };
1861                 };
1862
1863                 uart0 {
1864                         uart0_xfer: uart0-xfer {
1865                                 rockchip,pins = <4 RK_PC0 1 &pcfg_pull_up>,
1866                                                 <4 RK_PC1 1 &pcfg_pull_none>;
1867                         };
1868
1869                         uart0_cts: uart0-cts {
1870                                 rockchip,pins = <4 RK_PC2 1 &pcfg_pull_up>;
1871                         };
1872
1873                         uart0_rts: uart0-rts {
1874                                 rockchip,pins = <4 RK_PC3 1 &pcfg_pull_none>;
1875                         };
1876                 };
1877
1878                 uart1 {
1879                         uart1_xfer: uart1-xfer {
1880                                 rockchip,pins = <5 RK_PB0 1 &pcfg_pull_up>,
1881                                                 <5 RK_PB1 1 &pcfg_pull_none>;
1882                         };
1883
1884                         uart1_cts: uart1-cts {
1885                                 rockchip,pins = <5 RK_PB2 1 &pcfg_pull_up>;
1886                         };
1887
1888                         uart1_rts: uart1-rts {
1889                                 rockchip,pins = <5 RK_PB3 1 &pcfg_pull_none>;
1890                         };
1891                 };
1892
1893                 uart2 {
1894                         uart2_xfer: uart2-xfer {
1895                                 rockchip,pins = <7 RK_PC6 1 &pcfg_pull_up>,
1896                                                 <7 RK_PC7 1 &pcfg_pull_none>;
1897                         };
1898                         /* no rts / cts for uart2 */
1899                 };
1900
1901                 uart3 {
1902                         uart3_xfer: uart3-xfer {
1903                                 rockchip,pins = <7 RK_PA7 1 &pcfg_pull_up>,
1904                                                 <7 RK_PB0 1 &pcfg_pull_none>;
1905                         };
1906
1907                         uart3_cts: uart3-cts {
1908                                 rockchip,pins = <7 RK_PB1 1 &pcfg_pull_up>;
1909                         };
1910
1911                         uart3_rts: uart3-rts {
1912                                 rockchip,pins = <7 RK_PB2 1 &pcfg_pull_none>;
1913                         };
1914                 };
1915
1916                 uart4 {
1917                         uart4_xfer: uart4-xfer {
1918                                 rockchip,pins = <5 RK_PB7 3 &pcfg_pull_up>,
1919                                                 <5 RK_PB6 3 &pcfg_pull_none>;
1920                         };
1921
1922                         uart4_cts: uart4-cts {
1923                                 rockchip,pins = <5 RK_PB4 3 &pcfg_pull_up>;
1924                         };
1925
1926                         uart4_rts: uart4-rts {
1927                                 rockchip,pins = <5 RK_PB5 3 &pcfg_pull_none>;
1928                         };
1929                 };
1930
1931                 tsadc {
1932                         otp_gpio: otp-gpio {
1933                                 rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>;
1934                         };
1935
1936                         otp_out: otp-out {
1937                                 rockchip,pins = <0 RK_PB2 1 &pcfg_pull_none>;
1938                         };
1939                 };
1940
1941                 pwm0 {
1942                         pwm0_pin: pwm0-pin {
1943                                 rockchip,pins = <7 RK_PA0 1 &pcfg_pull_none>;
1944                         };
1945                 };
1946
1947                 pwm1 {
1948                         pwm1_pin: pwm1-pin {
1949                                 rockchip,pins = <7 RK_PA1 1 &pcfg_pull_none>;
1950                         };
1951                 };
1952
1953                 pwm2 {
1954                         pwm2_pin: pwm2-pin {
1955                                 rockchip,pins = <7 RK_PC6 3 &pcfg_pull_none>;
1956                         };
1957                 };
1958
1959                 pwm3 {
1960                         pwm3_pin: pwm3-pin {
1961                                 rockchip,pins = <7 RK_PC7 3 &pcfg_pull_none>;
1962                         };
1963                 };
1964
1965                 gmac {
1966                         rgmii_pins: rgmii-pins {
1967                                 rockchip,pins = <3 RK_PD6 3 &pcfg_pull_none>,
1968                                                 <3 RK_PD7 3 &pcfg_pull_none>,
1969                                                 <3 RK_PD2 3 &pcfg_pull_none>,
1970                                                 <3 RK_PD3 3 &pcfg_pull_none>,
1971                                                 <3 RK_PD4 3 &pcfg_pull_none_12ma>,
1972                                                 <3 RK_PD5 3 &pcfg_pull_none_12ma>,
1973                                                 <3 RK_PD0 3 &pcfg_pull_none_12ma>,
1974                                                 <3 RK_PD1 3 &pcfg_pull_none_12ma>,
1975                                                 <4 RK_PA0 3 &pcfg_pull_none>,
1976                                                 <4 RK_PA5 3 &pcfg_pull_none>,
1977                                                 <4 RK_PA6 3 &pcfg_pull_none>,
1978                                                 <4 RK_PB1 3 &pcfg_pull_none_12ma>,
1979                                                 <4 RK_PA4 3 &pcfg_pull_none_12ma>,
1980                                                 <4 RK_PA1 3 &pcfg_pull_none>,
1981                                                 <4 RK_PA3 3 &pcfg_pull_none>;
1982                         };
1983
1984                         rmii_pins: rmii-pins {
1985                                 rockchip,pins = <3 RK_PD6 3 &pcfg_pull_none>,
1986                                                 <3 RK_PD7 3 &pcfg_pull_none>,
1987                                                 <3 RK_PD4 3 &pcfg_pull_none>,
1988                                                 <3 RK_PD5 3 &pcfg_pull_none>,
1989                                                 <4 RK_PA0 3 &pcfg_pull_none>,
1990                                                 <4 RK_PA5 3 &pcfg_pull_none>,
1991                                                 <4 RK_PA4 3 &pcfg_pull_none>,
1992                                                 <4 RK_PA1 3 &pcfg_pull_none>,
1993                                                 <4 RK_PA2 3 &pcfg_pull_none>,
1994                                                 <4 RK_PA3 3 &pcfg_pull_none>;
1995                         };
1996                 };
1997
1998                 spdif {
1999                         spdif_tx: spdif-tx {
2000                                 rockchip,pins = <6 RK_PB3 1 &pcfg_pull_none>;
2001                         };
2002                 };
2003         };
2004 };