2 * sama5d2.dtsi - Device Tree Include file for SAMA5D2 family SoC
4 * Copyright (C) 2015 Atmel,
5 * 2015 Ludovic Desroches <ludovic.desroches@atmel.com>
7 * This file is dual-licensed: you can use it either under the terms
8 * of the GPL or the X11 license, at your option. Note that this dual
9 * licensing only applies to this file, and not this project as a
12 * a) This file is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of the
15 * License, or (at your option) any later version.
17 * This file is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
24 * b) Permission is hereby granted, free of charge, to any person
25 * obtaining a copy of this software and associated documentation
26 * files (the "Software"), to deal in the Software without
27 * restriction, including without limitation the rights to use,
28 * copy, modify, merge, publish, distribute, sublicense, and/or
29 * sell copies of the Software, and to permit persons to whom the
30 * Software is furnished to do so, subject to the following
33 * The above copyright notice and this permission notice shall be
34 * included in all copies or substantial portions of the Software.
36 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
37 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
38 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
39 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
40 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
41 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
42 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
43 * OTHER DEALINGS IN THE SOFTWARE.
46 #include "skeleton.dtsi"
47 #include <dt-bindings/dma/at91.h>
48 #include <dt-bindings/interrupt-controller/irq.h>
49 #include <dt-bindings/clock/at91.h>
50 #include <dt-bindings/iio/adc/at91-sama5d2_adc.h>
53 model = "Atmel SAMA5D2 family SoC";
54 compatible = "atmel,sama5d2";
55 interrupt-parent = <&aic>;
72 compatible = "arm,cortex-a5";
74 next-level-cache = <&L2>;
79 compatible = "arm,cortex-a5-pmu";
80 interrupts = <2 IRQ_TYPE_LEVEL_HIGH 0>;
84 compatible = "arm,coresight-etb10", "arm,primecell";
85 reg = <0x740000 0x1000>;
88 clock-names = "apb_pclk";
93 remote-endpoint = <&etm_out>;
100 compatible = "arm,coresight-etm3x", "arm,primecell";
101 reg = <0x73C000 0x1000>;
104 clock-names = "apb_pclk";
109 remote-endpoint = <&etb_in>;
116 reg = <0x20000000 0x20000000>;
120 slow_xtal: slow_xtal {
121 compatible = "fixed-clock";
123 clock-frequency = <0>;
126 main_xtal: main_xtal {
127 compatible = "fixed-clock";
129 clock-frequency = <0>;
133 ns_sram: sram@200000 {
134 compatible = "mmio-sram";
135 reg = <0x00200000 0x20000>;
139 compatible = "simple-bus";
140 #address-cells = <1>;
144 nfc_sram: sram@100000 {
145 compatible = "mmio-sram";
147 reg = <0x00100000 0x2400>;
150 usb0: gadget@300000 {
151 #address-cells = <1>;
153 compatible = "atmel,sama5d3-udc";
154 reg = <0x00300000 0x100000
156 interrupts = <42 IRQ_TYPE_LEVEL_HIGH 2>;
157 clocks = <&udphs_clk>, <&utmi>;
158 clock-names = "pclk", "hclk";
163 atmel,fifo-size = <64>;
164 atmel,nb-banks = <1>;
169 atmel,fifo-size = <1024>;
170 atmel,nb-banks = <3>;
177 atmel,fifo-size = <1024>;
178 atmel,nb-banks = <3>;
185 atmel,fifo-size = <1024>;
186 atmel,nb-banks = <2>;
193 atmel,fifo-size = <1024>;
194 atmel,nb-banks = <2>;
201 atmel,fifo-size = <1024>;
202 atmel,nb-banks = <2>;
209 atmel,fifo-size = <1024>;
210 atmel,nb-banks = <2>;
217 atmel,fifo-size = <1024>;
218 atmel,nb-banks = <2>;
225 atmel,fifo-size = <1024>;
226 atmel,nb-banks = <2>;
232 atmel,fifo-size = <1024>;
233 atmel,nb-banks = <2>;
239 atmel,fifo-size = <1024>;
240 atmel,nb-banks = <2>;
246 atmel,fifo-size = <1024>;
247 atmel,nb-banks = <2>;
253 atmel,fifo-size = <1024>;
254 atmel,nb-banks = <2>;
260 atmel,fifo-size = <1024>;
261 atmel,nb-banks = <2>;
267 atmel,fifo-size = <1024>;
268 atmel,nb-banks = <2>;
274 atmel,fifo-size = <1024>;
275 atmel,nb-banks = <2>;
281 compatible = "atmel,at91rm9200-ohci", "usb-ohci";
282 reg = <0x00400000 0x100000>;
283 interrupts = <41 IRQ_TYPE_LEVEL_HIGH 2>;
284 clocks = <&uhphs_clk>, <&uhphs_clk>, <&uhpck>;
285 clock-names = "ohci_clk", "hclk", "uhpck";
290 compatible = "atmel,at91sam9g45-ehci", "usb-ehci";
291 reg = <0x00500000 0x100000>;
292 interrupts = <41 IRQ_TYPE_LEVEL_HIGH 2>;
293 clocks = <&utmi>, <&uhphs_clk>;
294 clock-names = "usb_clk", "ehci_clk";
298 L2: cache-controller@a00000 {
299 compatible = "arm,pl310-cache";
300 reg = <0x00a00000 0x1000>;
301 interrupts = <63 IRQ_TYPE_LEVEL_HIGH 4>;
307 compatible = "atmel,sama5d3-ebi";
308 #address-cells = <2>;
311 reg = <0x10000000 0x10000000
312 0x60000000 0x30000000>;
313 ranges = <0x0 0x0 0x10000000 0x10000000
314 0x1 0x0 0x60000000 0x10000000
315 0x2 0x0 0x70000000 0x10000000
316 0x3 0x0 0x80000000 0x10000000>;
320 nand_controller: nand-controller {
321 compatible = "atmel,sama5d3-nand-controller";
322 atmel,nfc-sram = <&nfc_sram>;
323 atmel,nfc-io = <&nfc_io>;
324 ecc-engine = <&pmecc>;
325 #address-cells = <2>;
332 sdmmc0: sdio-host@a0000000 {
333 compatible = "atmel,sama5d2-sdhci";
334 reg = <0xa0000000 0x300>;
335 interrupts = <31 IRQ_TYPE_LEVEL_HIGH 0>;
336 clocks = <&sdmmc0_hclk>, <&sdmmc0_gclk>, <&main>;
337 clock-names = "hclock", "multclk", "baseclk";
341 sdmmc1: sdio-host@b0000000 {
342 compatible = "atmel,sama5d2-sdhci";
343 reg = <0xb0000000 0x300>;
344 interrupts = <32 IRQ_TYPE_LEVEL_HIGH 0>;
345 clocks = <&sdmmc1_hclk>, <&sdmmc1_gclk>, <&main>;
346 clock-names = "hclock", "multclk", "baseclk";
350 nfc_io: nfc-io@c0000000 {
351 compatible = "atmel,sama5d3-nfc-io", "syscon";
352 reg = <0xc0000000 0x8000000>;
356 compatible = "simple-bus";
357 #address-cells = <1>;
361 hlcdc: hlcdc@f0000000 {
362 compatible = "atmel,sama5d2-hlcdc";
363 reg = <0xf0000000 0x2000>;
364 interrupts = <45 IRQ_TYPE_LEVEL_HIGH 0>;
365 clocks = <&lcdc_clk>, <&lcdck>, <&clk32k>;
366 clock-names = "periph_clk","sys_clk", "slow_clk";
369 hlcdc-display-controller {
370 compatible = "atmel,hlcdc-display-controller";
371 #address-cells = <1>;
375 #address-cells = <1>;
381 hlcdc_pwm: hlcdc-pwm {
382 compatible = "atmel,hlcdc-pwm";
388 compatible = "atmel,sama5d2-isc";
389 reg = <0xf0008000 0x4000>;
390 interrupts = <46 IRQ_TYPE_LEVEL_HIGH 5>;
391 clocks = <&isc_clk>, <&iscck>, <&isc_gclk>;
392 clock-names = "hclock", "iscck", "gck";
394 clock-output-names = "isc-mck";
398 ramc0: ramc@f000c000 {
399 compatible = "atmel,sama5d3-ddramc";
400 reg = <0xf000c000 0x200>;
401 clocks = <&ddrck>, <&mpddr_clk>;
402 clock-names = "ddrck", "mpddr";
405 dma0: dma-controller@f0010000 {
406 compatible = "atmel,sama5d4-dma";
407 reg = <0xf0010000 0x1000>;
408 interrupts = <6 IRQ_TYPE_LEVEL_HIGH 0>;
410 clocks = <&dma0_clk>;
411 clock-names = "dma_clk";
414 /* Place dma1 here despite its address */
415 dma1: dma-controller@f0004000 {
416 compatible = "atmel,sama5d4-dma";
417 reg = <0xf0004000 0x1000>;
418 interrupts = <7 IRQ_TYPE_LEVEL_HIGH 0>;
420 clocks = <&dma1_clk>;
421 clock-names = "dma_clk";
425 compatible = "atmel,sama5d2-pmc", "syscon";
426 reg = <0xf0014000 0x160>;
427 interrupts = <74 IRQ_TYPE_LEVEL_HIGH 7>;
428 interrupt-controller;
429 #address-cells = <1>;
431 #interrupt-cells = <1>;
433 main_rc_osc: main_rc_osc {
434 compatible = "atmel,at91sam9x5-clk-main-rc-osc";
436 interrupt-parent = <&pmc>;
437 interrupts = <AT91_PMC_MOSCRCS>;
438 clock-frequency = <12000000>;
439 clock-accuracy = <100000000>;
443 compatible = "atmel,at91rm9200-clk-main-osc";
445 interrupt-parent = <&pmc>;
446 interrupts = <AT91_PMC_MOSCS>;
447 clocks = <&main_xtal>;
451 compatible = "atmel,at91sam9x5-clk-main";
453 interrupt-parent = <&pmc>;
454 interrupts = <AT91_PMC_MOSCSELS>;
455 clocks = <&main_rc_osc &main_osc>;
459 compatible = "atmel,sama5d3-clk-pll";
461 interrupt-parent = <&pmc>;
462 interrupts = <AT91_PMC_LOCKA>;
465 atmel,clk-input-range = <12000000 12000000>;
466 #atmel,pll-clk-output-range-cells = <4>;
467 atmel,pll-clk-output-ranges = <600000000 1200000000 0 0>;
471 compatible = "atmel,at91sam9x5-clk-plldiv";
476 audio_pll_frac: audiopll_fracck {
477 compatible = "atmel,sama5d2-clk-audio-pll-frac";
482 audio_pll_pad: audiopll_padck {
483 compatible = "atmel,sama5d2-clk-audio-pll-pad";
485 clocks = <&audio_pll_frac>;
488 audio_pll_pmc: audiopll_pmcck {
489 compatible = "atmel,sama5d2-clk-audio-pll-pmc";
491 clocks = <&audio_pll_frac>;
495 compatible = "atmel,at91sam9x5-clk-utmi";
497 interrupt-parent = <&pmc>;
498 interrupts = <AT91_PMC_LOCKU>;
503 compatible = "atmel,at91sam9x5-clk-master";
505 interrupt-parent = <&pmc>;
506 interrupts = <AT91_PMC_MCKRDY>;
507 clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>;
508 atmel,clk-output-range = <124000000 166000000>;
509 atmel,clk-divisors = <1 2 4 3>;
514 compatible = "atmel,sama5d4-clk-h32mx";
519 compatible = "atmel,at91sam9x5-clk-usb";
521 clocks = <&plladiv>, <&utmi>;
525 compatible = "atmel,at91sam9x5-clk-programmable";
526 #address-cells = <1>;
528 interrupt-parent = <&pmc>;
529 clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>, <&mck>;
534 interrupts = <AT91_PMC_PCKRDY(0)>;
540 interrupts = <AT91_PMC_PCKRDY(1)>;
546 interrupts = <AT91_PMC_PCKRDY(2)>;
551 compatible = "atmel,at91rm9200-clk-system";
552 #address-cells = <1>;
605 compatible = "atmel,at91sam9x5-clk-peripheral";
606 #address-cells = <1>;
610 macb0_clk: macb0_clk {
613 atmel,clk-output-range = <0 83000000>;
619 atmel,clk-output-range = <0 83000000>;
622 matrix1_clk: matrix1_clk {
635 atmel,clk-output-range = <0 83000000>;
641 atmel,clk-output-range = <0 83000000>;
647 atmel,clk-output-range = <0 83000000>;
653 atmel,clk-output-range = <0 83000000>;
659 atmel,clk-output-range = <0 83000000>;
665 atmel,clk-output-range = <0 83000000>;
668 uart0_clk: uart0_clk {
671 atmel,clk-output-range = <0 83000000>;
674 uart1_clk: uart1_clk {
677 atmel,clk-output-range = <0 83000000>;
680 uart2_clk: uart2_clk {
683 atmel,clk-output-range = <0 83000000>;
686 uart3_clk: uart3_clk {
689 atmel,clk-output-range = <0 83000000>;
692 uart4_clk: uart4_clk {
695 atmel,clk-output-range = <0 83000000>;
701 atmel,clk-output-range = <0 83000000>;
707 atmel,clk-output-range = <0 83000000>;
713 atmel,clk-output-range = <0 83000000>;
719 atmel,clk-output-range = <0 83000000>;
725 atmel,clk-output-range = <0 83000000>;
731 atmel,clk-output-range = <0 83000000>;
737 atmel,clk-output-range = <0 83000000>;
743 atmel,clk-output-range = <0 83000000>;
746 uhphs_clk: uhphs_clk {
749 atmel,clk-output-range = <0 83000000>;
752 udphs_clk: udphs_clk {
755 atmel,clk-output-range = <0 83000000>;
761 atmel,clk-output-range = <0 83000000>;
767 atmel,clk-output-range = <0 83000000>;
773 atmel,clk-output-range = <0 83000000>;
776 pdmic_clk: pdmic_clk {
779 atmel,clk-output-range = <0 83000000>;
782 securam_clk: securam_clk {
790 atmel,clk-output-range = <0 83000000>;
796 atmel,clk-output-range = <0 83000000>;
802 atmel,clk-output-range = <0 83000000>;
808 atmel,clk-output-range = <0 83000000>;
811 classd_clk: classd_clk {
814 atmel,clk-output-range = <0 83000000>;
819 compatible = "atmel,at91sam9x5-clk-peripheral";
820 #address-cells = <1>;
849 mpddr_clk: mpddr_clk {
854 matrix0_clk: matrix0_clk {
859 sdmmc0_hclk: sdmmc0_hclk {
864 sdmmc1_hclk: sdmmc1_hclk {
879 qspi0_clk: qspi0_clk {
884 qspi1_clk: qspi1_clk {
891 compatible = "atmel,sama5d2-clk-generated";
892 #address-cells = <1>;
894 interrupt-parent = <&pmc>;
895 clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>, <&mck>, <&audio_pll_pmc>;
897 sdmmc0_gclk: sdmmc0_gclk {
902 sdmmc1_gclk: sdmmc1_gclk {
907 tcb0_gclk: tcb0_gclk {
910 atmel,clk-output-range = <0 83000000>;
913 tcb1_gclk: tcb1_gclk {
916 atmel,clk-output-range = <0 83000000>;
922 atmel,clk-output-range = <0 83000000>;
930 pdmic_gclk: pdmic_gclk {
935 i2s0_gclk: i2s0_gclk {
940 i2s1_gclk: i2s1_gclk {
945 can0_gclk: can0_gclk {
948 atmel,clk-output-range = <0 80000000>;
951 can1_gclk: can1_gclk {
954 atmel,clk-output-range = <0 80000000>;
957 classd_gclk: classd_gclk {
960 atmel,clk-output-range = <0 100000000>;
965 compatible = "atmel,sama5d2-clk-i2s-mux";
966 #address-cells = <1>;
969 i2s0muxck: i2s0_muxclk {
970 clocks = <&i2s0_clk>, <&i2s0_gclk>;
975 i2s1muxck: i2s1_muxclk {
976 clocks = <&i2s1_clk>, <&i2s1_gclk>;
983 qspi0: spi@f0020000 {
984 compatible = "atmel,sama5d2-qspi";
985 reg = <0xf0020000 0x100>, <0xd0000000 0x08000000>;
986 reg-names = "qspi_base", "qspi_mmap";
987 interrupts = <52 IRQ_TYPE_LEVEL_HIGH 7>;
988 clocks = <&qspi0_clk>;
989 #address-cells = <1>;
994 qspi1: spi@f0024000 {
995 compatible = "atmel,sama5d2-qspi";
996 reg = <0xf0024000 0x100>, <0xd8000000 0x08000000>;
997 reg-names = "qspi_base", "qspi_mmap";
998 interrupts = <53 IRQ_TYPE_LEVEL_HIGH 7>;
999 clocks = <&qspi1_clk>;
1000 #address-cells = <1>;
1002 status = "disabled";
1006 compatible = "atmel,at91sam9g46-sha";
1007 reg = <0xf0028000 0x100>;
1008 interrupts = <12 IRQ_TYPE_LEVEL_HIGH 0>;
1010 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
1011 AT91_XDMAC_DT_PERID(30))>;
1013 clocks = <&sha_clk>;
1014 clock-names = "sha_clk";
1019 compatible = "atmel,at91sam9g46-aes";
1020 reg = <0xf002c000 0x100>;
1021 interrupts = <9 IRQ_TYPE_LEVEL_HIGH 0>;
1023 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
1024 AT91_XDMAC_DT_PERID(26))>,
1026 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
1027 AT91_XDMAC_DT_PERID(27))>;
1028 dma-names = "tx", "rx";
1029 clocks = <&aes_clk>;
1030 clock-names = "aes_clk";
1034 spi0: spi@f8000000 {
1035 compatible = "atmel,at91rm9200-spi";
1036 reg = <0xf8000000 0x100>;
1037 interrupts = <33 IRQ_TYPE_LEVEL_HIGH 7>;
1039 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
1040 AT91_XDMAC_DT_PERID(6))>,
1042 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
1043 AT91_XDMAC_DT_PERID(7))>;
1044 dma-names = "tx", "rx";
1045 clocks = <&spi0_clk>;
1046 clock-names = "spi_clk";
1047 atmel,fifo-size = <16>;
1048 #address-cells = <1>;
1050 status = "disabled";
1053 ssc0: ssc@f8004000 {
1054 compatible = "atmel,at91sam9g45-ssc";
1055 reg = <0xf8004000 0x4000>;
1056 interrupts = <43 IRQ_TYPE_LEVEL_HIGH 4>;
1058 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
1059 AT91_XDMAC_DT_PERID(21))>,
1061 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
1062 AT91_XDMAC_DT_PERID(22))>;
1063 dma-names = "tx", "rx";
1064 clocks = <&ssc0_clk>;
1065 clock-names = "pclk";
1066 status = "disabled";
1069 macb0: ethernet@f8008000 {
1070 compatible = "atmel,sama5d2-gem";
1071 reg = <0xf8008000 0x1000>;
1072 interrupts = <5 IRQ_TYPE_LEVEL_HIGH 3 /* Queue 0 */
1073 66 IRQ_TYPE_LEVEL_HIGH 3 /* Queue 1 */
1074 67 IRQ_TYPE_LEVEL_HIGH 3>; /* Queue 2 */
1075 #address-cells = <1>;
1077 clocks = <&macb0_clk>, <&macb0_clk>;
1078 clock-names = "hclk", "pclk";
1079 status = "disabled";
1082 tcb0: timer@f800c000 {
1083 compatible = "atmel,at91sam9x5-tcb", "simple-mfd", "syscon";
1084 #address-cells = <1>;
1086 reg = <0xf800c000 0x100>;
1087 interrupts = <35 IRQ_TYPE_LEVEL_HIGH 0>;
1088 clocks = <&tcb0_clk>, <&clk32k>;
1089 clock-names = "t0_clk", "slow_clk";
1092 tcb1: timer@f8010000 {
1093 compatible = "atmel,at91sam9x5-tcb", "simple-mfd", "syscon";
1094 #address-cells = <1>;
1096 reg = <0xf8010000 0x100>;
1097 interrupts = <36 IRQ_TYPE_LEVEL_HIGH 0>;
1098 clocks = <&tcb1_clk>, <&clk32k>;
1099 clock-names = "t0_clk", "slow_clk";
1102 hsmc: hsmc@f8014000 {
1103 compatible = "atmel,sama5d2-smc", "syscon", "simple-mfd";
1104 reg = <0xf8014000 0x1000>;
1105 interrupts = <17 IRQ_TYPE_LEVEL_HIGH 6>;
1106 clocks = <&hsmc_clk>;
1107 #address-cells = <1>;
1111 pmecc: ecc-engine@f8014070 {
1112 compatible = "atmel,sama5d2-pmecc";
1113 reg = <0xf8014070 0x490>,
1118 pdmic: pdmic@f8018000 {
1119 compatible = "atmel,sama5d2-pdmic";
1120 reg = <0xf8018000 0x124>;
1121 interrupts = <48 IRQ_TYPE_LEVEL_HIGH 7>;
1123 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
1124 | AT91_XDMAC_DT_PERID(50))>;
1126 clocks = <&pdmic_clk>, <&pdmic_gclk>;
1127 clock-names = "pclk", "gclk";
1128 status = "disabled";
1131 uart0: serial@f801c000 {
1132 compatible = "atmel,at91sam9260-usart";
1133 reg = <0xf801c000 0x100>;
1134 interrupts = <24 IRQ_TYPE_LEVEL_HIGH 7>;
1136 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
1137 AT91_XDMAC_DT_PERID(35))>,
1139 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
1140 AT91_XDMAC_DT_PERID(36))>;
1141 dma-names = "tx", "rx";
1142 clocks = <&uart0_clk>;
1143 clock-names = "usart";
1144 status = "disabled";
1147 uart1: serial@f8020000 {
1148 compatible = "atmel,at91sam9260-usart";
1149 reg = <0xf8020000 0x100>;
1150 interrupts = <25 IRQ_TYPE_LEVEL_HIGH 7>;
1152 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
1153 AT91_XDMAC_DT_PERID(37))>,
1155 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
1156 AT91_XDMAC_DT_PERID(38))>;
1157 dma-names = "tx", "rx";
1158 clocks = <&uart1_clk>;
1159 clock-names = "usart";
1160 status = "disabled";
1163 uart2: serial@f8024000 {
1164 compatible = "atmel,at91sam9260-usart";
1165 reg = <0xf8024000 0x100>;
1166 interrupts = <26 IRQ_TYPE_LEVEL_HIGH 7>;
1168 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
1169 AT91_XDMAC_DT_PERID(39))>,
1171 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
1172 AT91_XDMAC_DT_PERID(40))>;
1173 dma-names = "tx", "rx";
1174 clocks = <&uart2_clk>;
1175 clock-names = "usart";
1176 status = "disabled";
1179 i2c0: i2c@f8028000 {
1180 compatible = "atmel,sama5d2-i2c";
1181 reg = <0xf8028000 0x100>;
1182 interrupts = <29 IRQ_TYPE_LEVEL_HIGH 7>;
1184 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
1185 AT91_XDMAC_DT_PERID(0))>,
1187 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
1188 AT91_XDMAC_DT_PERID(1))>;
1189 dma-names = "tx", "rx";
1190 #address-cells = <1>;
1192 clocks = <&twi0_clk>;
1193 atmel,fifo-size = <16>;
1194 status = "disabled";
1197 pwm0: pwm@f802c000 {
1198 compatible = "atmel,sama5d2-pwm";
1199 reg = <0xf802c000 0x4000>;
1200 interrupts = <38 IRQ_TYPE_LEVEL_HIGH 7>;
1202 clocks = <&pwm_clk>;
1206 compatible = "atmel,sama5d2-sfr", "syscon";
1207 reg = <0xf8030000 0x98>;
1210 flx0: flexcom@f8034000 {
1211 compatible = "atmel,sama5d2-flexcom";
1212 reg = <0xf8034000 0x200>;
1213 clocks = <&flx0_clk>;
1214 #address-cells = <1>;
1216 ranges = <0x0 0xf8034000 0x800>;
1217 status = "disabled";
1220 flx1: flexcom@f8038000 {
1221 compatible = "atmel,sama5d2-flexcom";
1222 reg = <0xf8038000 0x200>;
1223 clocks = <&flx1_clk>;
1224 #address-cells = <1>;
1226 ranges = <0x0 0xf8038000 0x800>;
1227 status = "disabled";
1230 securam: sram@f8044000 {
1231 compatible = "atmel,sama5d2-securam", "mmio-sram";
1232 reg = <0xf8044000 0x1420>;
1233 clocks = <&securam_clk>;
1234 #address-cells = <1>;
1236 ranges = <0 0xf8044000 0x1420>;
1240 compatible = "atmel,sama5d3-rstc";
1241 reg = <0xf8048000 0x10>;
1246 compatible = "atmel,sama5d2-shdwc";
1247 reg = <0xf8048010 0x10>;
1249 #address-cells = <1>;
1251 atmel,wakeup-rtc-timer;
1254 pit: timer@f8048030 {
1255 compatible = "atmel,at91sam9260-pit";
1256 reg = <0xf8048030 0x10>;
1257 interrupts = <3 IRQ_TYPE_LEVEL_HIGH 5>;
1262 compatible = "atmel,sama5d4-wdt";
1263 reg = <0xf8048040 0x10>;
1264 interrupts = <4 IRQ_TYPE_LEVEL_HIGH 7>;
1266 status = "disabled";
1269 clk32k: sckc@f8048050 {
1270 compatible = "atmel,sama5d4-sckc";
1271 reg = <0xf8048050 0x4>;
1273 clocks = <&slow_xtal>;
1278 compatible = "atmel,at91rm9200-rtc";
1279 reg = <0xf80480b0 0x30>;
1280 interrupts = <74 IRQ_TYPE_LEVEL_HIGH 7>;
1284 i2s0: i2s@f8050000 {
1285 compatible = "atmel,sama5d2-i2s";
1286 reg = <0xf8050000 0x100>;
1287 interrupts = <54 IRQ_TYPE_LEVEL_HIGH 7>;
1289 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
1290 AT91_XDMAC_DT_PERID(31))>,
1292 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
1293 AT91_XDMAC_DT_PERID(32))>;
1294 dma-names = "tx", "rx";
1295 clocks = <&i2s0_clk>, <&i2s0_gclk>;
1296 clock-names = "pclk", "gclk";
1297 assigned-clocks = <&i2s0muxck>;
1298 assigned-clock-parents = <&i2s0_gclk>;
1299 status = "disabled";
1302 can0: can@f8054000 {
1303 compatible = "bosch,m_can";
1304 reg = <0xf8054000 0x4000>, <0x210000 0x4000>;
1305 reg-names = "m_can", "message_ram";
1306 interrupts = <56 IRQ_TYPE_LEVEL_HIGH 7>,
1307 <64 IRQ_TYPE_LEVEL_HIGH 7>;
1308 interrupt-names = "int0", "int1";
1309 clocks = <&can0_clk>, <&can0_gclk>;
1310 clock-names = "hclk", "cclk";
1311 assigned-clocks = <&can0_gclk>;
1312 assigned-clock-parents = <&utmi>;
1313 assigned-clock-rates = <40000000>;
1314 bosch,mram-cfg = <0x0 0 0 64 0 0 32 32>;
1315 status = "disabled";
1318 spi1: spi@fc000000 {
1319 compatible = "atmel,at91rm9200-spi";
1320 reg = <0xfc000000 0x100>;
1321 interrupts = <34 IRQ_TYPE_LEVEL_HIGH 7>;
1323 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
1324 AT91_XDMAC_DT_PERID(8))>,
1326 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
1327 AT91_XDMAC_DT_PERID(9))>;
1328 dma-names = "tx", "rx";
1329 clocks = <&spi1_clk>;
1330 clock-names = "spi_clk";
1331 atmel,fifo-size = <16>;
1332 #address-cells = <1>;
1334 status = "disabled";
1337 uart3: serial@fc008000 {
1338 compatible = "atmel,at91sam9260-usart";
1339 reg = <0xfc008000 0x100>;
1340 interrupts = <27 IRQ_TYPE_LEVEL_HIGH 7>;
1342 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
1343 AT91_XDMAC_DT_PERID(41))>,
1345 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
1346 AT91_XDMAC_DT_PERID(42))>;
1347 dma-names = "tx", "rx";
1348 clocks = <&uart3_clk>;
1349 clock-names = "usart";
1350 status = "disabled";
1353 uart4: serial@fc00c000 {
1354 compatible = "atmel,at91sam9260-usart";
1355 reg = <0xfc00c000 0x100>;
1357 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
1358 AT91_XDMAC_DT_PERID(43))>,
1360 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
1361 AT91_XDMAC_DT_PERID(44))>;
1362 dma-names = "tx", "rx";
1363 interrupts = <28 IRQ_TYPE_LEVEL_HIGH 7>;
1364 clocks = <&uart4_clk>;
1365 clock-names = "usart";
1366 status = "disabled";
1369 flx2: flexcom@fc010000 {
1370 compatible = "atmel,sama5d2-flexcom";
1371 reg = <0xfc010000 0x200>;
1372 clocks = <&flx2_clk>;
1373 #address-cells = <1>;
1375 ranges = <0x0 0xfc010000 0x800>;
1376 status = "disabled";
1379 flx3: flexcom@fc014000 {
1380 compatible = "atmel,sama5d2-flexcom";
1381 reg = <0xfc014000 0x200>;
1382 clocks = <&flx3_clk>;
1383 #address-cells = <1>;
1385 ranges = <0x0 0xfc014000 0x800>;
1386 status = "disabled";
1389 flx4: flexcom@fc018000 {
1390 compatible = "atmel,sama5d2-flexcom";
1391 reg = <0xfc018000 0x200>;
1392 clocks = <&flx4_clk>;
1393 #address-cells = <1>;
1395 ranges = <0x0 0xfc018000 0x800>;
1396 status = "disabled";
1400 compatible = "atmel,at91sam9g45-trng";
1401 reg = <0xfc01c000 0x100>;
1402 interrupts = <47 IRQ_TYPE_LEVEL_HIGH 0>;
1403 clocks = <&trng_clk>;
1406 aic: interrupt-controller@fc020000 {
1407 #interrupt-cells = <3>;
1408 compatible = "atmel,sama5d2-aic";
1409 interrupt-controller;
1410 reg = <0xfc020000 0x200>;
1411 atmel,external-irqs = <49>;
1414 i2c1: i2c@fc028000 {
1415 compatible = "atmel,sama5d2-i2c";
1416 reg = <0xfc028000 0x100>;
1417 interrupts = <30 IRQ_TYPE_LEVEL_HIGH 7>;
1419 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
1420 AT91_XDMAC_DT_PERID(2))>,
1422 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
1423 AT91_XDMAC_DT_PERID(3))>;
1424 dma-names = "tx", "rx";
1425 #address-cells = <1>;
1427 clocks = <&twi1_clk>;
1428 atmel,fifo-size = <16>;
1429 status = "disabled";
1433 compatible = "atmel,sama5d2-adc";
1434 reg = <0xfc030000 0x100>;
1435 interrupts = <40 IRQ_TYPE_LEVEL_HIGH 7>;
1436 clocks = <&adc_clk>;
1437 clock-names = "adc_clk";
1438 dmas = <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | AT91_XDMAC_DT_PERID(25))>;
1440 atmel,min-sample-rate-hz = <200000>;
1441 atmel,max-sample-rate-hz = <20000000>;
1442 atmel,startup-time-ms = <4>;
1443 atmel,trigger-edge-type = <IRQ_TYPE_EDGE_RISING>;
1444 #io-channel-cells = <1>;
1445 status = "disabled";
1448 resistive_touch: resistive-touch {
1449 compatible = "resistive-adc-touch";
1450 io-channels = <&adc AT91_SAMA5D2_ADC_X_CHANNEL>,
1451 <&adc AT91_SAMA5D2_ADC_Y_CHANNEL>,
1452 <&adc AT91_SAMA5D2_ADC_P_CHANNEL>;
1453 io-channel-names = "x", "y", "pressure";
1454 touchscreen-min-pressure = <50000>;
1455 status = "disabled";
1458 pioA: pinctrl@fc038000 {
1459 compatible = "atmel,sama5d2-pinctrl";
1460 reg = <0xfc038000 0x600>;
1461 interrupts = <18 IRQ_TYPE_LEVEL_HIGH 7>,
1462 <68 IRQ_TYPE_LEVEL_HIGH 7>,
1463 <69 IRQ_TYPE_LEVEL_HIGH 7>,
1464 <70 IRQ_TYPE_LEVEL_HIGH 7>;
1465 interrupt-controller;
1466 #interrupt-cells = <2>;
1469 clocks = <&pioA_clk>;
1473 compatible = "atmel,sama5d2-secumod", "syscon";
1474 reg = <0xfc040000 0x100>;
1478 compatible = "atmel,at91sam9g46-tdes";
1479 reg = <0xfc044000 0x100>;
1480 interrupts = <11 IRQ_TYPE_LEVEL_HIGH 0>;
1482 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
1483 AT91_XDMAC_DT_PERID(28))>,
1485 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
1486 AT91_XDMAC_DT_PERID(29))>;
1487 dma-names = "tx", "rx";
1488 clocks = <&tdes_clk>;
1489 clock-names = "tdes_clk";
1493 classd: classd@fc048000 {
1494 compatible = "atmel,sama5d2-classd";
1495 reg = <0xfc048000 0x100>;
1496 interrupts = <59 IRQ_TYPE_LEVEL_HIGH 7>;
1498 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
1499 AT91_XDMAC_DT_PERID(47))>;
1501 clocks = <&classd_clk>, <&classd_gclk>;
1502 clock-names = "pclk", "gclk";
1503 status = "disabled";
1506 i2s1: i2s@fc04c000 {
1507 compatible = "atmel,sama5d2-i2s";
1508 reg = <0xfc04c000 0x100>;
1509 interrupts = <55 IRQ_TYPE_LEVEL_HIGH 7>;
1511 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
1512 AT91_XDMAC_DT_PERID(33))>,
1514 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
1515 AT91_XDMAC_DT_PERID(34))>;
1516 dma-names = "tx", "rx";
1517 clocks = <&i2s1_clk>, <&i2s1_gclk>;
1518 clock-names = "pclk", "gclk";
1519 assigned-clocks = <&i2s1muxck>;
1520 assigned-parrents = <&i2s1_gclk>;
1521 status = "disabled";
1524 can1: can@fc050000 {
1525 compatible = "bosch,m_can";
1526 reg = <0xfc050000 0x4000>, <0x210000 0x4000>;
1527 reg-names = "m_can", "message_ram";
1528 interrupts = <57 IRQ_TYPE_LEVEL_HIGH 7>,
1529 <65 IRQ_TYPE_LEVEL_HIGH 7>;
1530 interrupt-names = "int0", "int1";
1531 clocks = <&can1_clk>, <&can1_gclk>;
1532 clock-names = "hclk", "cclk";
1533 assigned-clocks = <&can1_gclk>;
1534 assigned-clock-parents = <&utmi>;
1535 assigned-clock-rates = <40000000>;
1536 bosch,mram-cfg = <0x1100 0 0 64 0 0 32 32>;
1537 status = "disabled";
1540 sfrbu: sfr@fc05c000 {
1541 compatible = "atmel,sama5d2-sfrbu", "syscon";
1542 reg = <0xfc05c000 0x20>;
1546 compatible = "atmel,sama5d2-chipid";
1547 reg = <0xfc069000 0x8>;