2 * sama5d2.dtsi - Device Tree Include file for SAMA5D2 family SoC
4 * Copyright (C) 2015 Atmel,
5 * 2015 Ludovic Desroches <ludovic.desroches@atmel.com>
7 * This file is dual-licensed: you can use it either under the terms
8 * of the GPL or the X11 license, at your option. Note that this dual
9 * licensing only applies to this file, and not this project as a
12 * a) This file is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of the
15 * License, or (at your option) any later version.
17 * This file is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
24 * b) Permission is hereby granted, free of charge, to any person
25 * obtaining a copy of this software and associated documentation
26 * files (the "Software"), to deal in the Software without
27 * restriction, including without limitation the rights to use,
28 * copy, modify, merge, publish, distribute, sublicense, and/or
29 * sell copies of the Software, and to permit persons to whom the
30 * Software is furnished to do so, subject to the following
33 * The above copyright notice and this permission notice shall be
34 * included in all copies or substantial portions of the Software.
36 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
37 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
38 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
39 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
40 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
41 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
42 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
43 * OTHER DEALINGS IN THE SOFTWARE.
46 #include <dt-bindings/dma/at91.h>
47 #include <dt-bindings/interrupt-controller/irq.h>
48 #include <dt-bindings/clock/at91.h>
49 #include <dt-bindings/iio/adc/at91-sama5d2_adc.h>
54 model = "Atmel SAMA5D2 family SoC";
55 compatible = "atmel,sama5d2";
56 interrupt-parent = <&aic>;
73 compatible = "arm,cortex-a5";
75 next-level-cache = <&L2>;
80 compatible = "arm,cortex-a5-pmu";
81 interrupts = <2 IRQ_TYPE_LEVEL_HIGH 0>;
85 compatible = "arm,coresight-etb10", "arm,primecell";
86 reg = <0x740000 0x1000>;
88 clocks = <&pmc PMC_TYPE_CORE PMC_MCK>;
89 clock-names = "apb_pclk";
94 remote-endpoint = <&etm_out>;
101 compatible = "arm,coresight-etm3x", "arm,primecell";
102 reg = <0x73C000 0x1000>;
104 clocks = <&pmc PMC_TYPE_CORE PMC_MCK>;
105 clock-names = "apb_pclk";
110 remote-endpoint = <&etb_in>;
117 device_type = "memory";
118 reg = <0x20000000 0x20000000>;
122 slow_xtal: slow_xtal {
123 compatible = "fixed-clock";
125 clock-frequency = <0>;
128 main_xtal: main_xtal {
129 compatible = "fixed-clock";
131 clock-frequency = <0>;
135 ns_sram: sram@200000 {
136 compatible = "mmio-sram";
137 reg = <0x00200000 0x20000>;
141 compatible = "simple-bus";
142 #address-cells = <1>;
146 nfc_sram: sram@100000 {
147 compatible = "mmio-sram";
149 reg = <0x00100000 0x2400>;
152 usb0: gadget@300000 {
153 #address-cells = <1>;
155 compatible = "atmel,sama5d3-udc";
156 reg = <0x00300000 0x100000
158 interrupts = <42 IRQ_TYPE_LEVEL_HIGH 2>;
159 clocks = <&pmc PMC_TYPE_PERIPHERAL 42>, <&pmc PMC_TYPE_CORE PMC_UTMI>;
160 clock-names = "pclk", "hclk";
165 atmel,fifo-size = <64>;
166 atmel,nb-banks = <1>;
171 atmel,fifo-size = <1024>;
172 atmel,nb-banks = <3>;
179 atmel,fifo-size = <1024>;
180 atmel,nb-banks = <3>;
187 atmel,fifo-size = <1024>;
188 atmel,nb-banks = <2>;
195 atmel,fifo-size = <1024>;
196 atmel,nb-banks = <2>;
203 atmel,fifo-size = <1024>;
204 atmel,nb-banks = <2>;
211 atmel,fifo-size = <1024>;
212 atmel,nb-banks = <2>;
219 atmel,fifo-size = <1024>;
220 atmel,nb-banks = <2>;
227 atmel,fifo-size = <1024>;
228 atmel,nb-banks = <2>;
234 atmel,fifo-size = <1024>;
235 atmel,nb-banks = <2>;
241 atmel,fifo-size = <1024>;
242 atmel,nb-banks = <2>;
248 atmel,fifo-size = <1024>;
249 atmel,nb-banks = <2>;
255 atmel,fifo-size = <1024>;
256 atmel,nb-banks = <2>;
262 atmel,fifo-size = <1024>;
263 atmel,nb-banks = <2>;
269 atmel,fifo-size = <1024>;
270 atmel,nb-banks = <2>;
276 atmel,fifo-size = <1024>;
277 atmel,nb-banks = <2>;
283 compatible = "atmel,at91rm9200-ohci", "usb-ohci";
284 reg = <0x00400000 0x100000>;
285 interrupts = <41 IRQ_TYPE_LEVEL_HIGH 2>;
286 clocks = <&pmc PMC_TYPE_PERIPHERAL 41>, <&pmc PMC_TYPE_PERIPHERAL 41>, <&pmc PMC_TYPE_SYSTEM 6>;
287 clock-names = "ohci_clk", "hclk", "uhpck";
292 compatible = "atmel,at91sam9g45-ehci", "usb-ehci";
293 reg = <0x00500000 0x100000>;
294 interrupts = <41 IRQ_TYPE_LEVEL_HIGH 2>;
295 clocks = <&pmc PMC_TYPE_CORE PMC_UTMI>, <&pmc PMC_TYPE_PERIPHERAL 41>;
296 clock-names = "usb_clk", "ehci_clk";
300 L2: cache-controller@a00000 {
301 compatible = "arm,pl310-cache";
302 reg = <0x00a00000 0x1000>;
303 interrupts = <63 IRQ_TYPE_LEVEL_HIGH 4>;
309 compatible = "atmel,sama5d3-ebi";
310 #address-cells = <2>;
313 reg = <0x10000000 0x10000000
314 0x60000000 0x30000000>;
315 ranges = <0x0 0x0 0x10000000 0x10000000
316 0x1 0x0 0x60000000 0x10000000
317 0x2 0x0 0x70000000 0x10000000
318 0x3 0x0 0x80000000 0x10000000>;
319 clocks = <&pmc PMC_TYPE_CORE PMC_MCK2>;
322 nand_controller: nand-controller {
323 compatible = "atmel,sama5d3-nand-controller";
324 atmel,nfc-sram = <&nfc_sram>;
325 atmel,nfc-io = <&nfc_io>;
326 ecc-engine = <&pmecc>;
327 #address-cells = <2>;
334 sdmmc0: sdio-host@a0000000 {
335 compatible = "atmel,sama5d2-sdhci";
336 reg = <0xa0000000 0x300>;
337 interrupts = <31 IRQ_TYPE_LEVEL_HIGH 0>;
338 clocks = <&pmc PMC_TYPE_PERIPHERAL 31>, <&pmc PMC_TYPE_GCK 31>, <&pmc PMC_TYPE_CORE PMC_MAIN>;
339 clock-names = "hclock", "multclk", "baseclk";
343 sdmmc1: sdio-host@b0000000 {
344 compatible = "atmel,sama5d2-sdhci";
345 reg = <0xb0000000 0x300>;
346 interrupts = <32 IRQ_TYPE_LEVEL_HIGH 0>;
347 clocks = <&pmc PMC_TYPE_PERIPHERAL 32>, <&pmc PMC_TYPE_GCK 32>, <&pmc PMC_TYPE_CORE PMC_MAIN>;
348 clock-names = "hclock", "multclk", "baseclk";
352 nfc_io: nfc-io@c0000000 {
353 compatible = "atmel,sama5d3-nfc-io", "syscon";
354 reg = <0xc0000000 0x8000000>;
358 compatible = "simple-bus";
359 #address-cells = <1>;
363 hlcdc: hlcdc@f0000000 {
364 compatible = "atmel,sama5d2-hlcdc";
365 reg = <0xf0000000 0x2000>;
366 interrupts = <45 IRQ_TYPE_LEVEL_HIGH 0>;
367 clocks = <&pmc PMC_TYPE_PERIPHERAL 45>, <&pmc PMC_TYPE_SYSTEM 3>, <&clk32k>;
368 clock-names = "periph_clk","sys_clk", "slow_clk";
371 hlcdc-display-controller {
372 compatible = "atmel,hlcdc-display-controller";
373 #address-cells = <1>;
377 #address-cells = <1>;
383 hlcdc_pwm: hlcdc-pwm {
384 compatible = "atmel,hlcdc-pwm";
390 compatible = "atmel,sama5d2-isc";
391 reg = <0xf0008000 0x4000>;
392 interrupts = <46 IRQ_TYPE_LEVEL_HIGH 5>;
393 clocks = <&pmc PMC_TYPE_PERIPHERAL 46>, <&pmc PMC_TYPE_SYSTEM 18>, <&pmc PMC_TYPE_GCK 46>;
394 clock-names = "hclock", "iscck", "gck";
396 clock-output-names = "isc-mck";
400 ramc0: ramc@f000c000 {
401 compatible = "atmel,sama5d3-ddramc";
402 reg = <0xf000c000 0x200>;
403 clocks = <&pmc PMC_TYPE_SYSTEM 2>, <&pmc PMC_TYPE_PERIPHERAL 13>;
404 clock-names = "ddrck", "mpddr";
407 dma0: dma-controller@f0010000 {
408 compatible = "atmel,sama5d4-dma";
409 reg = <0xf0010000 0x1000>;
410 interrupts = <6 IRQ_TYPE_LEVEL_HIGH 0>;
412 clocks = <&pmc PMC_TYPE_PERIPHERAL 6>;
413 clock-names = "dma_clk";
416 /* Place dma1 here despite its address */
417 dma1: dma-controller@f0004000 {
418 compatible = "atmel,sama5d4-dma";
419 reg = <0xf0004000 0x1000>;
420 interrupts = <7 IRQ_TYPE_LEVEL_HIGH 0>;
422 clocks = <&pmc PMC_TYPE_PERIPHERAL 7>;
423 clock-names = "dma_clk";
427 compatible = "atmel,sama5d2-pmc", "syscon";
428 reg = <0xf0014000 0x160>;
429 interrupts = <74 IRQ_TYPE_LEVEL_HIGH 7>;
431 clocks = <&clk32k>, <&main_xtal>;
432 clock-names = "slow_clk", "main_xtal";
435 qspi0: spi@f0020000 {
436 compatible = "atmel,sama5d2-qspi";
437 reg = <0xf0020000 0x100>, <0xd0000000 0x08000000>;
438 reg-names = "qspi_base", "qspi_mmap";
439 interrupts = <52 IRQ_TYPE_LEVEL_HIGH 7>;
440 clocks = <&pmc PMC_TYPE_PERIPHERAL 52>;
441 #address-cells = <1>;
446 qspi1: spi@f0024000 {
447 compatible = "atmel,sama5d2-qspi";
448 reg = <0xf0024000 0x100>, <0xd8000000 0x08000000>;
449 reg-names = "qspi_base", "qspi_mmap";
450 interrupts = <53 IRQ_TYPE_LEVEL_HIGH 7>;
451 clocks = <&pmc PMC_TYPE_PERIPHERAL 53>;
452 #address-cells = <1>;
458 compatible = "atmel,at91sam9g46-sha";
459 reg = <0xf0028000 0x100>;
460 interrupts = <12 IRQ_TYPE_LEVEL_HIGH 0>;
462 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
463 AT91_XDMAC_DT_PERID(30))>;
465 clocks = <&pmc PMC_TYPE_PERIPHERAL 12>;
466 clock-names = "sha_clk";
471 compatible = "atmel,at91sam9g46-aes";
472 reg = <0xf002c000 0x100>;
473 interrupts = <9 IRQ_TYPE_LEVEL_HIGH 0>;
475 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
476 AT91_XDMAC_DT_PERID(26))>,
478 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
479 AT91_XDMAC_DT_PERID(27))>;
480 dma-names = "tx", "rx";
481 clocks = <&pmc PMC_TYPE_PERIPHERAL 9>;
482 clock-names = "aes_clk";
487 compatible = "atmel,at91rm9200-spi";
488 reg = <0xf8000000 0x100>;
489 interrupts = <33 IRQ_TYPE_LEVEL_HIGH 7>;
491 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
492 AT91_XDMAC_DT_PERID(6))>,
494 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
495 AT91_XDMAC_DT_PERID(7))>;
496 dma-names = "tx", "rx";
497 clocks = <&pmc PMC_TYPE_PERIPHERAL 33>;
498 clock-names = "spi_clk";
499 atmel,fifo-size = <16>;
500 #address-cells = <1>;
506 compatible = "atmel,at91sam9g45-ssc";
507 reg = <0xf8004000 0x4000>;
508 interrupts = <43 IRQ_TYPE_LEVEL_HIGH 4>;
510 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
511 AT91_XDMAC_DT_PERID(21))>,
513 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
514 AT91_XDMAC_DT_PERID(22))>;
515 dma-names = "tx", "rx";
516 clocks = <&pmc PMC_TYPE_PERIPHERAL 43>;
517 clock-names = "pclk";
521 macb0: ethernet@f8008000 {
522 compatible = "atmel,sama5d2-gem";
523 reg = <0xf8008000 0x1000>;
524 interrupts = <5 IRQ_TYPE_LEVEL_HIGH 3 /* Queue 0 */
525 66 IRQ_TYPE_LEVEL_HIGH 3 /* Queue 1 */
526 67 IRQ_TYPE_LEVEL_HIGH 3>; /* Queue 2 */
527 #address-cells = <1>;
529 clocks = <&pmc PMC_TYPE_PERIPHERAL 5>, <&pmc PMC_TYPE_PERIPHERAL 5>;
530 clock-names = "hclk", "pclk";
534 tcb0: timer@f800c000 {
535 compatible = "atmel,at91sam9x5-tcb", "simple-mfd", "syscon";
536 #address-cells = <1>;
538 reg = <0xf800c000 0x100>;
539 interrupts = <35 IRQ_TYPE_LEVEL_HIGH 0>;
540 clocks = <&pmc PMC_TYPE_PERIPHERAL 35>, <&clk32k>;
541 clock-names = "t0_clk", "slow_clk";
544 tcb1: timer@f8010000 {
545 compatible = "atmel,at91sam9x5-tcb", "simple-mfd", "syscon";
546 #address-cells = <1>;
548 reg = <0xf8010000 0x100>;
549 interrupts = <36 IRQ_TYPE_LEVEL_HIGH 0>;
550 clocks = <&pmc PMC_TYPE_PERIPHERAL 36>, <&clk32k>;
551 clock-names = "t0_clk", "slow_clk";
554 hsmc: hsmc@f8014000 {
555 compatible = "atmel,sama5d2-smc", "syscon", "simple-mfd";
556 reg = <0xf8014000 0x1000>;
557 interrupts = <17 IRQ_TYPE_LEVEL_HIGH 6>;
558 clocks = <&pmc PMC_TYPE_PERIPHERAL 17>;
559 #address-cells = <1>;
563 pmecc: ecc-engine@f8014070 {
564 compatible = "atmel,sama5d2-pmecc";
565 reg = <0xf8014070 0x490>,
570 pdmic: pdmic@f8018000 {
571 compatible = "atmel,sama5d2-pdmic";
572 reg = <0xf8018000 0x124>;
573 interrupts = <48 IRQ_TYPE_LEVEL_HIGH 7>;
575 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
576 | AT91_XDMAC_DT_PERID(50))>;
578 clocks = <&pmc PMC_TYPE_PERIPHERAL 48>, <&pmc PMC_TYPE_GCK 48>;
579 clock-names = "pclk", "gclk";
583 uart0: serial@f801c000 {
584 compatible = "atmel,at91sam9260-usart";
585 reg = <0xf801c000 0x100>;
586 interrupts = <24 IRQ_TYPE_LEVEL_HIGH 7>;
588 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
589 AT91_XDMAC_DT_PERID(35))>,
591 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
592 AT91_XDMAC_DT_PERID(36))>;
593 dma-names = "tx", "rx";
594 clocks = <&pmc PMC_TYPE_PERIPHERAL 24>;
595 clock-names = "usart";
599 uart1: serial@f8020000 {
600 compatible = "atmel,at91sam9260-usart";
601 reg = <0xf8020000 0x100>;
602 interrupts = <25 IRQ_TYPE_LEVEL_HIGH 7>;
604 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
605 AT91_XDMAC_DT_PERID(37))>,
607 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
608 AT91_XDMAC_DT_PERID(38))>;
609 dma-names = "tx", "rx";
610 clocks = <&pmc PMC_TYPE_PERIPHERAL 25>;
611 clock-names = "usart";
615 uart2: serial@f8024000 {
616 compatible = "atmel,at91sam9260-usart";
617 reg = <0xf8024000 0x100>;
618 interrupts = <26 IRQ_TYPE_LEVEL_HIGH 7>;
620 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
621 AT91_XDMAC_DT_PERID(39))>,
623 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
624 AT91_XDMAC_DT_PERID(40))>;
625 dma-names = "tx", "rx";
626 clocks = <&pmc PMC_TYPE_PERIPHERAL 26>;
627 clock-names = "usart";
632 compatible = "atmel,sama5d2-i2c";
633 reg = <0xf8028000 0x100>;
634 interrupts = <29 IRQ_TYPE_LEVEL_HIGH 7>;
636 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
637 AT91_XDMAC_DT_PERID(0))>,
639 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
640 AT91_XDMAC_DT_PERID(1))>;
641 dma-names = "tx", "rx";
642 #address-cells = <1>;
644 clocks = <&pmc PMC_TYPE_PERIPHERAL 29>;
645 atmel,fifo-size = <16>;
650 compatible = "atmel,sama5d2-pwm";
651 reg = <0xf802c000 0x4000>;
652 interrupts = <38 IRQ_TYPE_LEVEL_HIGH 7>;
654 clocks = <&pmc PMC_TYPE_PERIPHERAL 38>;
658 compatible = "atmel,sama5d2-sfr", "syscon";
659 reg = <0xf8030000 0x98>;
662 flx0: flexcom@f8034000 {
663 compatible = "atmel,sama5d2-flexcom";
664 reg = <0xf8034000 0x200>;
665 clocks = <&pmc PMC_TYPE_PERIPHERAL 19>;
666 #address-cells = <1>;
668 ranges = <0x0 0xf8034000 0x800>;
672 flx1: flexcom@f8038000 {
673 compatible = "atmel,sama5d2-flexcom";
674 reg = <0xf8038000 0x200>;
675 clocks = <&pmc PMC_TYPE_PERIPHERAL 20>;
676 #address-cells = <1>;
678 ranges = <0x0 0xf8038000 0x800>;
682 securam: sram@f8044000 {
683 compatible = "atmel,sama5d2-securam", "mmio-sram";
684 reg = <0xf8044000 0x1420>;
685 clocks = <&pmc PMC_TYPE_PERIPHERAL 51>;
686 #address-cells = <1>;
688 ranges = <0 0xf8044000 0x1420>;
692 compatible = "atmel,sama5d3-rstc";
693 reg = <0xf8048000 0x10>;
698 compatible = "atmel,sama5d2-shdwc";
699 reg = <0xf8048010 0x10>;
701 #address-cells = <1>;
703 atmel,wakeup-rtc-timer;
706 pit: timer@f8048030 {
707 compatible = "atmel,at91sam9260-pit";
708 reg = <0xf8048030 0x10>;
709 interrupts = <3 IRQ_TYPE_LEVEL_HIGH 5>;
710 clocks = <&pmc PMC_TYPE_CORE PMC_MCK2>;
714 compatible = "atmel,sama5d4-wdt";
715 reg = <0xf8048040 0x10>;
716 interrupts = <4 IRQ_TYPE_LEVEL_HIGH 7>;
721 clk32k: sckc@f8048050 {
722 compatible = "atmel,sama5d4-sckc";
723 reg = <0xf8048050 0x4>;
725 clocks = <&slow_xtal>;
730 compatible = "atmel,at91rm9200-rtc";
731 reg = <0xf80480b0 0x30>;
732 interrupts = <74 IRQ_TYPE_LEVEL_HIGH 7>;
737 compatible = "atmel,sama5d2-i2s";
738 reg = <0xf8050000 0x100>;
739 interrupts = <54 IRQ_TYPE_LEVEL_HIGH 7>;
741 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
742 AT91_XDMAC_DT_PERID(31))>,
744 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
745 AT91_XDMAC_DT_PERID(32))>;
746 dma-names = "tx", "rx";
747 clocks = <&pmc PMC_TYPE_PERIPHERAL 54>, <&pmc PMC_TYPE_GCK 54>;
748 clock-names = "pclk", "gclk";
749 assigned-clocks = <&pmc PMC_TYPE_CORE PMC_I2S0_MUX>;
750 assigned-clock-parents = <&pmc PMC_TYPE_GCK 54>;
755 compatible = "bosch,m_can";
756 reg = <0xf8054000 0x4000>, <0x210000 0x4000>;
757 reg-names = "m_can", "message_ram";
758 interrupts = <56 IRQ_TYPE_LEVEL_HIGH 7>,
759 <64 IRQ_TYPE_LEVEL_HIGH 7>;
760 interrupt-names = "int0", "int1";
761 clocks = <&pmc PMC_TYPE_PERIPHERAL 56>, <&pmc PMC_TYPE_GCK 56>;
762 clock-names = "hclk", "cclk";
763 assigned-clocks = <&pmc PMC_TYPE_GCK 56>;
764 assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_UTMI>;
765 assigned-clock-rates = <40000000>;
766 bosch,mram-cfg = <0x0 0 0 64 0 0 32 32>;
771 compatible = "atmel,at91rm9200-spi";
772 reg = <0xfc000000 0x100>;
773 interrupts = <34 IRQ_TYPE_LEVEL_HIGH 7>;
775 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
776 AT91_XDMAC_DT_PERID(8))>,
778 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
779 AT91_XDMAC_DT_PERID(9))>;
780 dma-names = "tx", "rx";
781 clocks = <&pmc PMC_TYPE_PERIPHERAL 34>;
782 clock-names = "spi_clk";
783 atmel,fifo-size = <16>;
784 #address-cells = <1>;
789 uart3: serial@fc008000 {
790 compatible = "atmel,at91sam9260-usart";
791 reg = <0xfc008000 0x100>;
792 interrupts = <27 IRQ_TYPE_LEVEL_HIGH 7>;
794 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
795 AT91_XDMAC_DT_PERID(41))>,
797 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
798 AT91_XDMAC_DT_PERID(42))>;
799 dma-names = "tx", "rx";
800 clocks = <&pmc PMC_TYPE_PERIPHERAL 27>;
801 clock-names = "usart";
805 uart4: serial@fc00c000 {
806 compatible = "atmel,at91sam9260-usart";
807 reg = <0xfc00c000 0x100>;
809 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
810 AT91_XDMAC_DT_PERID(43))>,
812 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
813 AT91_XDMAC_DT_PERID(44))>;
814 dma-names = "tx", "rx";
815 interrupts = <28 IRQ_TYPE_LEVEL_HIGH 7>;
816 clocks = <&pmc PMC_TYPE_PERIPHERAL 28>;
817 clock-names = "usart";
821 flx2: flexcom@fc010000 {
822 compatible = "atmel,sama5d2-flexcom";
823 reg = <0xfc010000 0x200>;
824 clocks = <&pmc PMC_TYPE_PERIPHERAL 21>;
825 #address-cells = <1>;
827 ranges = <0x0 0xfc010000 0x800>;
831 flx3: flexcom@fc014000 {
832 compatible = "atmel,sama5d2-flexcom";
833 reg = <0xfc014000 0x200>;
834 clocks = <&pmc PMC_TYPE_PERIPHERAL 22>;
835 #address-cells = <1>;
837 ranges = <0x0 0xfc014000 0x800>;
841 flx4: flexcom@fc018000 {
842 compatible = "atmel,sama5d2-flexcom";
843 reg = <0xfc018000 0x200>;
844 clocks = <&pmc PMC_TYPE_PERIPHERAL 23>;
845 #address-cells = <1>;
847 ranges = <0x0 0xfc018000 0x800>;
852 compatible = "atmel,at91sam9g45-trng";
853 reg = <0xfc01c000 0x100>;
854 interrupts = <47 IRQ_TYPE_LEVEL_HIGH 0>;
855 clocks = <&pmc PMC_TYPE_PERIPHERAL 47>;
858 aic: interrupt-controller@fc020000 {
859 #interrupt-cells = <3>;
860 compatible = "atmel,sama5d2-aic";
861 interrupt-controller;
862 reg = <0xfc020000 0x200>;
863 atmel,external-irqs = <49>;
867 compatible = "atmel,sama5d2-i2c";
868 reg = <0xfc028000 0x100>;
869 interrupts = <30 IRQ_TYPE_LEVEL_HIGH 7>;
871 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
872 AT91_XDMAC_DT_PERID(2))>,
874 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
875 AT91_XDMAC_DT_PERID(3))>;
876 dma-names = "tx", "rx";
877 #address-cells = <1>;
879 clocks = <&pmc PMC_TYPE_PERIPHERAL 30>;
880 atmel,fifo-size = <16>;
885 compatible = "atmel,sama5d2-adc";
886 reg = <0xfc030000 0x100>;
887 interrupts = <40 IRQ_TYPE_LEVEL_HIGH 7>;
888 clocks = <&pmc PMC_TYPE_PERIPHERAL 40>;
889 clock-names = "adc_clk";
890 dmas = <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | AT91_XDMAC_DT_PERID(25))>;
892 atmel,min-sample-rate-hz = <200000>;
893 atmel,max-sample-rate-hz = <20000000>;
894 atmel,startup-time-ms = <4>;
895 atmel,trigger-edge-type = <IRQ_TYPE_EDGE_RISING>;
896 #io-channel-cells = <1>;
900 resistive_touch: resistive-touch {
901 compatible = "resistive-adc-touch";
902 io-channels = <&adc AT91_SAMA5D2_ADC_X_CHANNEL>,
903 <&adc AT91_SAMA5D2_ADC_Y_CHANNEL>,
904 <&adc AT91_SAMA5D2_ADC_P_CHANNEL>;
905 io-channel-names = "x", "y", "pressure";
906 touchscreen-min-pressure = <50000>;
910 pioA: pinctrl@fc038000 {
911 compatible = "atmel,sama5d2-pinctrl";
912 reg = <0xfc038000 0x600>;
913 interrupts = <18 IRQ_TYPE_LEVEL_HIGH 7>,
914 <68 IRQ_TYPE_LEVEL_HIGH 7>,
915 <69 IRQ_TYPE_LEVEL_HIGH 7>,
916 <70 IRQ_TYPE_LEVEL_HIGH 7>;
917 interrupt-controller;
918 #interrupt-cells = <2>;
921 clocks = <&pmc PMC_TYPE_PERIPHERAL 18>;
925 compatible = "atmel,sama5d2-secumod", "syscon";
926 reg = <0xfc040000 0x100>;
930 compatible = "atmel,at91sam9g46-tdes";
931 reg = <0xfc044000 0x100>;
932 interrupts = <11 IRQ_TYPE_LEVEL_HIGH 0>;
934 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
935 AT91_XDMAC_DT_PERID(28))>,
937 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
938 AT91_XDMAC_DT_PERID(29))>;
939 dma-names = "tx", "rx";
940 clocks = <&pmc PMC_TYPE_PERIPHERAL 11>;
941 clock-names = "tdes_clk";
945 classd: classd@fc048000 {
946 compatible = "atmel,sama5d2-classd";
947 reg = <0xfc048000 0x100>;
948 interrupts = <59 IRQ_TYPE_LEVEL_HIGH 7>;
950 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
951 AT91_XDMAC_DT_PERID(47))>;
953 clocks = <&pmc PMC_TYPE_PERIPHERAL 59>, <&pmc PMC_TYPE_GCK 59>;
954 clock-names = "pclk", "gclk";
959 compatible = "atmel,sama5d2-i2s";
960 reg = <0xfc04c000 0x100>;
961 interrupts = <55 IRQ_TYPE_LEVEL_HIGH 7>;
963 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
964 AT91_XDMAC_DT_PERID(33))>,
966 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
967 AT91_XDMAC_DT_PERID(34))>;
968 dma-names = "tx", "rx";
969 clocks = <&pmc PMC_TYPE_PERIPHERAL 55>, <&pmc PMC_TYPE_GCK 55>;
970 clock-names = "pclk", "gclk";
971 assigned-clocks = <&pmc PMC_TYPE_CORE PMC_I2S1_MUX>;
972 assigned-parrents = <&pmc PMC_TYPE_GCK 55>;
977 compatible = "bosch,m_can";
978 reg = <0xfc050000 0x4000>, <0x210000 0x4000>;
979 reg-names = "m_can", "message_ram";
980 interrupts = <57 IRQ_TYPE_LEVEL_HIGH 7>,
981 <65 IRQ_TYPE_LEVEL_HIGH 7>;
982 interrupt-names = "int0", "int1";
983 clocks = <&pmc PMC_TYPE_PERIPHERAL 57>, <&pmc PMC_TYPE_GCK 57>;
984 clock-names = "hclk", "cclk";
985 assigned-clocks = <&pmc PMC_TYPE_GCK 57>;
986 assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_UTMI>;
987 assigned-clock-rates = <40000000>;
988 bosch,mram-cfg = <0x1100 0 0 64 0 0 32 32>;
992 sfrbu: sfr@fc05c000 {
993 compatible = "atmel,sama5d2-sfrbu", "syscon";
994 reg = <0xfc05c000 0x20>;
998 compatible = "atmel,sama5d2-chipid";
999 reg = <0xfc069000 0x8>;