2 * Copyright (C) 2012 Altera <www.altera.com>
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
14 * You should have received a copy of the GNU General Public License
15 * along with this program. If not, see <http://www.gnu.org/licenses/>.
18 #include <dt-bindings/reset/altr,rst-mgr.h>
36 enable-method = "altr,socfpga-smp";
39 compatible = "arm,cortex-a9";
42 next-level-cache = <&L2>;
45 compatible = "arm,cortex-a9";
48 next-level-cache = <&L2>;
53 compatible = "arm,cortex-a9-pmu";
54 interrupt-parent = <&intc>;
55 interrupts = <0 176 4>, <0 177 4>;
56 interrupt-affinity = <&cpu0>, <&cpu1>;
57 reg = <0xff111000 0x1000>,
62 compatible = "arm,cortex-a9-gic";
63 #interrupt-cells = <3>;
65 reg = <0xfffed000 0x1000>,
72 compatible = "simple-bus";
74 interrupt-parent = <&intc>;
78 compatible = "simple-bus";
84 compatible = "arm,pl330", "arm,primecell";
85 reg = <0xffe01000 0x1000>;
86 interrupts = <0 104 4>,
97 clocks = <&l4_main_clk>;
98 clock-names = "apb_pclk";
103 compatible = "fpga-region";
104 fpga-mgr = <&fpgamgr0>;
106 #address-cells = <0x1>;
111 compatible = "bosch,d_can";
112 reg = <0xffc00000 0x1000>;
113 interrupts = <0 131 4>, <0 132 4>, <0 133 4>, <0 134 4>;
114 clocks = <&can0_clk>;
119 compatible = "bosch,d_can";
120 reg = <0xffc01000 0x1000>;
121 interrupts = <0 135 4>, <0 136 4>, <0 137 4>, <0 138 4>;
122 clocks = <&can1_clk>;
127 compatible = "altr,clk-mgr";
128 reg = <0xffd04000 0x1000>;
131 #address-cells = <1>;
136 compatible = "fixed-clock";
141 compatible = "fixed-clock";
144 f2s_periph_ref_clk: f2s_periph_ref_clk {
146 compatible = "fixed-clock";
149 f2s_sdram_ref_clk: f2s_sdram_ref_clk {
151 compatible = "fixed-clock";
154 main_pll: main_pll@40 {
155 #address-cells = <1>;
158 compatible = "altr,socfpga-pll-clock";
164 compatible = "altr,socfpga-perip-clk";
165 clocks = <&main_pll>;
166 div-reg = <0xe0 0 9>;
170 mainclk: mainclk@4c {
172 compatible = "altr,socfpga-perip-clk";
173 clocks = <&main_pll>;
174 div-reg = <0xe4 0 9>;
178 dbg_base_clk: dbg_base_clk@50 {
180 compatible = "altr,socfpga-perip-clk";
181 clocks = <&main_pll>, <&osc1>;
182 div-reg = <0xe8 0 9>;
186 main_qspi_clk: main_qspi_clk@54 {
188 compatible = "altr,socfpga-perip-clk";
189 clocks = <&main_pll>;
193 main_nand_sdmmc_clk: main_nand_sdmmc_clk@58 {
195 compatible = "altr,socfpga-perip-clk";
196 clocks = <&main_pll>;
200 cfg_h2f_usr0_clk: cfg_h2f_usr0_clk@5c {
202 compatible = "altr,socfpga-perip-clk";
203 clocks = <&main_pll>;
208 periph_pll: periph_pll@80 {
209 #address-cells = <1>;
212 compatible = "altr,socfpga-pll-clock";
213 clocks = <&osc1>, <&osc2>, <&f2s_periph_ref_clk>;
216 emac0_clk: emac0_clk@88 {
218 compatible = "altr,socfpga-perip-clk";
219 clocks = <&periph_pll>;
223 emac1_clk: emac1_clk@8c {
225 compatible = "altr,socfpga-perip-clk";
226 clocks = <&periph_pll>;
230 per_qspi_clk: per_qsi_clk@90 {
232 compatible = "altr,socfpga-perip-clk";
233 clocks = <&periph_pll>;
237 per_nand_mmc_clk: per_nand_mmc_clk@94 {
239 compatible = "altr,socfpga-perip-clk";
240 clocks = <&periph_pll>;
244 per_base_clk: per_base_clk@98 {
246 compatible = "altr,socfpga-perip-clk";
247 clocks = <&periph_pll>;
251 h2f_usr1_clk: h2f_usr1_clk@9c {
253 compatible = "altr,socfpga-perip-clk";
254 clocks = <&periph_pll>;
259 sdram_pll: sdram_pll@c0 {
260 #address-cells = <1>;
263 compatible = "altr,socfpga-pll-clock";
264 clocks = <&osc1>, <&osc2>, <&f2s_sdram_ref_clk>;
267 ddr_dqs_clk: ddr_dqs_clk@c8 {
269 compatible = "altr,socfpga-perip-clk";
270 clocks = <&sdram_pll>;
274 ddr_2x_dqs_clk: ddr_2x_dqs_clk@cc {
276 compatible = "altr,socfpga-perip-clk";
277 clocks = <&sdram_pll>;
281 ddr_dq_clk: ddr_dq_clk@d0 {
283 compatible = "altr,socfpga-perip-clk";
284 clocks = <&sdram_pll>;
288 h2f_usr2_clk: h2f_usr2_clk@d4 {
290 compatible = "altr,socfpga-perip-clk";
291 clocks = <&sdram_pll>;
296 mpu_periph_clk: mpu_periph_clk {
298 compatible = "altr,socfpga-perip-clk";
303 mpu_l2_ram_clk: mpu_l2_ram_clk {
305 compatible = "altr,socfpga-perip-clk";
310 l4_main_clk: l4_main_clk {
312 compatible = "altr,socfpga-gate-clk";
317 l3_main_clk: l3_main_clk {
319 compatible = "altr,socfpga-perip-clk";
324 l3_mp_clk: l3_mp_clk {
326 compatible = "altr,socfpga-gate-clk";
328 div-reg = <0x64 0 2>;
332 l3_sp_clk: l3_sp_clk {
334 compatible = "altr,socfpga-gate-clk";
335 clocks = <&l3_mp_clk>;
336 div-reg = <0x64 2 2>;
339 l4_mp_clk: l4_mp_clk {
341 compatible = "altr,socfpga-gate-clk";
342 clocks = <&mainclk>, <&per_base_clk>;
343 div-reg = <0x64 4 3>;
347 l4_sp_clk: l4_sp_clk {
349 compatible = "altr,socfpga-gate-clk";
350 clocks = <&mainclk>, <&per_base_clk>;
351 div-reg = <0x64 7 3>;
355 dbg_at_clk: dbg_at_clk {
357 compatible = "altr,socfpga-gate-clk";
358 clocks = <&dbg_base_clk>;
359 div-reg = <0x68 0 2>;
365 compatible = "altr,socfpga-gate-clk";
366 clocks = <&dbg_at_clk>;
367 div-reg = <0x68 2 2>;
371 dbg_trace_clk: dbg_trace_clk {
373 compatible = "altr,socfpga-gate-clk";
374 clocks = <&dbg_base_clk>;
375 div-reg = <0x6C 0 3>;
379 dbg_timer_clk: dbg_timer_clk {
381 compatible = "altr,socfpga-gate-clk";
382 clocks = <&dbg_base_clk>;
388 compatible = "altr,socfpga-gate-clk";
389 clocks = <&cfg_h2f_usr0_clk>;
393 h2f_user0_clk: h2f_user0_clk {
395 compatible = "altr,socfpga-gate-clk";
396 clocks = <&cfg_h2f_usr0_clk>;
400 emac_0_clk: emac_0_clk {
402 compatible = "altr,socfpga-gate-clk";
403 clocks = <&emac0_clk>;
407 emac_1_clk: emac_1_clk {
409 compatible = "altr,socfpga-gate-clk";
410 clocks = <&emac1_clk>;
414 usb_mp_clk: usb_mp_clk {
416 compatible = "altr,socfpga-gate-clk";
417 clocks = <&per_base_clk>;
419 div-reg = <0xa4 0 3>;
422 spi_m_clk: spi_m_clk {
424 compatible = "altr,socfpga-gate-clk";
425 clocks = <&per_base_clk>;
427 div-reg = <0xa4 3 3>;
432 compatible = "altr,socfpga-gate-clk";
433 clocks = <&per_base_clk>;
435 div-reg = <0xa4 6 3>;
440 compatible = "altr,socfpga-gate-clk";
441 clocks = <&per_base_clk>;
443 div-reg = <0xa4 9 3>;
446 gpio_db_clk: gpio_db_clk {
448 compatible = "altr,socfpga-gate-clk";
449 clocks = <&per_base_clk>;
451 div-reg = <0xa8 0 24>;
454 h2f_user1_clk: h2f_user1_clk {
456 compatible = "altr,socfpga-gate-clk";
457 clocks = <&h2f_usr1_clk>;
461 sdmmc_clk: sdmmc_clk {
463 compatible = "altr,socfpga-gate-clk";
464 clocks = <&f2s_periph_ref_clk>, <&main_nand_sdmmc_clk>, <&per_nand_mmc_clk>;
469 sdmmc_clk_divided: sdmmc_clk_divided {
471 compatible = "altr,socfpga-gate-clk";
472 clocks = <&sdmmc_clk>;
477 nand_x_clk: nand_x_clk {
479 compatible = "altr,socfpga-gate-clk";
480 clocks = <&f2s_periph_ref_clk>, <&main_nand_sdmmc_clk>, <&per_nand_mmc_clk>;
484 nand_ecc_clk: nand_ecc_clk {
486 compatible = "altr,socfpga-gate-clk";
487 clocks = <&nand_x_clk>;
493 compatible = "altr,socfpga-gate-clk";
494 clocks = <&nand_x_clk>;
495 clk-gate = <0xa0 10>;
501 compatible = "altr,socfpga-gate-clk";
502 clocks = <&f2s_periph_ref_clk>, <&main_qspi_clk>, <&per_qspi_clk>;
503 clk-gate = <0xa0 11>;
506 ddr_dqs_clk_gate: ddr_dqs_clk_gate {
508 compatible = "altr,socfpga-gate-clk";
509 clocks = <&ddr_dqs_clk>;
513 ddr_2x_dqs_clk_gate: ddr_2x_dqs_clk_gate {
515 compatible = "altr,socfpga-gate-clk";
516 clocks = <&ddr_2x_dqs_clk>;
520 ddr_dq_clk_gate: ddr_dq_clk_gate {
522 compatible = "altr,socfpga-gate-clk";
523 clocks = <&ddr_dq_clk>;
527 h2f_user2_clk: h2f_user2_clk {
529 compatible = "altr,socfpga-gate-clk";
530 clocks = <&h2f_usr2_clk>;
537 fpga_bridge0: fpga_bridge@ff400000 {
538 compatible = "altr,socfpga-lwhps2fpga-bridge";
539 reg = <0xff400000 0x100000>;
540 resets = <&rst LWHPS2FPGA_RESET>;
541 clocks = <&l4_main_clk>;
544 fpga_bridge1: fpga_bridge@ff500000 {
545 compatible = "altr,socfpga-hps2fpga-bridge";
546 reg = <0xff500000 0x10000>;
547 resets = <&rst HPS2FPGA_RESET>;
548 clocks = <&l4_main_clk>;
551 fpgamgr0: fpgamgr@ff706000 {
552 compatible = "altr,socfpga-fpga-mgr";
553 reg = <0xff706000 0x1000
555 interrupts = <0 175 4>;
558 gmac0: ethernet@ff700000 {
559 compatible = "altr,socfpga-stmmac", "snps,dwmac-3.70a", "snps,dwmac";
560 altr,sysmgr-syscon = <&sysmgr 0x60 0>;
561 reg = <0xff700000 0x2000>;
562 interrupts = <0 115 4>;
563 interrupt-names = "macirq";
564 mac-address = [00 00 00 00 00 00];/* Filled in by U-Boot */
565 clocks = <&emac_0_clk>;
566 clock-names = "stmmaceth";
567 resets = <&rst EMAC0_RESET>;
568 reset-names = "stmmaceth";
569 snps,multicast-filter-bins = <256>;
570 snps,perfect-filter-entries = <128>;
571 tx-fifo-depth = <4096>;
572 rx-fifo-depth = <4096>;
576 gmac1: ethernet@ff702000 {
577 compatible = "altr,socfpga-stmmac", "snps,dwmac-3.70a", "snps,dwmac";
578 altr,sysmgr-syscon = <&sysmgr 0x60 2>;
579 reg = <0xff702000 0x2000>;
580 interrupts = <0 120 4>;
581 interrupt-names = "macirq";
582 mac-address = [00 00 00 00 00 00];/* Filled in by U-Boot */
583 clocks = <&emac_1_clk>;
584 clock-names = "stmmaceth";
585 resets = <&rst EMAC1_RESET>;
586 reset-names = "stmmaceth";
587 snps,multicast-filter-bins = <256>;
588 snps,perfect-filter-entries = <128>;
589 tx-fifo-depth = <4096>;
590 rx-fifo-depth = <4096>;
594 gpio0: gpio@ff708000 {
595 #address-cells = <1>;
597 compatible = "snps,dw-apb-gpio";
598 reg = <0xff708000 0x1000>;
599 clocks = <&l4_mp_clk>;
602 porta: gpio-controller@0 {
603 compatible = "snps,dw-apb-gpio-port";
606 snps,nr-gpios = <29>;
608 interrupt-controller;
609 #interrupt-cells = <2>;
610 interrupts = <0 164 4>;
614 gpio1: gpio@ff709000 {
615 #address-cells = <1>;
617 compatible = "snps,dw-apb-gpio";
618 reg = <0xff709000 0x1000>;
619 clocks = <&l4_mp_clk>;
622 portb: gpio-controller@0 {
623 compatible = "snps,dw-apb-gpio-port";
626 snps,nr-gpios = <29>;
628 interrupt-controller;
629 #interrupt-cells = <2>;
630 interrupts = <0 165 4>;
634 gpio2: gpio@ff70a000 {
635 #address-cells = <1>;
637 compatible = "snps,dw-apb-gpio";
638 reg = <0xff70a000 0x1000>;
639 clocks = <&l4_mp_clk>;
642 portc: gpio-controller@0 {
643 compatible = "snps,dw-apb-gpio-port";
646 snps,nr-gpios = <27>;
648 interrupt-controller;
649 #interrupt-cells = <2>;
650 interrupts = <0 166 4>;
655 #address-cells = <1>;
657 compatible = "snps,designware-i2c";
658 reg = <0xffc04000 0x1000>;
659 resets = <&rst I2C0_RESET>;
660 clocks = <&l4_sp_clk>;
661 interrupts = <0 158 0x4>;
666 #address-cells = <1>;
668 compatible = "snps,designware-i2c";
669 reg = <0xffc05000 0x1000>;
670 resets = <&rst I2C1_RESET>;
671 clocks = <&l4_sp_clk>;
672 interrupts = <0 159 0x4>;
677 #address-cells = <1>;
679 compatible = "snps,designware-i2c";
680 reg = <0xffc06000 0x1000>;
681 resets = <&rst I2C2_RESET>;
682 clocks = <&l4_sp_clk>;
683 interrupts = <0 160 0x4>;
688 #address-cells = <1>;
690 compatible = "snps,designware-i2c";
691 reg = <0xffc07000 0x1000>;
692 resets = <&rst I2C3_RESET>;
693 clocks = <&l4_sp_clk>;
694 interrupts = <0 161 0x4>;
699 compatible = "altr,socfpga-ecc-manager";
700 #address-cells = <1>;
705 compatible = "altr,socfpga-l2-ecc";
706 reg = <0xffd08140 0x4>;
707 interrupts = <0 36 1>, <0 37 1>;
711 compatible = "altr,socfpga-ocram-ecc";
712 reg = <0xffd08144 0x4>;
714 interrupts = <0 178 1>, <0 179 1>;
718 L2: l2-cache@fffef000 {
719 compatible = "arm,pl310-cache";
720 reg = <0xfffef000 0x1000>;
721 interrupts = <0 38 0x04>;
724 arm,tag-latency = <1 1 1>;
725 arm,data-latency = <2 1 1>;
727 prefetch-instr = <1>;
729 arm,double-linefill = <1>;
730 arm,double-linefill-incr = <0>;
731 arm,double-linefill-wrap = <1>;
732 arm,prefetch-drop = <0>;
733 arm,prefetch-offset = <7>;
737 compatible = "altr,l3regs", "syscon";
738 reg = <0xff800000 0x1000>;
741 mmc: dwmmc0@ff704000 {
742 compatible = "altr,socfpga-dw-mshc";
743 reg = <0xff704000 0x1000>;
744 interrupts = <0 139 4>;
745 fifo-depth = <0x400>;
746 #address-cells = <1>;
748 clocks = <&l4_mp_clk>, <&sdmmc_clk_divided>;
749 clock-names = "biu", "ciu";
753 nand0: nand@ff900000 {
754 #address-cells = <0x1>;
756 compatible = "altr,socfpga-denali-nand";
757 reg = <0xff900000 0x100000>,
758 <0xffb80000 0x10000>;
759 reg-names = "nand_data", "denali_reg";
760 interrupts = <0x0 0x90 0x4>;
761 dma-mask = <0xffffffff>;
762 clocks = <&nand_clk>, <&nand_x_clk>, <&nand_ecc_clk>;
763 clock-names = "nand", "nand_x", "ecc";
767 ocram: sram@ffff0000 {
768 compatible = "mmio-sram";
769 reg = <0xffff0000 0x10000>;
773 compatible = "cdns,qspi-nor";
774 #address-cells = <1>;
776 reg = <0xff705000 0x1000>,
778 interrupts = <0 151 4>;
779 cdns,fifo-depth = <128>;
780 cdns,fifo-width = <4>;
781 cdns,trigger-address = <0x00000000>;
782 clocks = <&qspi_clk>;
786 rst: rstmgr@ffd05000 {
788 compatible = "altr,rst-mgr";
789 reg = <0xffd05000 0x1000>;
790 altr,modrst-offset = <0x10>;
793 scu: snoop-control-unit@fffec000 {
794 compatible = "arm,cortex-a9-scu";
795 reg = <0xfffec000 0x100>;
799 compatible = "altr,sdr-ctl", "syscon";
800 reg = <0xffc25000 0x1000>;
804 compatible = "altr,sdram-edac";
805 altr,sdr-syscon = <&sdr>;
806 interrupts = <0 39 4>;
810 compatible = "snps,dw-apb-ssi";
811 #address-cells = <1>;
813 reg = <0xfff00000 0x1000>;
814 interrupts = <0 154 4>;
816 clocks = <&spi_m_clk>;
821 compatible = "snps,dw-apb-ssi";
822 #address-cells = <1>;
824 reg = <0xfff01000 0x1000>;
825 interrupts = <0 155 4>;
827 clocks = <&spi_m_clk>;
831 sysmgr: sysmgr@ffd08000 {
832 compatible = "altr,sys-mgr", "syscon";
833 reg = <0xffd08000 0x4000>;
838 compatible = "arm,cortex-a9-twd-timer";
839 reg = <0xfffec600 0x100>;
840 interrupts = <1 13 0xf01>;
841 clocks = <&mpu_periph_clk>;
844 timer0: timer0@ffc08000 {
845 compatible = "snps,dw-apb-timer";
846 interrupts = <0 167 4>;
847 reg = <0xffc08000 0x1000>;
848 clocks = <&l4_sp_clk>;
849 clock-names = "timer";
850 resets = <&rst SPTIMER0_RESET>;
851 reset-names = "timer";
854 timer1: timer1@ffc09000 {
855 compatible = "snps,dw-apb-timer";
856 interrupts = <0 168 4>;
857 reg = <0xffc09000 0x1000>;
858 clocks = <&l4_sp_clk>;
859 clock-names = "timer";
860 resets = <&rst SPTIMER1_RESET>;
861 reset-names = "timer";
864 timer2: timer2@ffd00000 {
865 compatible = "snps,dw-apb-timer";
866 interrupts = <0 169 4>;
867 reg = <0xffd00000 0x1000>;
869 clock-names = "timer";
870 resets = <&rst OSC1TIMER0_RESET>;
871 reset-names = "timer";
874 timer3: timer3@ffd01000 {
875 compatible = "snps,dw-apb-timer";
876 interrupts = <0 170 4>;
877 reg = <0xffd01000 0x1000>;
879 clock-names = "timer";
880 resets = <&rst OSC1TIMER1_RESET>;
881 reset-names = "timer";
884 uart0: serial0@ffc02000 {
885 compatible = "snps,dw-apb-uart";
886 reg = <0xffc02000 0x1000>;
887 interrupts = <0 162 4>;
890 clocks = <&l4_sp_clk>;
893 dma-names = "tx", "rx";
896 uart1: serial1@ffc03000 {
897 compatible = "snps,dw-apb-uart";
898 reg = <0xffc03000 0x1000>;
899 interrupts = <0 163 4>;
902 clocks = <&l4_sp_clk>;
905 dma-names = "tx", "rx";
910 compatible = "usb-nop-xceiv";
915 compatible = "snps,dwc2";
916 reg = <0xffb00000 0xffff>;
917 interrupts = <0 125 4>;
918 clocks = <&usb_mp_clk>;
920 resets = <&rst USB0_RESET>;
921 reset-names = "dwc2";
923 phy-names = "usb2-phy";
928 compatible = "snps,dwc2";
929 reg = <0xffb40000 0xffff>;
930 interrupts = <0 128 4>;
931 clocks = <&usb_mp_clk>;
933 resets = <&rst USB1_RESET>;
934 reset-names = "dwc2";
936 phy-names = "usb2-phy";
940 watchdog0: watchdog@ffd02000 {
941 compatible = "snps,dw-wdt";
942 reg = <0xffd02000 0x1000>;
943 interrupts = <0 171 4>;
948 watchdog1: watchdog@ffd03000 {
949 compatible = "snps,dw-wdt";
950 reg = <0xffd03000 0x1000>;
951 interrupts = <0 172 4>;