2 * Copyright Altera Corporation (C) 2014. All rights reserved.
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * You should have received a copy of the GNU General Public License along with
14 * this program. If not, see <http://www.gnu.org/licenses/>.
17 #include <dt-bindings/interrupt-controller/arm-gic.h>
18 #include <dt-bindings/reset/altr,rst-mgr-a10.h>
27 enable-method = "altr,socfpga-a10-smp";
30 compatible = "arm,cortex-a9";
33 next-level-cache = <&L2>;
36 compatible = "arm,cortex-a9";
39 next-level-cache = <&L2>;
44 compatible = "arm,cortex-a9-gic";
45 #interrupt-cells = <3>;
47 reg = <0xffffd000 0x1000>,
54 compatible = "simple-bus";
56 interrupt-parent = <&intc>;
60 compatible = "simple-bus";
66 compatible = "arm,pl330", "arm,primecell";
67 reg = <0xffda1000 0x1000>;
68 interrupts = <0 83 IRQ_TYPE_LEVEL_HIGH>,
69 <0 84 IRQ_TYPE_LEVEL_HIGH>,
70 <0 85 IRQ_TYPE_LEVEL_HIGH>,
71 <0 86 IRQ_TYPE_LEVEL_HIGH>,
72 <0 87 IRQ_TYPE_LEVEL_HIGH>,
73 <0 88 IRQ_TYPE_LEVEL_HIGH>,
74 <0 89 IRQ_TYPE_LEVEL_HIGH>,
75 <0 90 IRQ_TYPE_LEVEL_HIGH>,
76 <0 91 IRQ_TYPE_LEVEL_HIGH>;
80 clocks = <&l4_main_clk>;
81 clock-names = "apb_pclk";
86 #address-cells = <0x1>;
89 compatible = "fpga-region";
90 fpga-mgr = <&fpga_mgr>;
94 compatible = "altr,clk-mgr";
95 reg = <0xffd04000 0x1000>;
101 cb_intosc_hs_div2_clk: cb_intosc_hs_div2_clk {
103 compatible = "fixed-clock";
106 cb_intosc_ls_clk: cb_intosc_ls_clk {
108 compatible = "fixed-clock";
111 f2s_free_clk: f2s_free_clk {
113 compatible = "fixed-clock";
118 compatible = "fixed-clock";
121 main_pll: main_pll@40 {
122 #address-cells = <1>;
125 compatible = "altr,socfpga-a10-pll-clock";
126 clocks = <&osc1>, <&cb_intosc_ls_clk>,
130 main_mpu_base_clk: main_mpu_base_clk {
132 compatible = "altr,socfpga-a10-perip-clk";
133 clocks = <&main_pll>;
134 div-reg = <0x140 0 11>;
137 main_noc_base_clk: main_noc_base_clk {
139 compatible = "altr,socfpga-a10-perip-clk";
140 clocks = <&main_pll>;
141 div-reg = <0x144 0 11>;
144 main_emaca_clk: main_emaca_clk@68 {
146 compatible = "altr,socfpga-a10-perip-clk";
147 clocks = <&main_pll>;
151 main_emacb_clk: main_emacb_clk@6c {
153 compatible = "altr,socfpga-a10-perip-clk";
154 clocks = <&main_pll>;
158 main_emac_ptp_clk: main_emac_ptp_clk@70 {
160 compatible = "altr,socfpga-a10-perip-clk";
161 clocks = <&main_pll>;
165 main_gpio_db_clk: main_gpio_db_clk@74 {
167 compatible = "altr,socfpga-a10-perip-clk";
168 clocks = <&main_pll>;
172 main_sdmmc_clk: main_sdmmc_clk@78 {
174 compatible = "altr,socfpga-a10-perip-clk"
176 clocks = <&main_pll>;
180 main_s2f_usr0_clk: main_s2f_usr0_clk@7c {
182 compatible = "altr,socfpga-a10-perip-clk";
183 clocks = <&main_pll>;
187 main_s2f_usr1_clk: main_s2f_usr1_clk@80 {
189 compatible = "altr,socfpga-a10-perip-clk";
190 clocks = <&main_pll>;
194 main_hmc_pll_ref_clk: main_hmc_pll_ref_clk@84 {
196 compatible = "altr,socfpga-a10-perip-clk";
197 clocks = <&main_pll>;
201 main_periph_ref_clk: main_periph_ref_clk@9c {
203 compatible = "altr,socfpga-a10-perip-clk";
204 clocks = <&main_pll>;
209 periph_pll: periph_pll@c0 {
210 #address-cells = <1>;
213 compatible = "altr,socfpga-a10-pll-clock";
214 clocks = <&osc1>, <&cb_intosc_ls_clk>,
215 <&f2s_free_clk>, <&main_periph_ref_clk>;
218 peri_mpu_base_clk: peri_mpu_base_clk {
220 compatible = "altr,socfpga-a10-perip-clk";
221 clocks = <&periph_pll>;
222 div-reg = <0x140 16 11>;
225 peri_noc_base_clk: peri_noc_base_clk {
227 compatible = "altr,socfpga-a10-perip-clk";
228 clocks = <&periph_pll>;
229 div-reg = <0x144 16 11>;
232 peri_emaca_clk: peri_emaca_clk@e8 {
234 compatible = "altr,socfpga-a10-perip-clk";
235 clocks = <&periph_pll>;
239 peri_emacb_clk: peri_emacb_clk@ec {
241 compatible = "altr,socfpga-a10-perip-clk";
242 clocks = <&periph_pll>;
246 peri_emac_ptp_clk: peri_emac_ptp_clk@f0 {
248 compatible = "altr,socfpga-a10-perip-clk";
249 clocks = <&periph_pll>;
253 peri_gpio_db_clk: peri_gpio_db_clk@f4 {
255 compatible = "altr,socfpga-a10-perip-clk";
256 clocks = <&periph_pll>;
260 peri_sdmmc_clk: peri_sdmmc_clk@f8 {
262 compatible = "altr,socfpga-a10-perip-clk";
263 clocks = <&periph_pll>;
267 peri_s2f_usr0_clk: peri_s2f_usr0_clk@fc {
269 compatible = "altr,socfpga-a10-perip-clk";
270 clocks = <&periph_pll>;
274 peri_s2f_usr1_clk: peri_s2f_usr1_clk@100 {
276 compatible = "altr,socfpga-a10-perip-clk";
277 clocks = <&periph_pll>;
281 peri_hmc_pll_ref_clk: peri_hmc_pll_ref_clk@104 {
283 compatible = "altr,socfpga-a10-perip-clk";
284 clocks = <&periph_pll>;
289 mpu_free_clk: mpu_free_clk@60 {
291 compatible = "altr,socfpga-a10-perip-clk";
292 clocks = <&main_mpu_base_clk>, <&peri_mpu_base_clk>,
293 <&osc1>, <&cb_intosc_hs_div2_clk>,
298 noc_free_clk: noc_free_clk@64 {
300 compatible = "altr,socfpga-a10-perip-clk";
301 clocks = <&main_noc_base_clk>, <&peri_noc_base_clk>,
302 <&osc1>, <&cb_intosc_hs_div2_clk>,
307 s2f_user1_free_clk: s2f_user1_free_clk@104 {
309 compatible = "altr,socfpga-a10-perip-clk";
310 clocks = <&main_s2f_usr1_clk>, <&peri_s2f_usr1_clk>,
311 <&osc1>, <&cb_intosc_hs_div2_clk>,
316 sdmmc_free_clk: sdmmc_free_clk@f8 {
318 compatible = "altr,socfpga-a10-perip-clk";
319 clocks = <&main_sdmmc_clk>, <&peri_sdmmc_clk>,
320 <&osc1>, <&cb_intosc_hs_div2_clk>,
326 l4_sys_free_clk: l4_sys_free_clk {
328 compatible = "altr,socfpga-a10-perip-clk";
329 clocks = <&noc_free_clk>;
333 l4_main_clk: l4_main_clk {
335 compatible = "altr,socfpga-a10-gate-clk";
336 clocks = <&noc_free_clk>;
337 div-reg = <0xA8 0 2>;
341 l4_mp_clk: l4_mp_clk {
343 compatible = "altr,socfpga-a10-gate-clk";
344 clocks = <&noc_free_clk>;
345 div-reg = <0xA8 8 2>;
349 l4_sp_clk: l4_sp_clk {
351 compatible = "altr,socfpga-a10-gate-clk";
352 clocks = <&noc_free_clk>;
353 div-reg = <0xA8 16 2>;
357 mpu_periph_clk: mpu_periph_clk {
359 compatible = "altr,socfpga-a10-gate-clk";
360 clocks = <&mpu_free_clk>;
365 sdmmc_clk: sdmmc_clk {
367 compatible = "altr,socfpga-a10-gate-clk";
368 clocks = <&sdmmc_free_clk>;
375 compatible = "altr,socfpga-a10-gate-clk";
376 clocks = <&l4_main_clk>;
377 clk-gate = <0xC8 11>;
380 nand_x_clk: nand_x_clk {
382 compatible = "altr,socfpga-a10-gate-clk";
383 clocks = <&l4_mp_clk>;
384 clk-gate = <0xC8 10>;
387 nand_ecc_clk: nand_ecc_clk {
389 compatible = "altr,socfpga-a10-gate-clk";
390 clocks = <&nand_x_clk>;
391 clk-gate = <0xC8 10>;
396 compatible = "altr,socfpga-a10-gate-clk";
397 clocks = <&nand_x_clk>;
399 clk-gate = <0xC8 10>;
402 spi_m_clk: spi_m_clk {
404 compatible = "altr,socfpga-a10-gate-clk";
405 clocks = <&l4_main_clk>;
411 compatible = "altr,socfpga-a10-gate-clk";
412 clocks = <&l4_mp_clk>;
416 s2f_usr1_clk: s2f_usr1_clk {
418 compatible = "altr,socfpga-a10-gate-clk";
419 clocks = <&peri_s2f_usr1_clk>;
425 socfpga_axi_setup: stmmac-axi-config {
426 snps,wr_osr_lmt = <0xf>;
427 snps,rd_osr_lmt = <0xf>;
428 snps,blen = <0 0 0 0 16 0 0>;
431 gmac0: ethernet@ff800000 {
432 compatible = "altr,socfpga-stmmac", "snps,dwmac-3.72a", "snps,dwmac";
433 altr,sysmgr-syscon = <&sysmgr 0x44 0>;
434 reg = <0xff800000 0x2000>;
435 interrupts = <0 92 IRQ_TYPE_LEVEL_HIGH>;
436 interrupt-names = "macirq";
437 /* Filled in by bootloader */
438 mac-address = [00 00 00 00 00 00];
439 snps,multicast-filter-bins = <256>;
440 snps,perfect-filter-entries = <128>;
441 tx-fifo-depth = <4096>;
442 rx-fifo-depth = <16384>;
443 clocks = <&l4_mp_clk>;
444 clock-names = "stmmaceth";
445 resets = <&rst EMAC0_RESET>;
446 reset-names = "stmmaceth";
447 snps,axi-config = <&socfpga_axi_setup>;
451 gmac1: ethernet@ff802000 {
452 compatible = "altr,socfpga-stmmac", "snps,dwmac-3.72a", "snps,dwmac";
453 altr,sysmgr-syscon = <&sysmgr 0x48 0>;
454 reg = <0xff802000 0x2000>;
455 interrupts = <0 93 IRQ_TYPE_LEVEL_HIGH>;
456 interrupt-names = "macirq";
457 /* Filled in by bootloader */
458 mac-address = [00 00 00 00 00 00];
459 snps,multicast-filter-bins = <256>;
460 snps,perfect-filter-entries = <128>;
461 tx-fifo-depth = <4096>;
462 rx-fifo-depth = <16384>;
463 clocks = <&l4_mp_clk>;
464 clock-names = "stmmaceth";
465 resets = <&rst EMAC1_RESET>;
466 reset-names = "stmmaceth";
467 snps,axi-config = <&socfpga_axi_setup>;
471 gmac2: ethernet@ff804000 {
472 compatible = "altr,socfpga-stmmac", "snps,dwmac-3.72a", "snps,dwmac";
473 altr,sysmgr-syscon = <&sysmgr 0x4C 0>;
474 reg = <0xff804000 0x2000>;
475 interrupts = <0 94 IRQ_TYPE_LEVEL_HIGH>;
476 interrupt-names = "macirq";
477 /* Filled in by bootloader */
478 mac-address = [00 00 00 00 00 00];
479 snps,multicast-filter-bins = <256>;
480 snps,perfect-filter-entries = <128>;
481 tx-fifo-depth = <4096>;
482 rx-fifo-depth = <16384>;
483 clocks = <&l4_mp_clk>;
484 clock-names = "stmmaceth";
485 snps,axi-config = <&socfpga_axi_setup>;
489 gpio0: gpio@ffc02900 {
490 #address-cells = <1>;
492 compatible = "snps,dw-apb-gpio";
493 reg = <0xffc02900 0x100>;
496 porta: gpio-controller@0 {
497 compatible = "snps,dw-apb-gpio-port";
500 snps,nr-gpios = <29>;
502 interrupt-controller;
503 #interrupt-cells = <2>;
504 interrupts = <0 112 IRQ_TYPE_LEVEL_HIGH>;
508 gpio1: gpio@ffc02a00 {
509 #address-cells = <1>;
511 compatible = "snps,dw-apb-gpio";
512 reg = <0xffc02a00 0x100>;
515 portb: gpio-controller@0 {
516 compatible = "snps,dw-apb-gpio-port";
519 snps,nr-gpios = <29>;
521 interrupt-controller;
522 #interrupt-cells = <2>;
523 interrupts = <0 113 IRQ_TYPE_LEVEL_HIGH>;
527 gpio2: gpio@ffc02b00 {
528 #address-cells = <1>;
530 compatible = "snps,dw-apb-gpio";
531 reg = <0xffc02b00 0x100>;
534 portc: gpio-controller@0 {
535 compatible = "snps,dw-apb-gpio-port";
538 snps,nr-gpios = <27>;
540 interrupt-controller;
541 #interrupt-cells = <2>;
542 interrupts = <0 114 IRQ_TYPE_LEVEL_HIGH>;
546 fpga_mgr: fpga-mgr@ffd03000 {
547 compatible = "altr,socfpga-a10-fpga-mgr";
548 reg = <0xffd03000 0x100
550 clocks = <&l4_mp_clk>;
551 resets = <&rst FPGAMGR_RESET>;
552 reset-names = "fpgamgr";
556 #address-cells = <1>;
558 compatible = "snps,designware-i2c";
559 reg = <0xffc02200 0x100>;
560 interrupts = <0 105 IRQ_TYPE_LEVEL_HIGH>;
561 clocks = <&l4_sp_clk>;
566 #address-cells = <1>;
568 compatible = "snps,designware-i2c";
569 reg = <0xffc02300 0x100>;
570 interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>;
571 clocks = <&l4_sp_clk>;
576 #address-cells = <1>;
578 compatible = "snps,designware-i2c";
579 reg = <0xffc02400 0x100>;
580 interrupts = <0 107 IRQ_TYPE_LEVEL_HIGH>;
581 clocks = <&l4_sp_clk>;
586 #address-cells = <1>;
588 compatible = "snps,designware-i2c";
589 reg = <0xffc02500 0x100>;
590 interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>;
591 clocks = <&l4_sp_clk>;
596 #address-cells = <1>;
598 compatible = "snps,designware-i2c";
599 reg = <0xffc02600 0x100>;
600 interrupts = <0 109 IRQ_TYPE_LEVEL_HIGH>;
601 clocks = <&l4_sp_clk>;
606 compatible = "snps,dw-apb-ssi";
607 #address-cells = <1>;
609 reg = <0xffda4000 0x100>;
610 interrupts = <0 101 4>;
613 clocks = <&spi_m_clk>;
618 compatible = "snps,dw-apb-ssi";
619 #address-cells = <1>;
621 reg = <0xffda5000 0x100>;
622 interrupts = <0 102 4>;
625 tx-dma-channel = <&pdma 16>;
626 rx-dma-channel = <&pdma 17>;
627 clocks = <&spi_m_clk>;
632 compatible = "altr,sdr-ctl", "syscon";
633 reg = <0xffcfb100 0x80>;
636 L2: l2-cache@fffff000 {
637 compatible = "arm,pl310-cache";
638 reg = <0xfffff000 0x1000>;
639 interrupts = <0 18 IRQ_TYPE_LEVEL_HIGH>;
643 prefetch-instr = <1>;
647 mmc: dwmmc0@ff808000 {
648 #address-cells = <1>;
650 compatible = "altr,socfpga-dw-mshc";
651 reg = <0xff808000 0x1000>;
652 interrupts = <0 98 IRQ_TYPE_LEVEL_HIGH>;
653 fifo-depth = <0x400>;
654 clocks = <&l4_mp_clk>, <&sdmmc_clk>;
655 clock-names = "biu", "ciu";
659 nand: nand@ffb90000 {
660 #address-cells = <1>;
662 compatible = "altr,socfpga-denali-nand";
663 reg = <0xffb90000 0x72000>,
664 <0xffb80000 0x10000>;
665 reg-names = "nand_data", "denali_reg";
666 interrupts = <0 99 4>;
667 dma-mask = <0xffffffff>;
668 clocks = <&nand_clk>, <&nand_x_clk>, <&nand_ecc_clk>;
669 clock-names = "nand", "nand_x", "ecc";
673 ocram: sram@ffe00000 {
674 compatible = "mmio-sram";
675 reg = <0xffe00000 0x40000>;
679 compatible = "altr,socfpga-a10-ecc-manager";
680 altr,sysmgr-syscon = <&sysmgr>;
681 #address-cells = <1>;
683 interrupts = <0 2 IRQ_TYPE_LEVEL_HIGH>,
684 <0 0 IRQ_TYPE_LEVEL_HIGH>;
685 interrupt-controller;
686 #interrupt-cells = <2>;
690 compatible = "altr,sdram-edac-a10";
691 altr,sdr-syscon = <&sdr>;
692 interrupts = <17 IRQ_TYPE_LEVEL_HIGH>,
693 <49 IRQ_TYPE_LEVEL_HIGH>;
697 compatible = "altr,socfpga-a10-l2-ecc";
698 reg = <0xffd06010 0x4>;
699 interrupts = <0 IRQ_TYPE_LEVEL_HIGH>,
700 <32 IRQ_TYPE_LEVEL_HIGH>;
704 compatible = "altr,socfpga-a10-ocram-ecc";
705 reg = <0xff8c3000 0x400>;
706 interrupts = <1 IRQ_TYPE_LEVEL_HIGH>,
707 <33 IRQ_TYPE_LEVEL_HIGH>;
710 emac0-rx-ecc@ff8c0800 {
711 compatible = "altr,socfpga-eth-mac-ecc";
712 reg = <0xff8c0800 0x400>;
713 altr,ecc-parent = <&gmac0>;
714 interrupts = <4 IRQ_TYPE_LEVEL_HIGH>,
715 <36 IRQ_TYPE_LEVEL_HIGH>;
718 emac0-tx-ecc@ff8c0c00 {
719 compatible = "altr,socfpga-eth-mac-ecc";
720 reg = <0xff8c0c00 0x400>;
721 altr,ecc-parent = <&gmac0>;
722 interrupts = <5 IRQ_TYPE_LEVEL_HIGH>,
723 <37 IRQ_TYPE_LEVEL_HIGH>;
727 compatible = "altr,socfpga-dma-ecc";
728 reg = <0xff8c8000 0x400>;
729 altr,ecc-parent = <&pdma>;
730 interrupts = <10 IRQ_TYPE_LEVEL_HIGH>,
731 <42 IRQ_TYPE_LEVEL_HIGH>;
735 compatible = "altr,socfpga-usb-ecc";
736 reg = <0xff8c8800 0x400>;
737 altr,ecc-parent = <&usb0>;
738 interrupts = <2 IRQ_TYPE_LEVEL_HIGH>,
739 <34 IRQ_TYPE_LEVEL_HIGH>;
744 compatible = "cdns,qspi-nor";
745 #address-cells = <1>;
747 reg = <0xff809000 0x100>,
748 <0xffa00000 0x100000>;
749 interrupts = <0 100 IRQ_TYPE_LEVEL_HIGH>;
750 cdns,fifo-depth = <128>;
751 cdns,fifo-width = <4>;
752 cdns,trigger-address = <0x00000000>;
753 clocks = <&qspi_clk>;
757 rst: rstmgr@ffd05000 {
759 compatible = "altr,rst-mgr";
760 reg = <0xffd05000 0x100>;
761 altr,modrst-offset = <0x20>;
764 scu: snoop-control-unit@ffffc000 {
765 compatible = "arm,cortex-a9-scu";
766 reg = <0xffffc000 0x100>;
769 sysmgr: sysmgr@ffd06000 {
770 compatible = "altr,sys-mgr", "syscon";
771 reg = <0xffd06000 0x300>;
772 cpu1-start-addr = <0xffd06230>;
777 compatible = "arm,cortex-a9-twd-timer";
778 reg = <0xffffc600 0x100>;
779 interrupts = <1 13 0xf01>;
780 clocks = <&mpu_periph_clk>;
783 timer0: timer0@ffc02700 {
784 compatible = "snps,dw-apb-timer";
785 interrupts = <0 115 IRQ_TYPE_LEVEL_HIGH>;
786 reg = <0xffc02700 0x100>;
787 clocks = <&l4_sp_clk>;
788 clock-names = "timer";
789 resets = <&rst SPTIMER0_RESET>;
790 reset-names = "timer";
793 timer1: timer1@ffc02800 {
794 compatible = "snps,dw-apb-timer";
795 interrupts = <0 116 IRQ_TYPE_LEVEL_HIGH>;
796 reg = <0xffc02800 0x100>;
797 clocks = <&l4_sp_clk>;
798 clock-names = "timer";
799 resets = <&rst SPTIMER1_RESET>;
800 reset-names = "timer";
803 timer2: timer2@ffd00000 {
804 compatible = "snps,dw-apb-timer";
805 interrupts = <0 117 IRQ_TYPE_LEVEL_HIGH>;
806 reg = <0xffd00000 0x100>;
807 clocks = <&l4_sys_free_clk>;
808 clock-names = "timer";
809 resets = <&rst L4SYSTIMER0_RESET>;
810 reset-names = "timer";
813 timer3: timer3@ffd00100 {
814 compatible = "snps,dw-apb-timer";
815 interrupts = <0 118 IRQ_TYPE_LEVEL_HIGH>;
816 reg = <0xffd01000 0x100>;
817 clocks = <&l4_sys_free_clk>;
818 clock-names = "timer";
819 resets = <&rst L4SYSTIMER1_RESET>;
820 reset-names = "timer";
823 uart0: serial0@ffc02000 {
824 compatible = "snps,dw-apb-uart";
825 reg = <0xffc02000 0x100>;
826 interrupts = <0 110 IRQ_TYPE_LEVEL_HIGH>;
829 clocks = <&l4_sp_clk>;
833 uart1: serial1@ffc02100 {
834 compatible = "snps,dw-apb-uart";
835 reg = <0xffc02100 0x100>;
836 interrupts = <0 111 IRQ_TYPE_LEVEL_HIGH>;
839 clocks = <&l4_sp_clk>;
845 compatible = "usb-nop-xceiv";
850 compatible = "snps,dwc2";
851 reg = <0xffb00000 0xffff>;
852 interrupts = <0 95 IRQ_TYPE_LEVEL_HIGH>;
855 resets = <&rst USB0_RESET>;
856 reset-names = "dwc2";
858 phy-names = "usb2-phy";
863 compatible = "snps,dwc2";
864 reg = <0xffb40000 0xffff>;
865 interrupts = <0 96 IRQ_TYPE_LEVEL_HIGH>;
868 resets = <&rst USB1_RESET>;
869 reset-names = "dwc2";
871 phy-names = "usb2-phy";
875 watchdog0: watchdog@ffd00200 {
876 compatible = "snps,dw-wdt";
877 reg = <0xffd00200 0x100>;
878 interrupts = <0 119 IRQ_TYPE_LEVEL_HIGH>;
879 clocks = <&l4_sys_free_clk>;
883 watchdog1: watchdog@ffd00300 {
884 compatible = "snps,dw-wdt";
885 reg = <0xffd00300 0x100>;
886 interrupts = <0 120 IRQ_TYPE_LEVEL_HIGH>;
887 clocks = <&l4_sys_free_clk>;