sys/gnu/dts/arm/socfpga_arria10.dtsi

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright Altera Corporation (C) 2014. All rights reserved.
   4  */
   5
   6 #include <dt-bindings/interrupt-controller/arm-gic.h>
   7 #include <dt-bindings/reset/altr,rst-mgr-a10.h>
   8
   9 / {
  10         #address-cells = <1>;
  11         #size-cells = <1>;
  12
  13         cpus {
  14                 #address-cells = <1>;
  15                 #size-cells = <0>;
  16                 enable-method = "altr,socfpga-a10-smp";
  17
  18                 cpu@0 {
  19                         compatible = "arm,cortex-a9";
  20                         device_type = "cpu";
  21                         reg = <0>;
  22                         next-level-cache = <&L2>;
  23                 };
  24                 cpu@1 {
  25                         compatible = "arm,cortex-a9";
  26                         device_type = "cpu";
  27                         reg = <1>;
  28                         next-level-cache = <&L2>;
  29                 };
  30         };
  31
  32         intc: intc@ffffd000 {
  33                 compatible = "arm,cortex-a9-gic";
  34                 #interrupt-cells = <3>;
  35                 interrupt-controller;
  36                 reg = <0xffffd000 0x1000>,
  37                       <0xffffc100 0x100>;
  38         };
  39
  40         soc {
  41                 #address-cells = <1>;
  42                 #size-cells = <1>;
  43                 compatible = "simple-bus";
  44                 device_type = "soc";
  45                 interrupt-parent = <&intc>;
  46                 ranges;
  47
  48                 amba {
  49                         compatible = "simple-bus";
  50                         #address-cells = <1>;
  51                         #size-cells = <1>;
  52                         ranges;
  53
  54                         pdma: pdma@ffda1000 {
  55                                 compatible = "arm,pl330", "arm,primecell";
  56                                 reg = <0xffda1000 0x1000>;
  57                                 interrupts = <0 83 IRQ_TYPE_LEVEL_HIGH>,
  58                                              <0 84 IRQ_TYPE_LEVEL_HIGH>,
  59                                              <0 85 IRQ_TYPE_LEVEL_HIGH>,
  60                                              <0 86 IRQ_TYPE_LEVEL_HIGH>,
  61                                              <0 87 IRQ_TYPE_LEVEL_HIGH>,
  62                                              <0 88 IRQ_TYPE_LEVEL_HIGH>,
  63                                              <0 89 IRQ_TYPE_LEVEL_HIGH>,
  64                                              <0 90 IRQ_TYPE_LEVEL_HIGH>,
  65                                              <0 91 IRQ_TYPE_LEVEL_HIGH>;
  66                                 #dma-cells = <1>;
  67                                 #dma-channels = <8>;
  68                                 #dma-requests = <32>;
  69                                 clocks = <&l4_main_clk>;
  70                                 clock-names = "apb_pclk";
  71                         };
  72                 };
  73
  74                 base_fpga_region {
  75                         #address-cells = <0x1>;
  76                         #size-cells = <0x1>;
  77
  78                         compatible = "fpga-region";
  79                         fpga-mgr = <&fpga_mgr>;
  80                 };
  81
  82                 clkmgr@ffd04000 {
  83                                 compatible = "altr,clk-mgr";
  84                                 reg = <0xffd04000 0x1000>;
  85
  86                                 clocks {
  87                                         #address-cells = <1>;
  88                                         #size-cells = <0>;
  89
  90                                         cb_intosc_hs_div2_clk: cb_intosc_hs_div2_clk {
  91                                                 #clock-cells = <0>;
  92                                                 compatible = "fixed-clock";
  93                                         };
  94
  95                                         cb_intosc_ls_clk: cb_intosc_ls_clk {
  96                                                 #clock-cells = <0>;
  97                                                 compatible = "fixed-clock";
  98                                         };
  99
 100                                         f2s_free_clk: f2s_free_clk {
 101                                                 #clock-cells = <0>;
 102                                                 compatible = "fixed-clock";
 103                                         };
 104
 105                                         osc1: osc1 {
 106                                                 #clock-cells = <0>;
 107                                                 compatible = "fixed-clock";
 108                                         };
 109
 110                                         main_pll: main_pll@40 {
 111                                                 #address-cells = <1>;
 112                                                 #size-cells = <0>;
 113                                                 #clock-cells = <0>;
 114                                                 compatible = "altr,socfpga-a10-pll-clock";
 115                                                 clocks = <&osc1>, <&cb_intosc_ls_clk>,
 116                                                          <&f2s_free_clk>;
 117                                                 reg = <0x40>;
 118
 119                                                 main_mpu_base_clk: main_mpu_base_clk {
 120                                                         #clock-cells = <0>;
 121                                                         compatible = "altr,socfpga-a10-perip-clk";
 122                                                         clocks = <&main_pll>;
 123                                                         div-reg = <0x140 0 11>;
 124                                                 };
 125
 126                                                 main_noc_base_clk: main_noc_base_clk {
 127                                                         #clock-cells = <0>;
 128                                                         compatible = "altr,socfpga-a10-perip-clk";
 129                                                         clocks = <&main_pll>;
 130                                                         div-reg = <0x144 0 11>;
 131                                                 };
 132
 133                                                 main_emaca_clk: main_emaca_clk@68 {
 134                                                         #clock-cells = <0>;
 135                                                         compatible = "altr,socfpga-a10-perip-clk";
 136                                                         clocks = <&main_pll>;
 137                                                         reg = <0x68>;
 138                                                 };
 139
 140                                                 main_emacb_clk: main_emacb_clk@6c {
 141                                                         #clock-cells = <0>;
 142                                                         compatible = "altr,socfpga-a10-perip-clk";
 143                                                         clocks = <&main_pll>;
 144                                                         reg = <0x6C>;
 145                                                 };
 146
 147                                                 main_emac_ptp_clk: main_emac_ptp_clk@70 {
 148                                                         #clock-cells = <0>;
 149                                                         compatible = "altr,socfpga-a10-perip-clk";
 150                                                         clocks = <&main_pll>;
 151                                                         reg = <0x70>;
 152                                                 };
 153
 154                                                 main_gpio_db_clk: main_gpio_db_clk@74 {
 155                                                         #clock-cells = <0>;
 156                                                         compatible = "altr,socfpga-a10-perip-clk";
 157                                                         clocks = <&main_pll>;
 158                                                         reg = <0x74>;
 159                                                 };
 160
 161                                                 main_sdmmc_clk: main_sdmmc_clk@78 {
 162                                                         #clock-cells = <0>;
 163                                                         compatible = "altr,socfpga-a10-perip-clk"
 164 ;
 165                                                         clocks = <&main_pll>;
 166                                                         reg = <0x78>;
 167                                                 };
 168
 169                                                 main_s2f_usr0_clk: main_s2f_usr0_clk@7c {
 170                                                         #clock-cells = <0>;
 171                                                         compatible = "altr,socfpga-a10-perip-clk";
 172                                                         clocks = <&main_pll>;
 173                                                         reg = <0x7C>;
 174                                                 };
 175
 176                                                 main_s2f_usr1_clk: main_s2f_usr1_clk@80 {
 177                                                         #clock-cells = <0>;
 178                                                         compatible = "altr,socfpga-a10-perip-clk";
 179                                                         clocks = <&main_pll>;
 180                                                         reg = <0x80>;
 181                                                 };
 182
 183                                                 main_hmc_pll_ref_clk: main_hmc_pll_ref_clk@84 {
 184                                                         #clock-cells = <0>;
 185                                                         compatible = "altr,socfpga-a10-perip-clk";
 186                                                         clocks = <&main_pll>;
 187                                                         reg = <0x84>;
 188                                                 };
 189
 190                                                 main_periph_ref_clk: main_periph_ref_clk@9c {
 191                                                         #clock-cells = <0>;
 192                                                         compatible = "altr,socfpga-a10-perip-clk";
 193                                                         clocks = <&main_pll>;
 194                                                         reg = <0x9C>;
 195                                                 };
 196                                         };
 197
 198                                         periph_pll: periph_pll@c0 {
 199                                                 #address-cells = <1>;
 200                                                 #size-cells = <0>;
 201                                                 #clock-cells = <0>;
 202                                                 compatible = "altr,socfpga-a10-pll-clock";
 203                                                 clocks = <&osc1>, <&cb_intosc_ls_clk>,
 204                                                          <&f2s_free_clk>, <&main_periph_ref_clk>;
 205                                                 reg = <0xC0>;
 206
 207                                                 peri_mpu_base_clk: peri_mpu_base_clk {
 208                                                         #clock-cells = <0>;
 209                                                         compatible = "altr,socfpga-a10-perip-clk";
 210                                                         clocks = <&periph_pll>;
 211                                                         div-reg = <0x140 16 11>;
 212                                                 };
 213
 214                                                 peri_noc_base_clk: peri_noc_base_clk {
 215                                                         #clock-cells = <0>;
 216                                                         compatible = "altr,socfpga-a10-perip-clk";
 217                                                         clocks = <&periph_pll>;
 218                                                         div-reg = <0x144 16 11>;
 219                                                 };
 220
 221                                                 peri_emaca_clk: peri_emaca_clk@e8 {
 222                                                         #clock-cells = <0>;
 223                                                         compatible = "altr,socfpga-a10-perip-clk";
 224                                                         clocks = <&periph_pll>;
 225                                                         reg = <0xE8>;
 226                                                 };
 227
 228                                                 peri_emacb_clk: peri_emacb_clk@ec {
 229                                                         #clock-cells = <0>;
 230                                                         compatible = "altr,socfpga-a10-perip-clk";
 231                                                         clocks = <&periph_pll>;
 232                                                         reg = <0xEC>;
 233                                                 };
 234
 235                                                 peri_emac_ptp_clk: peri_emac_ptp_clk@f0 {
 236                                                         #clock-cells = <0>;
 237                                                         compatible = "altr,socfpga-a10-perip-clk";
 238                                                         clocks = <&periph_pll>;
 239                                                         reg = <0xF0>;
 240                                                 };
 241
 242                                                 peri_gpio_db_clk: peri_gpio_db_clk@f4 {
 243                                                         #clock-cells = <0>;
 244                                                         compatible = "altr,socfpga-a10-perip-clk";
 245                                                         clocks = <&periph_pll>;
 246                                                         reg = <0xF4>;
 247                                                 };
 248
 249                                                 peri_sdmmc_clk: peri_sdmmc_clk@f8 {
 250                                                         #clock-cells = <0>;
 251                                                         compatible = "altr,socfpga-a10-perip-clk";
 252                                                         clocks = <&periph_pll>;
 253                                                         reg = <0xF8>;
 254                                                 };
 255
 256                                                 peri_s2f_usr0_clk: peri_s2f_usr0_clk@fc {
 257                                                         #clock-cells = <0>;
 258                                                         compatible = "altr,socfpga-a10-perip-clk";
 259                                                         clocks = <&periph_pll>;
 260                                                         reg = <0xFC>;
 261                                                 };
 262
 263                                                 peri_s2f_usr1_clk: peri_s2f_usr1_clk@100 {
 264                                                         #clock-cells = <0>;
 265                                                         compatible = "altr,socfpga-a10-perip-clk";
 266                                                         clocks = <&periph_pll>;
 267                                                         reg = <0x100>;
 268                                                 };
 269
 270                                                 peri_hmc_pll_ref_clk: peri_hmc_pll_ref_clk@104 {
 271                                                         #clock-cells = <0>;
 272                                                         compatible = "altr,socfpga-a10-perip-clk";
 273                                                         clocks = <&periph_pll>;
 274                                                         reg = <0x104>;
 275                                                 };
 276                                         };
 277
 278                                         mpu_free_clk: mpu_free_clk@60 {
 279                                                 #clock-cells = <0>;
 280                                                 compatible = "altr,socfpga-a10-perip-clk";
 281                                                 clocks = <&main_mpu_base_clk>, <&peri_mpu_base_clk>,
 282                                                          <&osc1>, <&cb_intosc_hs_div2_clk>,
 283                                                          <&f2s_free_clk>;
 284                                                 reg = <0x60>;
 285                                         };
 286
 287                                         noc_free_clk: noc_free_clk@64 {
 288                                                 #clock-cells = <0>;
 289                                                 compatible = "altr,socfpga-a10-perip-clk";
 290                                                 clocks = <&main_noc_base_clk>, <&peri_noc_base_clk>,
 291                                                          <&osc1>, <&cb_intosc_hs_div2_clk>,
 292                                                          <&f2s_free_clk>;
 293                                                 reg = <0x64>;
 294                                         };
 295
 296                                         s2f_user1_free_clk: s2f_user1_free_clk@104 {
 297                                                 #clock-cells = <0>;
 298                                                 compatible = "altr,socfpga-a10-perip-clk";
 299                                                 clocks = <&main_s2f_usr1_clk>, <&peri_s2f_usr1_clk>,
 300                                                          <&osc1>, <&cb_intosc_hs_div2_clk>,
 301                                                          <&f2s_free_clk>;
 302                                                 reg = <0x104>;
 303                                         };
 304
 305                                         sdmmc_free_clk: sdmmc_free_clk@f8 {
 306                                                 #clock-cells = <0>;
 307                                                 compatible = "altr,socfpga-a10-perip-clk";
 308                                                 clocks = <&main_sdmmc_clk>, <&peri_sdmmc_clk>,
 309                                                          <&osc1>, <&cb_intosc_hs_div2_clk>,
 310                                                          <&f2s_free_clk>;
 311                                                 fixed-divider = <4>;
 312                                                 reg = <0xF8>;
 313                                         };
 314
 315                                         l4_sys_free_clk: l4_sys_free_clk {
 316                                                 #clock-cells = <0>;
 317                                                 compatible = "altr,socfpga-a10-perip-clk";
 318                                                 clocks = <&noc_free_clk>;
 319                                                 fixed-divider = <4>;
 320                                         };
 321
 322                                         l4_main_clk: l4_main_clk {
 323                                                 #clock-cells = <0>;
 324                                                 compatible = "altr,socfpga-a10-gate-clk";
 325                                                 clocks = <&noc_free_clk>;
 326                                                 div-reg = <0xA8 0 2>;
 327                                                 clk-gate = <0x48 1>;
 328                                         };
 329
 330                                         l4_mp_clk: l4_mp_clk {
 331                                                 #clock-cells = <0>;
 332                                                 compatible = "altr,socfpga-a10-gate-clk";
 333                                                 clocks = <&noc_free_clk>;
 334                                                 div-reg = <0xA8 8 2>;
 335                                                 clk-gate = <0x48 2>;
 336                                         };
 337
 338                                         l4_sp_clk: l4_sp_clk {
 339                                                 #clock-cells = <0>;
 340                                                 compatible = "altr,socfpga-a10-gate-clk";
 341                                                 clocks = <&noc_free_clk>;
 342                                                 div-reg = <0xA8 16 2>;
 343                                                 clk-gate = <0x48 3>;
 344                                         };
 345
 346                                         mpu_periph_clk: mpu_periph_clk {
 347                                                 #clock-cells = <0>;
 348                                                 compatible = "altr,socfpga-a10-gate-clk";
 349                                                 clocks = <&mpu_free_clk>;
 350                                                 fixed-divider = <4>;
 351                                                 clk-gate = <0x48 0>;
 352                                         };
 353
 354                                         sdmmc_clk: sdmmc_clk {
 355                                                 #clock-cells = <0>;
 356                                                 compatible = "altr,socfpga-a10-gate-clk";
 357                                                 clocks = <&sdmmc_free_clk>;
 358                                                 clk-gate = <0xC8 5>;
 359                                                 clk-phase = <0 135>;
 360                                         };
 361
 362                                         qspi_clk: qspi_clk {
 363                                                 #clock-cells = <0>;
 364                                                 compatible = "altr,socfpga-a10-gate-clk";
 365                                                 clocks = <&l4_main_clk>;
 366                                                 clk-gate = <0xC8 11>;
 367                                         };
 368
 369                                         nand_x_clk: nand_x_clk {
 370                                                 #clock-cells = <0>;
 371                                                 compatible = "altr,socfpga-a10-gate-clk";
 372                                                 clocks = <&l4_mp_clk>;
 373                                                 clk-gate = <0xC8 10>;
 374                                         };
 375
 376                                         nand_ecc_clk: nand_ecc_clk {
 377                                                 #clock-cells = <0>;
 378                                                 compatible = "altr,socfpga-a10-gate-clk";
 379                                                 clocks = <&nand_x_clk>;
 380                                                 clk-gate = <0xC8 10>;
 381                                         };
 382
 383                                         nand_clk: nand_clk {
 384                                                 #clock-cells = <0>;
 385                                                 compatible = "altr,socfpga-a10-gate-clk";
 386                                                 clocks = <&nand_x_clk>;
 387                                                 fixed-divider = <4>;
 388                                                 clk-gate = <0xC8 10>;
 389                                         };
 390
 391                                         spi_m_clk: spi_m_clk {
 392                                                 #clock-cells = <0>;
 393                                                 compatible = "altr,socfpga-a10-gate-clk";
 394                                                 clocks = <&l4_main_clk>;
 395                                                 clk-gate = <0xC8 9>;
 396                                         };
 397
 398                                         usb_clk: usb_clk {
 399                                                 #clock-cells = <0>;
 400                                                 compatible = "altr,socfpga-a10-gate-clk";
 401                                                 clocks = <&l4_mp_clk>;
 402                                                 clk-gate = <0xC8 8>;
 403                                         };
 404
 405                                         s2f_usr1_clk: s2f_usr1_clk {
 406                                                 #clock-cells = <0>;
 407                                                 compatible = "altr,socfpga-a10-gate-clk";
 408                                                 clocks = <&peri_s2f_usr1_clk>;
 409                                                 clk-gate = <0xC8 6>;
 410                                         };
 411                                 };
 412                 };
 413
 414                 socfpga_axi_setup: stmmac-axi-config {
 415                         snps,wr_osr_lmt = <0xf>;
 416                         snps,rd_osr_lmt = <0xf>;
 417                         snps,blen = <0 0 0 0 16 0 0>;
 418                 };
 419
 420                 gmac0: ethernet@ff800000 {
 421                         compatible = "altr,socfpga-stmmac-a10-s10", "snps,dwmac-3.72a", "snps,dwmac";
 422                         altr,sysmgr-syscon = <&sysmgr 0x44 0>;
 423                         reg = <0xff800000 0x2000>;
 424                         interrupts = <0 92 IRQ_TYPE_LEVEL_HIGH>;
 425                         interrupt-names = "macirq";
 426                         /* Filled in by bootloader */
 427                         mac-address = [00 00 00 00 00 00];
 428                         snps,multicast-filter-bins = <256>;
 429                         snps,perfect-filter-entries = <128>;
 430                         tx-fifo-depth = <4096>;
 431                         rx-fifo-depth = <16384>;
 432                         clocks = <&l4_mp_clk>;
 433                         clock-names = "stmmaceth";
 434                         resets = <&rst EMAC0_RESET>, <&rst EMAC0_OCP_RESET>;
 435                         reset-names = "stmmaceth", "stmmaceth-ocp";
 436                         snps,axi-config = <&socfpga_axi_setup>;
 437                         status = "disabled";
 438                 };
 439
 440                 gmac1: ethernet@ff802000 {
 441                         compatible = "altr,socfpga-stmmac-a10-s10", "snps,dwmac-3.72a", "snps,dwmac";
 442                         altr,sysmgr-syscon = <&sysmgr 0x48 8>;
 443                         reg = <0xff802000 0x2000>;
 444                         interrupts = <0 93 IRQ_TYPE_LEVEL_HIGH>;
 445                         interrupt-names = "macirq";
 446                         /* Filled in by bootloader */
 447                         mac-address = [00 00 00 00 00 00];
 448                         snps,multicast-filter-bins = <256>;
 449                         snps,perfect-filter-entries = <128>;
 450                         tx-fifo-depth = <4096>;
 451                         rx-fifo-depth = <16384>;
 452                         clocks = <&l4_mp_clk>;
 453                         clock-names = "stmmaceth";
 454                         resets = <&rst EMAC1_RESET>, <&rst EMAC1_OCP_RESET>;
 455                         reset-names = "stmmaceth", "stmmaceth-ocp";
 456                         snps,axi-config = <&socfpga_axi_setup>;
 457                         status = "disabled";
 458                 };
 459
 460                 gmac2: ethernet@ff804000 {
 461                         compatible = "altr,socfpga-stmmac-a10-s10", "snps,dwmac-3.72a", "snps,dwmac";
 462                         altr,sysmgr-syscon = <&sysmgr 0x4C 16>;
 463                         reg = <0xff804000 0x2000>;
 464                         interrupts = <0 94 IRQ_TYPE_LEVEL_HIGH>;
 465                         interrupt-names = "macirq";
 466                         /* Filled in by bootloader */
 467                         mac-address = [00 00 00 00 00 00];
 468                         snps,multicast-filter-bins = <256>;
 469                         snps,perfect-filter-entries = <128>;
 470                         tx-fifo-depth = <4096>;
 471                         rx-fifo-depth = <16384>;
 472                         clocks = <&l4_mp_clk>;
 473                         clock-names = "stmmaceth";
 474                         resets = <&rst EMAC2_RESET>, <&rst EMAC2_OCP_RESET>;
 475                         reset-names = "stmmaceth", "stmmaceth-ocp";
 476                         snps,axi-config = <&socfpga_axi_setup>;
 477                         status = "disabled";
 478                 };
 479
 480                 gpio0: gpio@ffc02900 {
 481                         #address-cells = <1>;
 482                         #size-cells = <0>;
 483                         compatible = "snps,dw-apb-gpio";
 484                         reg = <0xffc02900 0x100>;
 485                         resets = <&rst GPIO0_RESET>;
 486                         status = "disabled";
 487
 488                         porta: gpio-controller@0 {
 489                                 compatible = "snps,dw-apb-gpio-port";
 490                                 gpio-controller;
 491                                 #gpio-cells = <2>;
 492                                 snps,nr-gpios = <29>;
 493                                 reg = <0>;
 494                                 interrupt-controller;
 495                                 #interrupt-cells = <2>;
 496                                 interrupts = <0 112 IRQ_TYPE_LEVEL_HIGH>;
 497                         };
 498                 };
 499
 500                 gpio1: gpio@ffc02a00 {
 501                         #address-cells = <1>;
 502                         #size-cells = <0>;
 503                         compatible = "snps,dw-apb-gpio";
 504                         reg = <0xffc02a00 0x100>;
 505                         resets = <&rst GPIO1_RESET>;
 506                         status = "disabled";
 507
 508                         portb: gpio-controller@0 {
 509                                 compatible = "snps,dw-apb-gpio-port";
 510                                 gpio-controller;
 511                                 #gpio-cells = <2>;
 512                                 snps,nr-gpios = <29>;
 513                                 reg = <0>;
 514                                 interrupt-controller;
 515                                 #interrupt-cells = <2>;
 516                                 interrupts = <0 113 IRQ_TYPE_LEVEL_HIGH>;
 517                         };
 518                 };
 519
 520                 gpio2: gpio@ffc02b00 {
 521                         #address-cells = <1>;
 522                         #size-cells = <0>;
 523                         compatible = "snps,dw-apb-gpio";
 524                         reg = <0xffc02b00 0x100>;
 525                         resets = <&rst GPIO2_RESET>;
 526                         status = "disabled";
 527
 528                         portc: gpio-controller@0 {
 529                                 compatible = "snps,dw-apb-gpio-port";
 530                                 gpio-controller;
 531                                 #gpio-cells = <2>;
 532                                 snps,nr-gpios = <27>;
 533                                 reg = <0>;
 534                                 interrupt-controller;
 535                                 #interrupt-cells = <2>;
 536                                 interrupts = <0 114 IRQ_TYPE_LEVEL_HIGH>;
 537                         };
 538                 };
 539
 540                 fpga_mgr: fpga-mgr@ffd03000 {
 541                         compatible = "altr,socfpga-a10-fpga-mgr";
 542                         reg = <0xffd03000 0x100
 543                                0xffcfe400 0x20>;
 544                         clocks = <&l4_mp_clk>;
 545                         resets = <&rst FPGAMGR_RESET>;
 546                         reset-names = "fpgamgr";
 547                 };
 548
 549                 i2c0: i2c@ffc02200 {
 550                         #address-cells = <1>;
 551                         #size-cells = <0>;
 552                         compatible = "snps,designware-i2c";
 553                         reg = <0xffc02200 0x100>;
 554                         interrupts = <0 105 IRQ_TYPE_LEVEL_HIGH>;
 555                         clocks = <&l4_sp_clk>;
 556                         resets = <&rst I2C0_RESET>;
 557                         status = "disabled";
 558                 };
 559
 560                 i2c1: i2c@ffc02300 {
 561                         #address-cells = <1>;
 562                         #size-cells = <0>;
 563                         compatible = "snps,designware-i2c";
 564                         reg = <0xffc02300 0x100>;
 565                         interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>;
 566                         clocks = <&l4_sp_clk>;
 567                         resets = <&rst I2C1_RESET>;
 568                         status = "disabled";
 569                 };
 570
 571                 i2c2: i2c@ffc02400 {
 572                         #address-cells = <1>;
 573                         #size-cells = <0>;
 574                         compatible = "snps,designware-i2c";
 575                         reg = <0xffc02400 0x100>;
 576                         interrupts = <0 107 IRQ_TYPE_LEVEL_HIGH>;
 577                         clocks = <&l4_sp_clk>;
 578                         resets = <&rst I2C2_RESET>;
 579                         status = "disabled";
 580                 };
 581
 582                 i2c3: i2c@ffc02500 {
 583                         #address-cells = <1>;
 584                         #size-cells = <0>;
 585                         compatible = "snps,designware-i2c";
 586                         reg = <0xffc02500 0x100>;
 587                         interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>;
 588                         clocks = <&l4_sp_clk>;
 589                         resets = <&rst I2C3_RESET>;
 590                         status = "disabled";
 591                 };
 592
 593                 i2c4: i2c@ffc02600 {
 594                         #address-cells = <1>;
 595                         #size-cells = <0>;
 596                         compatible = "snps,designware-i2c";
 597                         reg = <0xffc02600 0x100>;
 598                         interrupts = <0 109 IRQ_TYPE_LEVEL_HIGH>;
 599                         clocks = <&l4_sp_clk>;
 600                         resets = <&rst I2C4_RESET>;
 601                         status = "disabled";
 602                 };
 603
 604                 spi0: spi@ffda4000 {
 605                         compatible = "snps,dw-apb-ssi";
 606                         #address-cells = <1>;
 607                         #size-cells = <0>;
 608                         reg = <0xffda4000 0x100>;
 609                         interrupts = <0 101 4>;
 610                         num-cs = <4>;
 611                         /*32bit_access;*/
 612                         clocks = <&spi_m_clk>;
 613                         resets = <&rst SPIM0_RESET>;
 614                         status = "disabled";
 615                 };
 616
 617                 spi1: spi@ffda5000 {
 618                         compatible = "snps,dw-apb-ssi";
 619                         #address-cells = <1>;
 620                         #size-cells = <0>;
 621                         reg = <0xffda5000 0x100>;
 622                         interrupts = <0 102 4>;
 623                         num-cs = <4>;
 624                         /*32bit_access;*/
 625                         tx-dma-channel = <&pdma 16>;
 626                         rx-dma-channel = <&pdma 17>;
 627                         clocks = <&spi_m_clk>;
 628                         resets = <&rst SPIM1_RESET>;
 629                         status = "disabled";
 630                 };
 631
 632                 sdr: sdr@ffcfb100 {
 633                         compatible = "altr,sdr-ctl", "syscon";
 634                         reg = <0xffcfb100 0x80>;
 635                 };
 636
 637                 L2: l2-cache@fffff000 {
 638                         compatible = "arm,pl310-cache";
 639                         reg = <0xfffff000 0x1000>;
 640                         interrupts = <0 18 IRQ_TYPE_LEVEL_HIGH>;
 641                         cache-unified;
 642                         cache-level = <2>;
 643                         prefetch-data = <1>;
 644                         prefetch-instr = <1>;
 645                         arm,shared-override;
 646                 };
 647
 648                 mmc: dwmmc0@ff808000 {
 649                         #address-cells = <1>;
 650                         #size-cells = <0>;
 651                         compatible = "altr,socfpga-dw-mshc";
 652                         reg = <0xff808000 0x1000>;
 653                         interrupts = <0 98 IRQ_TYPE_LEVEL_HIGH>;
 654                         fifo-depth = <0x400>;
 655                         clocks = <&l4_mp_clk>, <&sdmmc_clk>;
 656                         clock-names = "biu", "ciu";
 657                         resets = <&rst SDMMC_RESET>;
 658                         status = "disabled";
 659                 };
 660
 661                 nand: nand@ffb90000 {
 662                         #address-cells = <1>;
 663                         #size-cells = <1>;
 664                         compatible = "altr,socfpga-denali-nand";
 665                         reg = <0xffb90000 0x72000>,
 666                               <0xffb80000 0x10000>;
 667                         reg-names = "nand_data", "denali_reg";
 668                         interrupts = <0 99 4>;
 669                         clocks = <&nand_clk>, <&nand_x_clk>, <&nand_ecc_clk>;
 670                         clock-names = "nand", "nand_x", "ecc";
 671                         resets = <&rst NAND_RESET>;
 672                         status = "disabled";
 673                 };
 674
 675                 ocram: sram@ffe00000 {
 676                         compatible = "mmio-sram";
 677                         reg = <0xffe00000 0x40000>;
 678                 };
 679
 680                 eccmgr: eccmgr {
 681                         compatible = "altr,socfpga-a10-ecc-manager";
 682                         altr,sysmgr-syscon = <&sysmgr>;
 683                         #address-cells = <1>;
 684                         #size-cells = <1>;
 685                         interrupts = <0 2 IRQ_TYPE_LEVEL_HIGH>,
 686                                      <0 0 IRQ_TYPE_LEVEL_HIGH>;
 687                         interrupt-controller;
 688                         #interrupt-cells = <2>;
 689                         ranges;
 690
 691                         sdramedac {
 692                                 compatible = "altr,sdram-edac-a10";
 693                                 altr,sdr-syscon = <&sdr>;
 694                                 interrupts = <17 IRQ_TYPE_LEVEL_HIGH>,
 695                                              <49 IRQ_TYPE_LEVEL_HIGH>;
 696                         };
 697
 698                         l2-ecc@ffd06010 {
 699                                 compatible = "altr,socfpga-a10-l2-ecc";
 700                                 reg = <0xffd06010 0x4>;
 701                                 interrupts = <0 IRQ_TYPE_LEVEL_HIGH>,
 702                                              <32 IRQ_TYPE_LEVEL_HIGH>;
 703                         };
 704
 705                         ocram-ecc@ff8c3000 {
 706                                 compatible = "altr,socfpga-a10-ocram-ecc";
 707                                 reg = <0xff8c3000 0x400>;
 708                                 interrupts = <1 IRQ_TYPE_LEVEL_HIGH>,
 709                                              <33 IRQ_TYPE_LEVEL_HIGH>;
 710                         };
 711
 712                         emac0-rx-ecc@ff8c0800 {
 713                                 compatible = "altr,socfpga-eth-mac-ecc";
 714                                 reg = <0xff8c0800 0x400>;
 715                                 altr,ecc-parent = <&gmac0>;
 716                                 interrupts = <4 IRQ_TYPE_LEVEL_HIGH>,
 717                                              <36 IRQ_TYPE_LEVEL_HIGH>;
 718                         };
 719
 720                         emac0-tx-ecc@ff8c0c00 {
 721                                 compatible = "altr,socfpga-eth-mac-ecc";
 722                                 reg = <0xff8c0c00 0x400>;
 723                                 altr,ecc-parent = <&gmac0>;
 724                                 interrupts = <5 IRQ_TYPE_LEVEL_HIGH>,
 725                                              <37 IRQ_TYPE_LEVEL_HIGH>;
 726                         };
 727
 728                         dma-ecc@ff8c8000 {
 729                                 compatible = "altr,socfpga-dma-ecc";
 730                                 reg = <0xff8c8000 0x400>;
 731                                 altr,ecc-parent = <&pdma>;
 732                                 interrupts = <10 IRQ_TYPE_LEVEL_HIGH>,
 733                                              <42 IRQ_TYPE_LEVEL_HIGH>;
 734                         };
 735
 736                         usb0-ecc@ff8c8800 {
 737                                 compatible = "altr,socfpga-usb-ecc";
 738                                 reg = <0xff8c8800 0x400>;
 739                                 altr,ecc-parent = <&usb0>;
 740                                 interrupts = <2 IRQ_TYPE_LEVEL_HIGH>,
 741                                              <34 IRQ_TYPE_LEVEL_HIGH>;
 742                         };
 743                 };
 744
 745                 qspi: spi@ff809000 {
 746                         compatible = "cdns,qspi-nor";
 747                         #address-cells = <1>;
 748                         #size-cells = <0>;
 749                         reg = <0xff809000 0x100>,
 750                               <0xffa00000 0x100000>;
 751                         interrupts = <0 100 IRQ_TYPE_LEVEL_HIGH>;
 752                         cdns,fifo-depth = <128>;
 753                         cdns,fifo-width = <4>;
 754                         cdns,trigger-address = <0x00000000>;
 755                         clocks = <&qspi_clk>;
 756                         resets = <&rst QSPI_RESET>;
 757                         status = "disabled";
 758                 };
 759
 760                 rst: rstmgr@ffd05000 {
 761                         #reset-cells = <1>;
 762                         compatible = "altr,rst-mgr";
 763                         reg = <0xffd05000 0x100>;
 764                         altr,modrst-offset = <0x20>;
 765                 };
 766
 767                 scu: snoop-control-unit@ffffc000 {
 768                         compatible = "arm,cortex-a9-scu";
 769                         reg = <0xffffc000 0x100>;
 770                 };
 771
 772                 sysmgr: sysmgr@ffd06000 {
 773                         compatible = "altr,sys-mgr", "syscon";
 774                         reg = <0xffd06000 0x300>;
 775                         cpu1-start-addr = <0xffd06230>;
 776                 };
 777
 778                 /* Local timer */
 779                 timer@ffffc600 {
 780                         compatible = "arm,cortex-a9-twd-timer";
 781                         reg = <0xffffc600 0x100>;
 782                         interrupts = <1 13 0xf01>;
 783                         clocks = <&mpu_periph_clk>;
 784                 };
 785
 786                 timer0: timer0@ffc02700 {
 787                         compatible = "snps,dw-apb-timer";
 788                         interrupts = <0 115 IRQ_TYPE_LEVEL_HIGH>;
 789                         reg = <0xffc02700 0x100>;
 790                         clocks = <&l4_sp_clk>;
 791                         clock-names = "timer";
 792                         resets = <&rst SPTIMER0_RESET>;
 793                         reset-names = "timer";
 794                 };
 795
 796                 timer1: timer1@ffc02800 {
 797                         compatible = "snps,dw-apb-timer";
 798                         interrupts = <0 116 IRQ_TYPE_LEVEL_HIGH>;
 799                         reg = <0xffc02800 0x100>;
 800                         clocks = <&l4_sp_clk>;
 801                         clock-names = "timer";
 802                         resets = <&rst SPTIMER1_RESET>;
 803                         reset-names = "timer";
 804                 };
 805
 806                 timer2: timer2@ffd00000 {
 807                         compatible = "snps,dw-apb-timer";
 808                         interrupts = <0 117 IRQ_TYPE_LEVEL_HIGH>;
 809                         reg = <0xffd00000 0x100>;
 810                         clocks = <&l4_sys_free_clk>;
 811                         clock-names = "timer";
 812                         resets = <&rst L4SYSTIMER0_RESET>;
 813                         reset-names = "timer";
 814                 };
 815
 816                 timer3: timer3@ffd00100 {
 817                         compatible = "snps,dw-apb-timer";
 818                         interrupts = <0 118 IRQ_TYPE_LEVEL_HIGH>;
 819                         reg = <0xffd01000 0x100>;
 820                         clocks = <&l4_sys_free_clk>;
 821                         clock-names = "timer";
 822                         resets = <&rst L4SYSTIMER1_RESET>;
 823                         reset-names = "timer";
 824                 };
 825
 826                 uart0: serial0@ffc02000 {
 827                         compatible = "snps,dw-apb-uart";
 828                         reg = <0xffc02000 0x100>;
 829                         interrupts = <0 110 IRQ_TYPE_LEVEL_HIGH>;
 830                         reg-shift = <2>;
 831                         reg-io-width = <4>;
 832                         clocks = <&l4_sp_clk>;
 833                         resets = <&rst UART0_RESET>;
 834                         status = "disabled";
 835                 };
 836
 837                 uart1: serial1@ffc02100 {
 838                         compatible = "snps,dw-apb-uart";
 839                         reg = <0xffc02100 0x100>;
 840                         interrupts = <0 111 IRQ_TYPE_LEVEL_HIGH>;
 841                         reg-shift = <2>;
 842                         reg-io-width = <4>;
 843                         clocks = <&l4_sp_clk>;
 844                         resets = <&rst UART1_RESET>;
 845                         status = "disabled";
 846                 };
 847
 848                 usbphy0: usbphy {
 849                         #phy-cells = <0>;
 850                         compatible = "usb-nop-xceiv";
 851                         status = "okay";
 852                 };
 853
 854                 usb0: usb@ffb00000 {
 855                         compatible = "snps,dwc2";
 856                         reg = <0xffb00000 0xffff>;
 857                         interrupts = <0 95 IRQ_TYPE_LEVEL_HIGH>;
 858                         clocks = <&usb_clk>;
 859                         clock-names = "otg";
 860                         resets = <&rst USB0_RESET>;
 861                         reset-names = "dwc2";
 862                         phys = <&usbphy0>;
 863                         phy-names = "usb2-phy";
 864                         status = "disabled";
 865                 };
 866
 867                 usb1: usb@ffb40000 {
 868                         compatible = "snps,dwc2";
 869                         reg = <0xffb40000 0xffff>;
 870                         interrupts = <0 96 IRQ_TYPE_LEVEL_HIGH>;
 871                         clocks = <&usb_clk>;
 872                         clock-names = "otg";
 873                         resets = <&rst USB1_RESET>;
 874                         reset-names = "dwc2";
 875                         phys = <&usbphy0>;
 876                         phy-names = "usb2-phy";
 877                         status = "disabled";
 878                 };
 879
 880                 watchdog0: watchdog@ffd00200 {
 881                         compatible = "snps,dw-wdt";
 882                         reg = <0xffd00200 0x100>;
 883                         interrupts = <0 119 IRQ_TYPE_LEVEL_HIGH>;
 884                         clocks = <&l4_sys_free_clk>;
 885                         resets = <&rst L4WD0_RESET>;
 886                         status = "disabled";
 887                 };
 888
 889                 watchdog1: watchdog@ffd00300 {
 890                         compatible = "snps,dw-wdt";
 891                         reg = <0xffd00300 0x100>;
 892                         interrupts = <0 120 IRQ_TYPE_LEVEL_HIGH>;
 893                         clocks = <&l4_sys_free_clk>;
 894                         resets = <&rst L4WD1_RESET>;
 895                         status = "disabled";
 896                 };
 897         };
 898 };