2 * Copyright 2017 - Alexandre Torgue <alexandre.torgue@st.com>
4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual
6 * licensing only applies to this file, and not this project as a
9 * a) This file is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of the
12 * License, or (at your option) any later version.
14 * This file is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
21 * b) Permission is hereby granted, free of charge, to any person
22 * obtaining a copy of this software and associated documentation
23 * files (the "Software"), to deal in the Software without
24 * restriction, including without limitation the rights to use,
25 * copy, modify, merge, publish, distribute, sublicense, and/or
26 * sell copies of the Software, and to permit persons to whom the
27 * Software is furnished to do so, subject to the following
30 * The above copyright notice and this permission notice shall be
31 * included in all copies or substantial portions of the Software.
33 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
34 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
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40 * OTHER DEALINGS IN THE SOFTWARE.
43 #include "skeleton.dtsi"
44 #include "armv7-m.dtsi"
45 #include <dt-bindings/clock/stm32h7-clks.h>
46 #include <dt-bindings/mfd/stm32h7-rcc.h>
47 #include <dt-bindings/interrupt-controller/irq.h>
53 compatible = "fixed-clock";
54 clock-frequency = <0>;
59 compatible = "fixed-clock";
60 clock-frequency = <32768>;
65 compatible = "fixed-clock";
66 clock-frequency = <0>;
71 timer5: timer@40000c00 {
72 compatible = "st,stm32-timer";
73 reg = <0x40000c00 0x400>;
75 clocks = <&rcc TIM5_CK>;
78 lptimer1: timer@40002400 {
81 compatible = "st,stm32-lptimer";
82 reg = <0x40002400 0x400>;
83 clocks = <&rcc LPTIM1_CK>;
88 compatible = "st,stm32-pwm-lp";
93 compatible = "st,stm32-lptimer-trigger";
99 compatible = "st,stm32-lptimer-counter";
105 #address-cells = <1>;
107 compatible = "st,stm32h7-spi";
108 reg = <0x40003800 0x400>;
110 clocks = <&rcc SPI2_CK>;
116 #address-cells = <1>;
118 compatible = "st,stm32h7-spi";
119 reg = <0x40003c00 0x400>;
121 clocks = <&rcc SPI3_CK>;
125 usart2: serial@40004400 {
126 compatible = "st,stm32f7-uart";
127 reg = <0x40004400 0x400>;
130 clocks = <&rcc USART2_CK>;
134 compatible = "st,stm32h7-dac-core";
135 reg = <0x40007400 0x400>;
136 clocks = <&rcc DAC12_CK>;
137 clock-names = "pclk";
138 #address-cells = <1>;
143 compatible = "st,stm32-dac";
144 #io-channels-cells = <1>;
150 compatible = "st,stm32-dac";
151 #io-channels-cells = <1>;
157 usart1: serial@40011000 {
158 compatible = "st,stm32f7-uart";
159 reg = <0x40011000 0x400>;
162 clocks = <&rcc USART1_CK>;
166 #address-cells = <1>;
168 compatible = "st,stm32h7-spi";
169 reg = <0x40013000 0x400>;
171 clocks = <&rcc SPI1_CK>;
176 #address-cells = <1>;
178 compatible = "st,stm32h7-spi";
179 reg = <0x40013400 0x400>;
181 clocks = <&rcc SPI4_CK>;
186 #address-cells = <1>;
188 compatible = "st,stm32h7-spi";
189 reg = <0x40015000 0x400>;
191 clocks = <&rcc SPI5_CK>;
196 compatible = "st,stm32-dma";
197 reg = <0x40020000 0x400>;
206 clocks = <&rcc DMA1_CK>;
214 compatible = "st,stm32-dma";
215 reg = <0x40020400 0x400>;
224 clocks = <&rcc DMA2_CK>;
231 dmamux1: dma-router@40020800 {
232 compatible = "st,stm32h7-dmamux";
233 reg = <0x40020800 0x1c>;
236 dma-requests = <128>;
237 dma-masters = <&dma1 &dma2>;
238 clocks = <&rcc DMA1_CK>;
241 adc_12: adc@40022000 {
242 compatible = "st,stm32h7-adc-core";
243 reg = <0x40022000 0x400>;
245 clocks = <&rcc ADC12_CK>;
247 interrupt-controller;
248 #interrupt-cells = <1>;
249 #address-cells = <1>;
254 compatible = "st,stm32h7-adc";
255 #io-channel-cells = <1>;
257 interrupt-parent = <&adc_12>;
263 compatible = "st,stm32h7-adc";
264 #io-channel-cells = <1>;
266 interrupt-parent = <&adc_12>;
272 usbotg_hs: usb@40040000 {
273 compatible = "st,stm32f7-hsotg";
274 reg = <0x40040000 0x40000>;
276 clocks = <&rcc USB1OTG_CK>;
278 g-rx-fifo-size = <256>;
279 g-np-tx-fifo-size = <32>;
280 g-tx-fifo-size = <128 128 64 64 64 64 32 32>;
284 usbotg_fs: usb@40080000 {
285 compatible = "st,stm32f4x9-fsotg";
286 reg = <0x40080000 0x40000>;
288 clocks = <&rcc USB2OTG_CK>;
293 mdma1: dma@52000000 {
294 compatible = "st,stm32h7-mdma";
295 reg = <0x52000000 0x1000>;
297 clocks = <&rcc MDMA_CK>;
303 exti: interrupt-controller@58000000 {
304 compatible = "st,stm32h7-exti";
305 interrupt-controller;
306 #interrupt-cells = <2>;
307 reg = <0x58000000 0x400>;
308 interrupts = <1>, <2>, <3>, <6>, <7>, <8>, <9>, <10>, <23>, <40>, <41>, <62>, <76>;
311 syscfg: system-config@58000400 {
312 compatible = "syscon";
313 reg = <0x58000400 0x400>;
317 #address-cells = <1>;
319 compatible = "st,stm32h7-spi";
320 reg = <0x58001400 0x400>;
322 clocks = <&rcc SPI6_CK>;
326 lptimer2: timer@58002400 {
327 #address-cells = <1>;
329 compatible = "st,stm32-lptimer";
330 reg = <0x58002400 0x400>;
331 clocks = <&rcc LPTIM2_CK>;
336 compatible = "st,stm32-pwm-lp";
341 compatible = "st,stm32-lptimer-trigger";
347 compatible = "st,stm32-lptimer-counter";
352 lptimer3: timer@58002800 {
353 #address-cells = <1>;
355 compatible = "st,stm32-lptimer";
356 reg = <0x58002800 0x400>;
357 clocks = <&rcc LPTIM3_CK>;
362 compatible = "st,stm32-pwm-lp";
367 compatible = "st,stm32-lptimer-trigger";
373 lptimer4: timer@58002c00 {
374 #address-cells = <1>;
376 compatible = "st,stm32-lptimer";
377 reg = <0x58002c00 0x400>;
378 clocks = <&rcc LPTIM4_CK>;
383 compatible = "st,stm32-pwm-lp";
388 lptimer5: timer@58003000 {
389 #address-cells = <1>;
391 compatible = "st,stm32-lptimer";
392 reg = <0x58003000 0x400>;
393 clocks = <&rcc LPTIM5_CK>;
398 compatible = "st,stm32-pwm-lp";
403 vrefbuf: regulator@58003c00 {
404 compatible = "st,stm32-vrefbuf";
405 reg = <0x58003C00 0x8>;
406 clocks = <&rcc VREF_CK>;
407 regulator-min-microvolt = <1500000>;
408 regulator-max-microvolt = <2500000>;
413 compatible = "st,stm32h7-rtc";
414 reg = <0x58004000 0x400>;
415 clocks = <&rcc RTCAPB_CK>, <&rcc RTC_CK>;
416 clock-names = "pclk", "rtc_ck";
417 assigned-clocks = <&rcc RTC_CK>;
418 assigned-clock-parents = <&rcc LSE_CK>;
419 interrupt-parent = <&exti>;
420 interrupts = <17 IRQ_TYPE_EDGE_RISING>;
421 interrupt-names = "alarm";
422 st,syscfg = <&pwrcfg>;
426 rcc: reset-clock-controller@58024400 {
427 compatible = "st,stm32h743-rcc", "st,stm32-rcc";
428 reg = <0x58024400 0x400>;
431 clocks = <&clk_hse>, <&clk_lse>, <&clk_i2s>;
432 st,syscfg = <&pwrcfg>;
435 pwrcfg: power-config@58024800 {
436 compatible = "syscon";
437 reg = <0x58024800 0x400>;
440 adc_3: adc@58026000 {
441 compatible = "st,stm32h7-adc-core";
442 reg = <0x58026000 0x400>;
444 clocks = <&rcc ADC3_CK>;
446 interrupt-controller;
447 #interrupt-cells = <1>;
448 #address-cells = <1>;
453 compatible = "st,stm32h7-adc";
454 #io-channel-cells = <1>;
456 interrupt-parent = <&adc_3>;
465 clock-frequency = <250000000>;