1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
3 * Copyright (C) STMicroelectronics 2017 - All Rights Reserved
4 * Author: Ludovic Barre <ludovic.barre@st.com> for STMicroelectronics.
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/clock/stm32mp1-clks.h>
8 #include <dt-bindings/reset/stm32mp1-resets.h>
19 compatible = "arm,cortex-a7";
20 clock-frequency = <650000000>;
27 compatible = "arm,psci-1.0";
31 intc: interrupt-controller@a0021000 {
32 compatible = "arm,cortex-a7-gic";
33 #interrupt-cells = <3>;
35 reg = <0xa0021000 0x1000>,
40 compatible = "arm,armv7-timer";
41 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
42 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
43 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
44 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
45 interrupt-parent = <&intc>;
51 compatible = "fixed-clock";
52 clock-frequency = <24000000>;
57 compatible = "fixed-clock";
58 clock-frequency = <64000000>;
63 compatible = "fixed-clock";
64 clock-frequency = <32768>;
69 compatible = "fixed-clock";
70 clock-frequency = <32000>;
75 compatible = "fixed-clock";
76 clock-frequency = <4000000>;
81 cpu_thermal: cpu-thermal {
82 polling-delay-passive = <0>;
84 thermal-sensors = <&dts>;
87 cpu_alert1: cpu-alert1 {
88 temperature = <85000>;
94 temperature = <120000>;
105 booster: regulator-booster {
106 compatible = "st,stm32mp1-booster";
107 st,syscfg = <&syscfg>;
112 compatible = "simple-bus";
113 #address-cells = <1>;
115 interrupt-parent = <&intc>;
118 timers2: timer@40000000 {
119 #address-cells = <1>;
121 compatible = "st,stm32-timers";
122 reg = <0x40000000 0x400>;
123 clocks = <&rcc TIM2_K>;
125 dmas = <&dmamux1 18 0x400 0x1>,
126 <&dmamux1 19 0x400 0x1>,
127 <&dmamux1 20 0x400 0x1>,
128 <&dmamux1 21 0x400 0x1>,
129 <&dmamux1 22 0x400 0x1>;
130 dma-names = "ch1", "ch2", "ch3", "ch4", "up";
134 compatible = "st,stm32-pwm";
140 compatible = "st,stm32h7-timer-trigger";
146 compatible = "st,stm32-timer-counter";
151 timers3: timer@40001000 {
152 #address-cells = <1>;
154 compatible = "st,stm32-timers";
155 reg = <0x40001000 0x400>;
156 clocks = <&rcc TIM3_K>;
158 dmas = <&dmamux1 23 0x400 0x1>,
159 <&dmamux1 24 0x400 0x1>,
160 <&dmamux1 25 0x400 0x1>,
161 <&dmamux1 26 0x400 0x1>,
162 <&dmamux1 27 0x400 0x1>,
163 <&dmamux1 28 0x400 0x1>;
164 dma-names = "ch1", "ch2", "ch3", "ch4", "up", "trig";
168 compatible = "st,stm32-pwm";
174 compatible = "st,stm32h7-timer-trigger";
180 compatible = "st,stm32-timer-counter";
185 timers4: timer@40002000 {
186 #address-cells = <1>;
188 compatible = "st,stm32-timers";
189 reg = <0x40002000 0x400>;
190 clocks = <&rcc TIM4_K>;
192 dmas = <&dmamux1 29 0x400 0x1>,
193 <&dmamux1 30 0x400 0x1>,
194 <&dmamux1 31 0x400 0x1>,
195 <&dmamux1 32 0x400 0x1>;
196 dma-names = "ch1", "ch2", "ch3", "ch4";
200 compatible = "st,stm32-pwm";
206 compatible = "st,stm32h7-timer-trigger";
212 compatible = "st,stm32-timer-counter";
217 timers5: timer@40003000 {
218 #address-cells = <1>;
220 compatible = "st,stm32-timers";
221 reg = <0x40003000 0x400>;
222 clocks = <&rcc TIM5_K>;
224 dmas = <&dmamux1 55 0x400 0x1>,
225 <&dmamux1 56 0x400 0x1>,
226 <&dmamux1 57 0x400 0x1>,
227 <&dmamux1 58 0x400 0x1>,
228 <&dmamux1 59 0x400 0x1>,
229 <&dmamux1 60 0x400 0x1>;
230 dma-names = "ch1", "ch2", "ch3", "ch4", "up", "trig";
234 compatible = "st,stm32-pwm";
240 compatible = "st,stm32h7-timer-trigger";
246 compatible = "st,stm32-timer-counter";
251 timers6: timer@40004000 {
252 #address-cells = <1>;
254 compatible = "st,stm32-timers";
255 reg = <0x40004000 0x400>;
256 clocks = <&rcc TIM6_K>;
258 dmas = <&dmamux1 69 0x400 0x1>;
263 compatible = "st,stm32h7-timer-trigger";
269 timers7: timer@40005000 {
270 #address-cells = <1>;
272 compatible = "st,stm32-timers";
273 reg = <0x40005000 0x400>;
274 clocks = <&rcc TIM7_K>;
276 dmas = <&dmamux1 70 0x400 0x1>;
281 compatible = "st,stm32h7-timer-trigger";
287 timers12: timer@40006000 {
288 #address-cells = <1>;
290 compatible = "st,stm32-timers";
291 reg = <0x40006000 0x400>;
292 clocks = <&rcc TIM12_K>;
297 compatible = "st,stm32-pwm";
303 compatible = "st,stm32h7-timer-trigger";
309 timers13: timer@40007000 {
310 #address-cells = <1>;
312 compatible = "st,stm32-timers";
313 reg = <0x40007000 0x400>;
314 clocks = <&rcc TIM13_K>;
319 compatible = "st,stm32-pwm";
325 compatible = "st,stm32h7-timer-trigger";
331 timers14: timer@40008000 {
332 #address-cells = <1>;
334 compatible = "st,stm32-timers";
335 reg = <0x40008000 0x400>;
336 clocks = <&rcc TIM14_K>;
341 compatible = "st,stm32-pwm";
347 compatible = "st,stm32h7-timer-trigger";
353 lptimer1: timer@40009000 {
354 #address-cells = <1>;
356 compatible = "st,stm32-lptimer";
357 reg = <0x40009000 0x400>;
358 clocks = <&rcc LPTIM1_K>;
363 compatible = "st,stm32-pwm-lp";
369 compatible = "st,stm32-lptimer-trigger";
375 compatible = "st,stm32-lptimer-counter";
381 #address-cells = <1>;
383 compatible = "st,stm32h7-spi";
384 reg = <0x4000b000 0x400>;
385 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
386 clocks = <&rcc SPI2_K>;
387 resets = <&rcc SPI2_R>;
388 dmas = <&dmamux1 39 0x400 0x05>,
389 <&dmamux1 40 0x400 0x05>;
390 dma-names = "rx", "tx";
394 i2s2: audio-controller@4000b000 {
395 compatible = "st,stm32h7-i2s";
396 #sound-dai-cells = <0>;
397 reg = <0x4000b000 0x400>;
398 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
399 dmas = <&dmamux1 39 0x400 0x01>,
400 <&dmamux1 40 0x400 0x01>;
401 dma-names = "rx", "tx";
406 #address-cells = <1>;
408 compatible = "st,stm32h7-spi";
409 reg = <0x4000c000 0x400>;
410 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
411 clocks = <&rcc SPI3_K>;
412 resets = <&rcc SPI3_R>;
413 dmas = <&dmamux1 61 0x400 0x05>,
414 <&dmamux1 62 0x400 0x05>;
415 dma-names = "rx", "tx";
419 i2s3: audio-controller@4000c000 {
420 compatible = "st,stm32h7-i2s";
421 #sound-dai-cells = <0>;
422 reg = <0x4000c000 0x400>;
423 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
424 dmas = <&dmamux1 61 0x400 0x01>,
425 <&dmamux1 62 0x400 0x01>;
426 dma-names = "rx", "tx";
430 spdifrx: audio-controller@4000d000 {
431 compatible = "st,stm32h7-spdifrx";
432 #sound-dai-cells = <0>;
433 reg = <0x4000d000 0x400>;
434 clocks = <&rcc SPDIF_K>;
435 clock-names = "kclk";
436 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
437 dmas = <&dmamux1 93 0x400 0x01>,
438 <&dmamux1 94 0x400 0x01>;
439 dma-names = "rx", "rx-ctrl";
443 usart2: serial@4000e000 {
444 compatible = "st,stm32h7-uart";
445 reg = <0x4000e000 0x400>;
446 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
447 clocks = <&rcc USART2_K>;
451 usart3: serial@4000f000 {
452 compatible = "st,stm32h7-uart";
453 reg = <0x4000f000 0x400>;
454 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
455 clocks = <&rcc USART3_K>;
459 uart4: serial@40010000 {
460 compatible = "st,stm32h7-uart";
461 reg = <0x40010000 0x400>;
462 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
463 clocks = <&rcc UART4_K>;
467 uart5: serial@40011000 {
468 compatible = "st,stm32h7-uart";
469 reg = <0x40011000 0x400>;
470 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
471 clocks = <&rcc UART5_K>;
476 compatible = "st,stm32mp15-i2c";
477 reg = <0x40012000 0x400>;
478 interrupt-names = "event", "error";
479 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
480 <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
481 clocks = <&rcc I2C1_K>;
482 resets = <&rcc I2C1_R>;
483 #address-cells = <1>;
485 st,syscfg-fmp = <&syscfg 0x4 0x1>;
491 compatible = "st,stm32mp15-i2c";
492 reg = <0x40013000 0x400>;
493 interrupt-names = "event", "error";
494 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
495 <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
496 clocks = <&rcc I2C2_K>;
497 resets = <&rcc I2C2_R>;
498 #address-cells = <1>;
500 st,syscfg-fmp = <&syscfg 0x4 0x2>;
506 compatible = "st,stm32mp15-i2c";
507 reg = <0x40014000 0x400>;
508 interrupt-names = "event", "error";
509 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
510 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
511 clocks = <&rcc I2C3_K>;
512 resets = <&rcc I2C3_R>;
513 #address-cells = <1>;
515 st,syscfg-fmp = <&syscfg 0x4 0x4>;
521 compatible = "st,stm32mp15-i2c";
522 reg = <0x40015000 0x400>;
523 interrupt-names = "event", "error";
524 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
525 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
526 clocks = <&rcc I2C5_K>;
527 resets = <&rcc I2C5_R>;
528 #address-cells = <1>;
530 st,syscfg-fmp = <&syscfg 0x4 0x10>;
536 compatible = "st,stm32-cec";
537 reg = <0x40016000 0x400>;
538 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
539 clocks = <&rcc CEC_K>, <&clk_lse>;
540 clock-names = "cec", "hdmi-cec";
545 compatible = "st,stm32h7-dac-core";
546 reg = <0x40017000 0x400>;
547 clocks = <&rcc DAC12>;
548 clock-names = "pclk";
549 #address-cells = <1>;
554 compatible = "st,stm32-dac";
555 #io-channel-cells = <1>;
561 compatible = "st,stm32-dac";
562 #io-channel-cells = <1>;
568 uart7: serial@40018000 {
569 compatible = "st,stm32h7-uart";
570 reg = <0x40018000 0x400>;
571 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
572 clocks = <&rcc UART7_K>;
576 uart8: serial@40019000 {
577 compatible = "st,stm32h7-uart";
578 reg = <0x40019000 0x400>;
579 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
580 clocks = <&rcc UART8_K>;
584 timers1: timer@44000000 {
585 #address-cells = <1>;
587 compatible = "st,stm32-timers";
588 reg = <0x44000000 0x400>;
589 clocks = <&rcc TIM1_K>;
591 dmas = <&dmamux1 11 0x400 0x1>,
592 <&dmamux1 12 0x400 0x1>,
593 <&dmamux1 13 0x400 0x1>,
594 <&dmamux1 14 0x400 0x1>,
595 <&dmamux1 15 0x400 0x1>,
596 <&dmamux1 16 0x400 0x1>,
597 <&dmamux1 17 0x400 0x1>;
598 dma-names = "ch1", "ch2", "ch3", "ch4",
603 compatible = "st,stm32-pwm";
609 compatible = "st,stm32h7-timer-trigger";
615 compatible = "st,stm32-timer-counter";
620 timers8: timer@44001000 {
621 #address-cells = <1>;
623 compatible = "st,stm32-timers";
624 reg = <0x44001000 0x400>;
625 clocks = <&rcc TIM8_K>;
627 dmas = <&dmamux1 47 0x400 0x1>,
628 <&dmamux1 48 0x400 0x1>,
629 <&dmamux1 49 0x400 0x1>,
630 <&dmamux1 50 0x400 0x1>,
631 <&dmamux1 51 0x400 0x1>,
632 <&dmamux1 52 0x400 0x1>,
633 <&dmamux1 53 0x400 0x1>;
634 dma-names = "ch1", "ch2", "ch3", "ch4",
639 compatible = "st,stm32-pwm";
645 compatible = "st,stm32h7-timer-trigger";
651 compatible = "st,stm32-timer-counter";
656 usart6: serial@44003000 {
657 compatible = "st,stm32h7-uart";
658 reg = <0x44003000 0x400>;
659 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
660 clocks = <&rcc USART6_K>;
665 #address-cells = <1>;
667 compatible = "st,stm32h7-spi";
668 reg = <0x44004000 0x400>;
669 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
670 clocks = <&rcc SPI1_K>;
671 resets = <&rcc SPI1_R>;
672 dmas = <&dmamux1 37 0x400 0x05>,
673 <&dmamux1 38 0x400 0x05>;
674 dma-names = "rx", "tx";
678 i2s1: audio-controller@44004000 {
679 compatible = "st,stm32h7-i2s";
680 #sound-dai-cells = <0>;
681 reg = <0x44004000 0x400>;
682 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
683 dmas = <&dmamux1 37 0x400 0x01>,
684 <&dmamux1 38 0x400 0x01>;
685 dma-names = "rx", "tx";
690 #address-cells = <1>;
692 compatible = "st,stm32h7-spi";
693 reg = <0x44005000 0x400>;
694 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
695 clocks = <&rcc SPI4_K>;
696 resets = <&rcc SPI4_R>;
697 dmas = <&dmamux1 83 0x400 0x05>,
698 <&dmamux1 84 0x400 0x05>;
699 dma-names = "rx", "tx";
703 timers15: timer@44006000 {
704 #address-cells = <1>;
706 compatible = "st,stm32-timers";
707 reg = <0x44006000 0x400>;
708 clocks = <&rcc TIM15_K>;
710 dmas = <&dmamux1 105 0x400 0x1>,
711 <&dmamux1 106 0x400 0x1>,
712 <&dmamux1 107 0x400 0x1>,
713 <&dmamux1 108 0x400 0x1>;
714 dma-names = "ch1", "up", "trig", "com";
718 compatible = "st,stm32-pwm";
724 compatible = "st,stm32h7-timer-trigger";
730 timers16: timer@44007000 {
731 #address-cells = <1>;
733 compatible = "st,stm32-timers";
734 reg = <0x44007000 0x400>;
735 clocks = <&rcc TIM16_K>;
737 dmas = <&dmamux1 109 0x400 0x1>,
738 <&dmamux1 110 0x400 0x1>;
739 dma-names = "ch1", "up";
743 compatible = "st,stm32-pwm";
748 compatible = "st,stm32h7-timer-trigger";
754 timers17: timer@44008000 {
755 #address-cells = <1>;
757 compatible = "st,stm32-timers";
758 reg = <0x44008000 0x400>;
759 clocks = <&rcc TIM17_K>;
761 dmas = <&dmamux1 111 0x400 0x1>,
762 <&dmamux1 112 0x400 0x1>;
763 dma-names = "ch1", "up";
767 compatible = "st,stm32-pwm";
773 compatible = "st,stm32h7-timer-trigger";
780 #address-cells = <1>;
782 compatible = "st,stm32h7-spi";
783 reg = <0x44009000 0x400>;
784 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
785 clocks = <&rcc SPI5_K>;
786 resets = <&rcc SPI5_R>;
787 dmas = <&dmamux1 85 0x400 0x05>,
788 <&dmamux1 86 0x400 0x05>;
789 dma-names = "rx", "tx";
794 compatible = "st,stm32h7-sai";
795 #address-cells = <1>;
797 ranges = <0 0x4400a000 0x400>;
798 reg = <0x4400a000 0x4>, <0x4400a3f0 0x10>;
799 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
800 resets = <&rcc SAI1_R>;
803 sai1a: audio-controller@4400a004 {
804 #sound-dai-cells = <0>;
806 compatible = "st,stm32-sai-sub-a";
808 clocks = <&rcc SAI1_K>;
809 clock-names = "sai_ck";
810 dmas = <&dmamux1 87 0x400 0x01>;
814 sai1b: audio-controller@4400a024 {
815 #sound-dai-cells = <0>;
816 compatible = "st,stm32-sai-sub-b";
818 clocks = <&rcc SAI1_K>;
819 clock-names = "sai_ck";
820 dmas = <&dmamux1 88 0x400 0x01>;
826 compatible = "st,stm32h7-sai";
827 #address-cells = <1>;
829 ranges = <0 0x4400b000 0x400>;
830 reg = <0x4400b000 0x4>, <0x4400b3f0 0x10>;
831 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
832 resets = <&rcc SAI2_R>;
835 sai2a: audio-controller@4400b004 {
836 #sound-dai-cells = <0>;
837 compatible = "st,stm32-sai-sub-a";
839 clocks = <&rcc SAI2_K>;
840 clock-names = "sai_ck";
841 dmas = <&dmamux1 89 0x400 0x01>;
845 sai2b: audio-controller@4400b024 {
846 #sound-dai-cells = <0>;
847 compatible = "st,stm32-sai-sub-b";
849 clocks = <&rcc SAI2_K>;
850 clock-names = "sai_ck";
851 dmas = <&dmamux1 90 0x400 0x01>;
857 compatible = "st,stm32h7-sai";
858 #address-cells = <1>;
860 ranges = <0 0x4400c000 0x400>;
861 reg = <0x4400c000 0x4>, <0x4400c3f0 0x10>;
862 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
863 resets = <&rcc SAI3_R>;
866 sai3a: audio-controller@4400c004 {
867 #sound-dai-cells = <0>;
868 compatible = "st,stm32-sai-sub-a";
870 clocks = <&rcc SAI3_K>;
871 clock-names = "sai_ck";
872 dmas = <&dmamux1 113 0x400 0x01>;
876 sai3b: audio-controller@4400c024 {
877 #sound-dai-cells = <0>;
878 compatible = "st,stm32-sai-sub-b";
880 clocks = <&rcc SAI3_K>;
881 clock-names = "sai_ck";
882 dmas = <&dmamux1 114 0x400 0x01>;
887 dfsdm: dfsdm@4400d000 {
888 compatible = "st,stm32mp1-dfsdm";
889 reg = <0x4400d000 0x800>;
890 clocks = <&rcc DFSDM_K>;
891 clock-names = "dfsdm";
892 #address-cells = <1>;
897 compatible = "st,stm32-dfsdm-adc";
898 #io-channel-cells = <1>;
900 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
901 dmas = <&dmamux1 101 0x400 0x01>;
907 compatible = "st,stm32-dfsdm-adc";
908 #io-channel-cells = <1>;
910 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
911 dmas = <&dmamux1 102 0x400 0x01>;
917 compatible = "st,stm32-dfsdm-adc";
918 #io-channel-cells = <1>;
920 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
921 dmas = <&dmamux1 103 0x400 0x01>;
927 compatible = "st,stm32-dfsdm-adc";
928 #io-channel-cells = <1>;
930 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
931 dmas = <&dmamux1 104 0x400 0x01>;
937 compatible = "st,stm32-dfsdm-adc";
938 #io-channel-cells = <1>;
940 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
941 dmas = <&dmamux1 91 0x400 0x01>;
947 compatible = "st,stm32-dfsdm-adc";
948 #io-channel-cells = <1>;
950 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
951 dmas = <&dmamux1 92 0x400 0x01>;
957 dma1: dma-controller@48000000 {
958 compatible = "st,stm32-dma";
959 reg = <0x48000000 0x400>;
960 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
961 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
962 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
963 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
964 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
965 <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
966 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
967 <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
968 clocks = <&rcc DMA1>;
969 resets = <&rcc DMA1_R>;
975 dma2: dma-controller@48001000 {
976 compatible = "st,stm32-dma";
977 reg = <0x48001000 0x400>;
978 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
979 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
980 <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
981 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
982 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
983 <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
984 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
985 <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
986 clocks = <&rcc DMA2>;
987 resets = <&rcc DMA2_R>;
993 dmamux1: dma-router@48002000 {
994 compatible = "st,stm32h7-dmamux";
995 reg = <0x48002000 0x1c>;
997 dma-requests = <128>;
998 dma-masters = <&dma1 &dma2>;
1000 clocks = <&rcc DMAMUX>;
1001 resets = <&rcc DMAMUX_R>;
1005 compatible = "st,stm32mp1-adc-core";
1006 reg = <0x48003000 0x400>;
1007 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
1008 <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
1009 clocks = <&rcc ADC12>, <&rcc ADC12_K>;
1010 clock-names = "bus", "adc";
1011 interrupt-controller;
1012 st,syscfg = <&syscfg>;
1013 #interrupt-cells = <1>;
1014 #address-cells = <1>;
1016 status = "disabled";
1019 compatible = "st,stm32mp1-adc";
1020 #io-channel-cells = <1>;
1022 interrupt-parent = <&adc>;
1024 dmas = <&dmamux1 9 0x400 0x01>;
1026 status = "disabled";
1030 compatible = "st,stm32mp1-adc";
1031 #io-channel-cells = <1>;
1033 interrupt-parent = <&adc>;
1035 dmas = <&dmamux1 10 0x400 0x01>;
1037 status = "disabled";
1041 sdmmc3: sdmmc@48004000 {
1042 compatible = "arm,pl18x", "arm,primecell";
1043 arm,primecell-periphid = <0x10153180>;
1044 reg = <0x48004000 0x400>;
1045 interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
1046 interrupt-names = "cmd_irq";
1047 clocks = <&rcc SDMMC3_K>;
1048 clock-names = "apb_pclk";
1049 resets = <&rcc SDMMC3_R>;
1052 max-frequency = <120000000>;
1053 status = "disabled";
1056 usbotg_hs: usb-otg@49000000 {
1057 compatible = "st,stm32mp15-hsotg", "snps,dwc2";
1058 reg = <0x49000000 0x10000>;
1059 clocks = <&rcc USBO_K>;
1060 clock-names = "otg";
1061 resets = <&rcc USBO_R>;
1062 reset-names = "dwc2";
1063 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
1064 g-rx-fifo-size = <256>;
1065 g-np-tx-fifo-size = <32>;
1066 g-tx-fifo-size = <128 128 64 64 64 64 32 32>;
1068 usb33d-supply = <&usb33>;
1069 status = "disabled";
1072 ipcc: mailbox@4c001000 {
1073 compatible = "st,stm32mp1-ipcc";
1075 reg = <0x4c001000 0x400>;
1077 interrupts-extended =
1078 <&intc GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
1079 <&intc GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
1081 interrupt-names = "rx", "tx", "wakeup";
1082 clocks = <&rcc IPCC>;
1084 status = "disabled";
1087 dcmi: dcmi@4c006000 {
1088 compatible = "st,stm32-dcmi";
1089 reg = <0x4c006000 0x400>;
1090 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
1091 resets = <&rcc CAMITF_R>;
1092 clocks = <&rcc DCMI>;
1093 clock-names = "mclk";
1094 dmas = <&dmamux1 75 0x400 0x0d>;
1096 status = "disabled";
1100 compatible = "st,stm32mp1-rcc", "syscon";
1101 reg = <0x50000000 0x1000>;
1106 pwr_regulators: pwr@50001000 {
1107 compatible = "st,stm32mp1,pwr-reg";
1108 reg = <0x50001000 0x10>;
1111 regulator-name = "reg11";
1112 regulator-min-microvolt = <1100000>;
1113 regulator-max-microvolt = <1100000>;
1117 regulator-name = "reg18";
1118 regulator-min-microvolt = <1800000>;
1119 regulator-max-microvolt = <1800000>;
1123 regulator-name = "usb33";
1124 regulator-min-microvolt = <3300000>;
1125 regulator-max-microvolt = <3300000>;
1129 pwr_mcu: pwr_mcu@50001014 {
1130 compatible = "syscon";
1131 reg = <0x50001014 0x4>;
1134 exti: interrupt-controller@5000d000 {
1135 compatible = "st,stm32mp1-exti", "syscon";
1136 interrupt-controller;
1137 #interrupt-cells = <2>;
1138 reg = <0x5000d000 0x400>;
1141 syscfg: syscon@50020000 {
1142 compatible = "st,stm32mp157-syscfg", "syscon";
1143 reg = <0x50020000 0x400>;
1144 clocks = <&rcc SYSCFG>;
1147 lptimer2: timer@50021000 {
1148 #address-cells = <1>;
1150 compatible = "st,stm32-lptimer";
1151 reg = <0x50021000 0x400>;
1152 clocks = <&rcc LPTIM2_K>;
1153 clock-names = "mux";
1154 status = "disabled";
1157 compatible = "st,stm32-pwm-lp";
1159 status = "disabled";
1163 compatible = "st,stm32-lptimer-trigger";
1165 status = "disabled";
1169 compatible = "st,stm32-lptimer-counter";
1170 status = "disabled";
1174 lptimer3: timer@50022000 {
1175 #address-cells = <1>;
1177 compatible = "st,stm32-lptimer";
1178 reg = <0x50022000 0x400>;
1179 clocks = <&rcc LPTIM3_K>;
1180 clock-names = "mux";
1181 status = "disabled";
1184 compatible = "st,stm32-pwm-lp";
1186 status = "disabled";
1190 compatible = "st,stm32-lptimer-trigger";
1192 status = "disabled";
1196 lptimer4: timer@50023000 {
1197 compatible = "st,stm32-lptimer";
1198 reg = <0x50023000 0x400>;
1199 clocks = <&rcc LPTIM4_K>;
1200 clock-names = "mux";
1201 status = "disabled";
1204 compatible = "st,stm32-pwm-lp";
1206 status = "disabled";
1210 lptimer5: timer@50024000 {
1211 compatible = "st,stm32-lptimer";
1212 reg = <0x50024000 0x400>;
1213 clocks = <&rcc LPTIM5_K>;
1214 clock-names = "mux";
1215 status = "disabled";
1218 compatible = "st,stm32-pwm-lp";
1220 status = "disabled";
1224 vrefbuf: vrefbuf@50025000 {
1225 compatible = "st,stm32-vrefbuf";
1226 reg = <0x50025000 0x8>;
1227 regulator-min-microvolt = <1500000>;
1228 regulator-max-microvolt = <2500000>;
1229 clocks = <&rcc VREF>;
1230 status = "disabled";
1233 sai4: sai@50027000 {
1234 compatible = "st,stm32h7-sai";
1235 #address-cells = <1>;
1237 ranges = <0 0x50027000 0x400>;
1238 reg = <0x50027000 0x4>, <0x500273f0 0x10>;
1239 interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
1240 resets = <&rcc SAI4_R>;
1241 status = "disabled";
1243 sai4a: audio-controller@50027004 {
1244 #sound-dai-cells = <0>;
1245 compatible = "st,stm32-sai-sub-a";
1247 clocks = <&rcc SAI4_K>;
1248 clock-names = "sai_ck";
1249 dmas = <&dmamux1 99 0x400 0x01>;
1250 status = "disabled";
1253 sai4b: audio-controller@50027024 {
1254 #sound-dai-cells = <0>;
1255 compatible = "st,stm32-sai-sub-b";
1257 clocks = <&rcc SAI4_K>;
1258 clock-names = "sai_ck";
1259 dmas = <&dmamux1 100 0x400 0x01>;
1260 status = "disabled";
1264 dts: thermal@50028000 {
1265 compatible = "st,stm32-thermal";
1266 reg = <0x50028000 0x100>;
1267 interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
1268 clocks = <&rcc TMPSENS>;
1269 clock-names = "pclk";
1270 #thermal-sensor-cells = <0>;
1271 status = "disabled";
1274 hash1: hash@54002000 {
1275 compatible = "st,stm32f756-hash";
1276 reg = <0x54002000 0x400>;
1277 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
1278 clocks = <&rcc HASH1>;
1279 resets = <&rcc HASH1_R>;
1280 dmas = <&mdma1 31 0x10 0x1000A02 0x0 0x0>;
1283 status = "disabled";
1286 rng1: rng@54003000 {
1287 compatible = "st,stm32-rng";
1288 reg = <0x54003000 0x400>;
1289 clocks = <&rcc RNG1_K>;
1290 resets = <&rcc RNG1_R>;
1291 status = "disabled";
1294 mdma1: dma-controller@58000000 {
1295 compatible = "st,stm32h7-mdma";
1296 reg = <0x58000000 0x1000>;
1297 interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
1298 clocks = <&rcc MDMA>;
1299 resets = <&rcc MDMA_R>;
1301 dma-channels = <32>;
1302 dma-requests = <48>;
1305 fmc: nand-controller@58002000 {
1306 compatible = "st,stm32mp15-fmc2";
1307 reg = <0x58002000 0x1000>,
1308 <0x80000000 0x1000>,
1309 <0x88010000 0x1000>,
1310 <0x88020000 0x1000>,
1311 <0x81000000 0x1000>,
1312 <0x89010000 0x1000>,
1313 <0x89020000 0x1000>;
1314 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
1315 dmas = <&mdma1 20 0x10 0x12000a02 0x0 0x0>,
1316 <&mdma1 20 0x10 0x12000a08 0x0 0x0>,
1317 <&mdma1 21 0x10 0x12000a0a 0x0 0x0>;
1318 dma-names = "tx", "rx", "ecc";
1319 clocks = <&rcc FMC_K>;
1320 resets = <&rcc FMC_R>;
1321 status = "disabled";
1324 qspi: spi@58003000 {
1325 compatible = "st,stm32f469-qspi";
1326 reg = <0x58003000 0x1000>, <0x70000000 0x10000000>;
1327 reg-names = "qspi", "qspi_mm";
1328 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
1329 dmas = <&mdma1 22 0x10 0x100002 0x0 0x0>,
1330 <&mdma1 22 0x10 0x100008 0x0 0x0>;
1331 dma-names = "tx", "rx";
1332 clocks = <&rcc QSPI_K>;
1333 resets = <&rcc QSPI_R>;
1334 status = "disabled";
1337 sdmmc1: sdmmc@58005000 {
1338 compatible = "arm,pl18x", "arm,primecell";
1339 arm,primecell-periphid = <0x10153180>;
1340 reg = <0x58005000 0x1000>;
1341 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
1342 interrupt-names = "cmd_irq";
1343 clocks = <&rcc SDMMC1_K>;
1344 clock-names = "apb_pclk";
1345 resets = <&rcc SDMMC1_R>;
1348 max-frequency = <120000000>;
1349 status = "disabled";
1352 sdmmc2: sdmmc@58007000 {
1353 compatible = "arm,pl18x", "arm,primecell";
1354 arm,primecell-periphid = <0x10153180>;
1355 reg = <0x58007000 0x1000>;
1356 interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
1357 interrupt-names = "cmd_irq";
1358 clocks = <&rcc SDMMC2_K>;
1359 clock-names = "apb_pclk";
1360 resets = <&rcc SDMMC2_R>;
1363 max-frequency = <120000000>;
1364 status = "disabled";
1367 crc1: crc@58009000 {
1368 compatible = "st,stm32f7-crc";
1369 reg = <0x58009000 0x400>;
1370 clocks = <&rcc CRC1>;
1371 status = "disabled";
1374 stmmac_axi_config_0: stmmac-axi-config {
1375 snps,wr_osr_lmt = <0x7>;
1376 snps,rd_osr_lmt = <0x7>;
1377 snps,blen = <0 0 0 0 16 8 4>;
1380 ethernet0: ethernet@5800a000 {
1381 compatible = "st,stm32mp1-dwmac", "snps,dwmac-4.20a";
1382 reg = <0x5800a000 0x2000>;
1383 reg-names = "stmmaceth";
1384 interrupts-extended = <&intc GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
1385 interrupt-names = "macirq";
1386 clock-names = "stmmaceth",
1391 clocks = <&rcc ETHMAC>,
1396 st,syscon = <&syscfg 0x4>;
1399 snps,en-tx-lpi-clockgating;
1400 snps,axi-config = <&stmmac_axi_config_0>;
1402 status = "disabled";
1405 usbh_ohci: usbh-ohci@5800c000 {
1406 compatible = "generic-ohci";
1407 reg = <0x5800c000 0x1000>;
1408 clocks = <&rcc USBH>;
1409 resets = <&rcc USBH_R>;
1410 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
1411 status = "disabled";
1414 usbh_ehci: usbh-ehci@5800d000 {
1415 compatible = "generic-ehci";
1416 reg = <0x5800d000 0x1000>;
1417 clocks = <&rcc USBH>;
1418 resets = <&rcc USBH_R>;
1419 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
1420 companion = <&usbh_ohci>;
1421 status = "disabled";
1424 ltdc: display-controller@5a001000 {
1425 compatible = "st,stm32-ltdc";
1426 reg = <0x5a001000 0x400>;
1427 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
1428 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
1429 clocks = <&rcc LTDC_PX>;
1430 clock-names = "lcd";
1431 resets = <&rcc LTDC_R>;
1432 status = "disabled";
1435 #address-cells = <1>;
1440 iwdg2: watchdog@5a002000 {
1441 compatible = "st,stm32mp1-iwdg";
1442 reg = <0x5a002000 0x400>;
1443 clocks = <&rcc IWDG2>, <&rcc CK_LSI>;
1444 clock-names = "pclk", "lsi";
1445 status = "disabled";
1448 usbphyc: usbphyc@5a006000 {
1449 #address-cells = <1>;
1451 compatible = "st,stm32mp1-usbphyc";
1452 reg = <0x5a006000 0x1000>;
1453 clocks = <&rcc USBPHY_K>;
1454 resets = <&rcc USBPHY_R>;
1455 status = "disabled";
1457 usbphyc_port0: usb-phy@0 {
1462 usbphyc_port1: usb-phy@1 {
1468 usart1: serial@5c000000 {
1469 compatible = "st,stm32h7-uart";
1470 reg = <0x5c000000 0x400>;
1471 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
1472 clocks = <&rcc USART1_K>;
1473 status = "disabled";
1476 spi6: spi@5c001000 {
1477 #address-cells = <1>;
1479 compatible = "st,stm32h7-spi";
1480 reg = <0x5c001000 0x400>;
1481 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
1482 clocks = <&rcc SPI6_K>;
1483 resets = <&rcc SPI6_R>;
1484 dmas = <&mdma1 34 0x0 0x40008 0x0 0x0>,
1485 <&mdma1 35 0x0 0x40002 0x0 0x0>;
1486 dma-names = "rx", "tx";
1487 status = "disabled";
1490 i2c4: i2c@5c002000 {
1491 compatible = "st,stm32mp15-i2c";
1492 reg = <0x5c002000 0x400>;
1493 interrupt-names = "event", "error";
1494 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
1495 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
1496 clocks = <&rcc I2C4_K>;
1497 resets = <&rcc I2C4_R>;
1498 #address-cells = <1>;
1500 st,syscfg-fmp = <&syscfg 0x4 0x8>;
1502 status = "disabled";
1506 compatible = "st,stm32mp1-rtc";
1507 reg = <0x5c004000 0x400>;
1508 clocks = <&rcc RTCAPB>, <&rcc RTC>;
1509 clock-names = "pclk", "rtc_ck";
1510 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
1511 status = "disabled";
1514 bsec: efuse@5c005000 {
1515 compatible = "st,stm32mp15-bsec";
1516 reg = <0x5c005000 0x400>;
1517 #address-cells = <1>;
1527 i2c6: i2c@5c009000 {
1528 compatible = "st,stm32mp15-i2c";
1529 reg = <0x5c009000 0x400>;
1530 interrupt-names = "event", "error";
1531 interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
1532 <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
1533 clocks = <&rcc I2C6_K>;
1534 resets = <&rcc I2C6_R>;
1535 #address-cells = <1>;
1537 st,syscfg-fmp = <&syscfg 0x4 0x20>;
1539 status = "disabled";
1543 * Break node order to solve dependency probe issue between
1546 pinctrl: pin-controller@50002000 {
1547 #address-cells = <1>;
1549 compatible = "st,stm32mp157-pinctrl";
1550 ranges = <0 0x50002000 0xa400>;
1551 interrupt-parent = <&exti>;
1552 st,syscfg = <&exti 0x60 0xff>;
1555 gpioa: gpio@50002000 {
1558 interrupt-controller;
1559 #interrupt-cells = <2>;
1561 clocks = <&rcc GPIOA>;
1562 st,bank-name = "GPIOA";
1563 status = "disabled";
1566 gpiob: gpio@50003000 {
1569 interrupt-controller;
1570 #interrupt-cells = <2>;
1571 reg = <0x1000 0x400>;
1572 clocks = <&rcc GPIOB>;
1573 st,bank-name = "GPIOB";
1574 status = "disabled";
1577 gpioc: gpio@50004000 {
1580 interrupt-controller;
1581 #interrupt-cells = <2>;
1582 reg = <0x2000 0x400>;
1583 clocks = <&rcc GPIOC>;
1584 st,bank-name = "GPIOC";
1585 status = "disabled";
1588 gpiod: gpio@50005000 {
1591 interrupt-controller;
1592 #interrupt-cells = <2>;
1593 reg = <0x3000 0x400>;
1594 clocks = <&rcc GPIOD>;
1595 st,bank-name = "GPIOD";
1596 status = "disabled";
1599 gpioe: gpio@50006000 {
1602 interrupt-controller;
1603 #interrupt-cells = <2>;
1604 reg = <0x4000 0x400>;
1605 clocks = <&rcc GPIOE>;
1606 st,bank-name = "GPIOE";
1607 status = "disabled";
1610 gpiof: gpio@50007000 {
1613 interrupt-controller;
1614 #interrupt-cells = <2>;
1615 reg = <0x5000 0x400>;
1616 clocks = <&rcc GPIOF>;
1617 st,bank-name = "GPIOF";
1618 status = "disabled";
1621 gpiog: gpio@50008000 {
1624 interrupt-controller;
1625 #interrupt-cells = <2>;
1626 reg = <0x6000 0x400>;
1627 clocks = <&rcc GPIOG>;
1628 st,bank-name = "GPIOG";
1629 status = "disabled";
1632 gpioh: gpio@50009000 {
1635 interrupt-controller;
1636 #interrupt-cells = <2>;
1637 reg = <0x7000 0x400>;
1638 clocks = <&rcc GPIOH>;
1639 st,bank-name = "GPIOH";
1640 status = "disabled";
1643 gpioi: gpio@5000a000 {
1646 interrupt-controller;
1647 #interrupt-cells = <2>;
1648 reg = <0x8000 0x400>;
1649 clocks = <&rcc GPIOI>;
1650 st,bank-name = "GPIOI";
1651 status = "disabled";
1654 gpioj: gpio@5000b000 {
1657 interrupt-controller;
1658 #interrupt-cells = <2>;
1659 reg = <0x9000 0x400>;
1660 clocks = <&rcc GPIOJ>;
1661 st,bank-name = "GPIOJ";
1662 status = "disabled";
1665 gpiok: gpio@5000c000 {
1668 interrupt-controller;
1669 #interrupt-cells = <2>;
1670 reg = <0xa000 0x400>;
1671 clocks = <&rcc GPIOK>;
1672 st,bank-name = "GPIOK";
1673 status = "disabled";
1677 pinctrl_z: pin-controller-z@54004000 {
1678 #address-cells = <1>;
1680 compatible = "st,stm32mp157-z-pinctrl";
1681 ranges = <0 0x54004000 0x400>;
1683 interrupt-parent = <&exti>;
1684 st,syscfg = <&exti 0x60 0xff>;
1686 gpioz: gpio@54004000 {
1689 interrupt-controller;
1690 #interrupt-cells = <2>;
1692 clocks = <&rcc GPIOZ>;
1693 st,bank-name = "GPIOZ";
1694 st,bank-ioport = <11>;
1695 status = "disabled";
1701 compatible = "st,mlahb", "simple-bus";
1702 #address-cells = <1>;
1705 dma-ranges = <0x00000000 0x38000000 0x10000>,
1706 <0x10000000 0x10000000 0x60000>,
1707 <0x30000000 0x30000000 0x60000>;
1709 m4_rproc: m4@10000000 {
1710 compatible = "st,stm32mp1-m4";
1711 reg = <0x10000000 0x40000>,
1712 <0x30000000 0x40000>,
1713 <0x38000000 0x10000>;
1714 resets = <&rcc MCU_R>;
1715 st,syscfg-holdboot = <&rcc 0x10C 0x1>;
1716 st,syscfg-tz = <&rcc 0x000 0x1>;
1717 st,syscfg-pdds = <&pwr_mcu 0x0 0x1>;
1718 status = "disabled";