1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
3 * Copyright (C) STMicroelectronics 2017 - All Rights Reserved
4 * Author: Ludovic Barre <ludovic.barre@st.com> for STMicroelectronics.
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
17 compatible = "arm,cortex-a7";
23 compatible = "arm,cortex-a7";
30 compatible = "arm,psci";
32 cpu_off = <0x84000002>;
33 cpu_on = <0x84000003>;
50 intc: interrupt-controller@a0021000 {
51 compatible = "arm,cortex-a7-gic";
52 #interrupt-cells = <3>;
54 reg = <0xa0021000 0x1000>,
59 compatible = "arm,armv7-timer";
60 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
61 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
62 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
63 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
64 interrupt-parent = <&intc>;
70 compatible = "fixed-clock";
71 clock-frequency = <24000000>;
74 clk_pll_per: clk-pll-per {
76 compatible = "fixed-clock";
77 clock-frequency = <64000000>;
82 compatible = "fixed-clock";
83 clock-frequency = <64000000>;
88 compatible = "fixed-clock";
89 clock-frequency = <32768>;
94 compatible = "fixed-clock";
95 clock-frequency = <32000>;
100 compatible = "fixed-clock";
101 clock-frequency = <4000000>;
104 clk_pclk1: clk-pclk1 {
106 compatible = "fixed-clock";
107 clock-frequency = <86000000>;
110 clk_pll3_p: clk-pll3_p {
112 compatible = "fixed-clock";
113 clock-frequency = <172000000>;
116 clk_pll2_p: clk-pll2_p {
118 compatible = "fixed-clock";
119 clock-frequency = <264000000>;
124 compatible = "simple-bus";
125 #address-cells = <1>;
127 interrupt-parent = <&intc>;
130 usart2: serial@4000e000 {
131 compatible = "st,stm32h7-uart";
132 reg = <0x4000e000 0x400>;
133 interrupts = <GIC_SPI 38 IRQ_TYPE_NONE>;
134 clocks = <&clk_pclk1>;
138 usart3: serial@4000f000 {
139 compatible = "st,stm32h7-uart";
140 reg = <0x4000f000 0x400>;
141 interrupts = <GIC_SPI 39 IRQ_TYPE_NONE>;
142 clocks = <&clk_pclk1>;
146 uart4: serial@40010000 {
147 compatible = "st,stm32h7-uart";
148 reg = <0x40010000 0x400>;
149 interrupts = <GIC_SPI 52 IRQ_TYPE_NONE>;
150 clocks = <&clk_pclk1>;
154 uart5: serial@40011000 {
155 compatible = "st,stm32h7-uart";
156 reg = <0x40011000 0x400>;
157 interrupts = <GIC_SPI 53 IRQ_TYPE_NONE>;
158 clocks = <&clk_pclk1>;
162 uart7: serial@40018000 {
163 compatible = "st,stm32h7-uart";
164 reg = <0x40018000 0x400>;
165 interrupts = <GIC_SPI 82 IRQ_TYPE_NONE>;
166 clocks = <&clk_pclk1>;
170 uart8: serial@40019000 {
171 compatible = "st,stm32h7-uart";
172 reg = <0x40019000 0x400>;
173 interrupts = <GIC_SPI 83 IRQ_TYPE_NONE>;
174 clocks = <&clk_pclk1>;
178 usart6: serial@44003000 {
179 compatible = "st,stm32h7-uart";
180 reg = <0x44003000 0x400>;
181 interrupts = <GIC_SPI 71 IRQ_TYPE_NONE>;
182 clocks = <&clk_pclk1>;
186 usart1: serial@5c000000 {
187 compatible = "st,stm32h7-uart";
188 reg = <0x5c000000 0x400>;
189 interrupts = <GIC_SPI 37 IRQ_TYPE_NONE>;
190 clocks = <&clk_pclk1>;