1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
3 * Copyright (C) STMicroelectronics 2017 - All Rights Reserved
4 * Author: Ludovic Barre <ludovic.barre@st.com> for STMicroelectronics.
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/clock/stm32mp1-clks.h>
8 #include <dt-bindings/reset/stm32mp1-resets.h>
19 compatible = "arm,cortex-a7";
25 compatible = "arm,cortex-a7";
32 compatible = "arm,psci";
34 cpu_off = <0x84000002>;
35 cpu_on = <0x84000003>;
52 intc: interrupt-controller@a0021000 {
53 compatible = "arm,cortex-a7-gic";
54 #interrupt-cells = <3>;
56 reg = <0xa0021000 0x1000>,
61 compatible = "arm,armv7-timer";
62 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
63 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
64 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
65 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
66 interrupt-parent = <&intc>;
72 compatible = "fixed-clock";
73 clock-frequency = <24000000>;
78 compatible = "fixed-clock";
79 clock-frequency = <64000000>;
84 compatible = "fixed-clock";
85 clock-frequency = <32768>;
90 compatible = "fixed-clock";
91 clock-frequency = <32000>;
96 compatible = "fixed-clock";
97 clock-frequency = <4000000>;
102 compatible = "simple-bus";
103 #address-cells = <1>;
105 interrupt-parent = <&intc>;
108 timers2: timer@40000000 {
109 #address-cells = <1>;
111 compatible = "st,stm32-timers";
112 reg = <0x40000000 0x400>;
113 clocks = <&rcc TIM2_K>;
118 compatible = "st,stm32-pwm";
123 compatible = "st,stm32h7-timer-trigger";
129 timers3: timer@40001000 {
130 #address-cells = <1>;
132 compatible = "st,stm32-timers";
133 reg = <0x40001000 0x400>;
134 clocks = <&rcc TIM3_K>;
139 compatible = "st,stm32-pwm";
144 compatible = "st,stm32h7-timer-trigger";
150 timers4: timer@40002000 {
151 #address-cells = <1>;
153 compatible = "st,stm32-timers";
154 reg = <0x40002000 0x400>;
155 clocks = <&rcc TIM4_K>;
160 compatible = "st,stm32-pwm";
165 compatible = "st,stm32h7-timer-trigger";
171 timers5: timer@40003000 {
172 #address-cells = <1>;
174 compatible = "st,stm32-timers";
175 reg = <0x40003000 0x400>;
176 clocks = <&rcc TIM5_K>;
181 compatible = "st,stm32-pwm";
186 compatible = "st,stm32h7-timer-trigger";
192 timers6: timer@40004000 {
193 #address-cells = <1>;
195 compatible = "st,stm32-timers";
196 reg = <0x40004000 0x400>;
197 clocks = <&rcc TIM6_K>;
202 compatible = "st,stm32h7-timer-trigger";
208 timers7: timer@40005000 {
209 #address-cells = <1>;
211 compatible = "st,stm32-timers";
212 reg = <0x40005000 0x400>;
213 clocks = <&rcc TIM7_K>;
218 compatible = "st,stm32h7-timer-trigger";
224 timers12: timer@40006000 {
225 #address-cells = <1>;
227 compatible = "st,stm32-timers";
228 reg = <0x40006000 0x400>;
229 clocks = <&rcc TIM12_K>;
234 compatible = "st,stm32-pwm";
239 compatible = "st,stm32h7-timer-trigger";
245 timers13: timer@40007000 {
246 #address-cells = <1>;
248 compatible = "st,stm32-timers";
249 reg = <0x40007000 0x400>;
250 clocks = <&rcc TIM13_K>;
255 compatible = "st,stm32-pwm";
260 compatible = "st,stm32h7-timer-trigger";
266 timers14: timer@40008000 {
267 #address-cells = <1>;
269 compatible = "st,stm32-timers";
270 reg = <0x40008000 0x400>;
271 clocks = <&rcc TIM14_K>;
276 compatible = "st,stm32-pwm";
281 compatible = "st,stm32h7-timer-trigger";
287 lptimer1: timer@40009000 {
288 #address-cells = <1>;
290 compatible = "st,stm32-lptimer";
291 reg = <0x40009000 0x400>;
292 clocks = <&rcc LPTIM1_K>;
297 compatible = "st,stm32-pwm-lp";
303 compatible = "st,stm32-lptimer-trigger";
309 compatible = "st,stm32-lptimer-counter";
314 usart2: serial@4000e000 {
315 compatible = "st,stm32h7-uart";
316 reg = <0x4000e000 0x400>;
317 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
318 clocks = <&rcc USART2_K>;
322 usart3: serial@4000f000 {
323 compatible = "st,stm32h7-uart";
324 reg = <0x4000f000 0x400>;
325 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
326 clocks = <&rcc USART3_K>;
330 uart4: serial@40010000 {
331 compatible = "st,stm32h7-uart";
332 reg = <0x40010000 0x400>;
333 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
334 clocks = <&rcc UART4_K>;
338 uart5: serial@40011000 {
339 compatible = "st,stm32h7-uart";
340 reg = <0x40011000 0x400>;
341 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
342 clocks = <&rcc UART5_K>;
347 compatible = "st,stm32f7-i2c";
348 reg = <0x40012000 0x400>;
349 interrupt-names = "event", "error";
350 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
351 <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
352 clocks = <&rcc I2C1_K>;
353 resets = <&rcc I2C1_R>;
354 #address-cells = <1>;
360 compatible = "st,stm32f7-i2c";
361 reg = <0x40013000 0x400>;
362 interrupt-names = "event", "error";
363 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
364 <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
365 clocks = <&rcc I2C2_K>;
366 resets = <&rcc I2C2_R>;
367 #address-cells = <1>;
373 compatible = "st,stm32f7-i2c";
374 reg = <0x40014000 0x400>;
375 interrupt-names = "event", "error";
376 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
377 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
378 clocks = <&rcc I2C3_K>;
379 resets = <&rcc I2C3_R>;
380 #address-cells = <1>;
386 compatible = "st,stm32f7-i2c";
387 reg = <0x40015000 0x400>;
388 interrupt-names = "event", "error";
389 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
390 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
391 clocks = <&rcc I2C5_K>;
392 resets = <&rcc I2C5_R>;
393 #address-cells = <1>;
399 compatible = "st,stm32-cec";
400 reg = <0x40016000 0x400>;
401 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
402 clocks = <&rcc CEC_K>, <&clk_lse>;
403 clock-names = "cec", "hdmi-cec";
408 compatible = "st,stm32h7-dac-core";
409 reg = <0x40017000 0x400>;
410 clocks = <&rcc DAC12>;
411 clock-names = "pclk";
412 #address-cells = <1>;
417 compatible = "st,stm32-dac";
418 #io-channels-cells = <1>;
424 compatible = "st,stm32-dac";
425 #io-channels-cells = <1>;
431 uart7: serial@40018000 {
432 compatible = "st,stm32h7-uart";
433 reg = <0x40018000 0x400>;
434 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
435 clocks = <&rcc UART7_K>;
439 uart8: serial@40019000 {
440 compatible = "st,stm32h7-uart";
441 reg = <0x40019000 0x400>;
442 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
443 clocks = <&rcc UART8_K>;
447 timers1: timer@44000000 {
448 #address-cells = <1>;
450 compatible = "st,stm32-timers";
451 reg = <0x44000000 0x400>;
452 clocks = <&rcc TIM1_K>;
457 compatible = "st,stm32-pwm";
462 compatible = "st,stm32h7-timer-trigger";
468 timers8: timer@44001000 {
469 #address-cells = <1>;
471 compatible = "st,stm32-timers";
472 reg = <0x44001000 0x400>;
473 clocks = <&rcc TIM8_K>;
478 compatible = "st,stm32-pwm";
483 compatible = "st,stm32h7-timer-trigger";
489 usart6: serial@44003000 {
490 compatible = "st,stm32h7-uart";
491 reg = <0x44003000 0x400>;
492 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
493 clocks = <&rcc USART6_K>;
497 timers15: timer@44006000 {
498 #address-cells = <1>;
500 compatible = "st,stm32-timers";
501 reg = <0x44006000 0x400>;
502 clocks = <&rcc TIM15_K>;
507 compatible = "st,stm32-pwm";
512 compatible = "st,stm32h7-timer-trigger";
518 timers16: timer@44007000 {
519 #address-cells = <1>;
521 compatible = "st,stm32-timers";
522 reg = <0x44007000 0x400>;
523 clocks = <&rcc TIM16_K>;
528 compatible = "st,stm32-pwm";
532 compatible = "st,stm32h7-timer-trigger";
538 timers17: timer@44008000 {
539 #address-cells = <1>;
541 compatible = "st,stm32-timers";
542 reg = <0x44008000 0x400>;
543 clocks = <&rcc TIM17_K>;
548 compatible = "st,stm32-pwm";
553 compatible = "st,stm32h7-timer-trigger";
560 compatible = "st,stm32-dma";
561 reg = <0x48000000 0x400>;
562 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
563 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
564 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
565 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
566 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
567 <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
568 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
569 <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
570 clocks = <&rcc DMA1>;
577 compatible = "st,stm32-dma";
578 reg = <0x48001000 0x400>;
579 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
580 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
581 <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
582 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
583 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
584 <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
585 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
586 <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
587 clocks = <&rcc DMA2>;
593 dmamux1: dma-router@48002000 {
594 compatible = "st,stm32h7-dmamux";
595 reg = <0x48002000 0x1c>;
597 dma-requests = <128>;
598 dma-masters = <&dma1 &dma2>;
600 clocks = <&rcc DMAMUX>;
604 compatible = "st,stm32mp1-rcc", "syscon";
605 reg = <0x50000000 0x1000>;
610 exti: interrupt-controller@5000d000 {
611 compatible = "st,stm32mp1-exti", "syscon";
612 interrupt-controller;
613 #interrupt-cells = <2>;
614 reg = <0x5000d000 0x400>;
617 lptimer2: timer@50021000 {
618 #address-cells = <1>;
620 compatible = "st,stm32-lptimer";
621 reg = <0x50021000 0x400>;
622 clocks = <&rcc LPTIM2_K>;
627 compatible = "st,stm32-pwm-lp";
633 compatible = "st,stm32-lptimer-trigger";
639 compatible = "st,stm32-lptimer-counter";
644 lptimer3: timer@50022000 {
645 #address-cells = <1>;
647 compatible = "st,stm32-lptimer";
648 reg = <0x50022000 0x400>;
649 clocks = <&rcc LPTIM3_K>;
654 compatible = "st,stm32-pwm-lp";
660 compatible = "st,stm32-lptimer-trigger";
666 lptimer4: timer@50023000 {
667 compatible = "st,stm32-lptimer";
668 reg = <0x50023000 0x400>;
669 clocks = <&rcc LPTIM4_K>;
674 compatible = "st,stm32-pwm-lp";
680 lptimer5: timer@50024000 {
681 compatible = "st,stm32-lptimer";
682 reg = <0x50024000 0x400>;
683 clocks = <&rcc LPTIM5_K>;
688 compatible = "st,stm32-pwm-lp";
694 vrefbuf: vrefbuf@50025000 {
695 compatible = "st,stm32-vrefbuf";
696 reg = <0x50025000 0x8>;
697 regulator-min-microvolt = <1500000>;
698 regulator-max-microvolt = <2500000>;
699 clocks = <&rcc VREF>;
703 cryp1: cryp@54001000 {
704 compatible = "st,stm32mp1-cryp";
705 reg = <0x54001000 0x400>;
706 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
707 clocks = <&rcc CRYP1>;
708 resets = <&rcc CRYP1_R>;
713 compatible = "st,stm32-rng";
714 reg = <0x54003000 0x400>;
715 clocks = <&rcc RNG1_K>;
716 resets = <&rcc RNG1_R>;
720 mdma1: dma@58000000 {
721 compatible = "st,stm32h7-mdma";
722 reg = <0x58000000 0x1000>;
723 interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
724 clocks = <&rcc MDMA>;
730 qspi: qspi@58003000 {
731 compatible = "st,stm32f469-qspi";
732 reg = <0x58003000 0x1000>, <0x70000000 0x10000000>;
733 reg-names = "qspi", "qspi_mm";
734 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
735 clocks = <&rcc QSPI_K>;
736 resets = <&rcc QSPI_R>;
741 compatible = "st,stm32f7-crc";
742 reg = <0x58009000 0x400>;
743 clocks = <&rcc CRC1>;
747 usbh_ohci: usbh-ohci@5800c000 {
748 compatible = "generic-ohci";
749 reg = <0x5800c000 0x1000>;
750 clocks = <&rcc USBH>;
751 resets = <&rcc USBH_R>;
752 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
756 usbh_ehci: usbh-ehci@5800d000 {
757 compatible = "generic-ehci";
758 reg = <0x5800d000 0x1000>;
759 clocks = <&rcc USBH>;
760 resets = <&rcc USBH_R>;
761 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
762 companion = <&usbh_ohci>;
767 compatible = "st,stm32-dsi";
768 reg = <0x5a000000 0x800>;
769 clocks = <&rcc DSI_K>, <&clk_hse>, <&rcc DSI_PX>;
770 clock-names = "pclk", "ref", "px_clk";
771 resets = <&rcc DSI_R>;
776 ltdc: display-controller@5a001000 {
777 compatible = "st,stm32-ltdc";
778 reg = <0x5a001000 0x400>;
779 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
780 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
781 clocks = <&rcc LTDC_PX>;
783 resets = <&rcc LTDC_R>;
787 usbphyc: usbphyc@5a006000 {
788 #address-cells = <1>;
790 compatible = "st,stm32mp1-usbphyc";
791 reg = <0x5a006000 0x1000>;
792 clocks = <&rcc USBPHY_K>;
793 resets = <&rcc USBPHY_R>;
796 usbphyc_port0: usb-phy@0 {
801 usbphyc_port1: usb-phy@1 {
807 usart1: serial@5c000000 {
808 compatible = "st,stm32h7-uart";
809 reg = <0x5c000000 0x400>;
810 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
811 clocks = <&rcc USART1_K>;
816 compatible = "st,stm32f7-i2c";
817 reg = <0x5c002000 0x400>;
818 interrupt-names = "event", "error";
819 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
820 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
821 clocks = <&rcc I2C4_K>;
822 resets = <&rcc I2C4_R>;
823 #address-cells = <1>;
829 compatible = "st,stm32f7-i2c";
830 reg = <0x5c009000 0x400>;
831 interrupt-names = "event", "error";
832 interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
833 <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
834 clocks = <&rcc I2C6_K>;
835 resets = <&rcc I2C6_R>;
836 #address-cells = <1>;