1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
3 * Copyright (C) STMicroelectronics 2017 - All Rights Reserved
4 * Author: Ludovic Barre <ludovic.barre@st.com> for STMicroelectronics.
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/clock/stm32mp1-clks.h>
8 #include <dt-bindings/reset/stm32mp1-resets.h>
19 compatible = "arm,cortex-a7";
25 compatible = "arm,cortex-a7";
32 compatible = "arm,psci";
34 cpu_off = <0x84000002>;
35 cpu_on = <0x84000003>;
38 intc: interrupt-controller@a0021000 {
39 compatible = "arm,cortex-a7-gic";
40 #interrupt-cells = <3>;
42 reg = <0xa0021000 0x1000>,
47 compatible = "arm,armv7-timer";
48 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
49 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
50 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
51 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
52 interrupt-parent = <&intc>;
58 compatible = "fixed-clock";
59 clock-frequency = <24000000>;
64 compatible = "fixed-clock";
65 clock-frequency = <64000000>;
70 compatible = "fixed-clock";
71 clock-frequency = <32768>;
76 compatible = "fixed-clock";
77 clock-frequency = <32000>;
82 compatible = "fixed-clock";
83 clock-frequency = <4000000>;
88 cpu_thermal: cpu-thermal {
89 polling-delay-passive = <0>;
91 thermal-sensors = <&dts>;
94 cpu_alert1: cpu-alert1 {
95 temperature = <85000>;
101 temperature = <120000>;
113 compatible = "simple-bus";
114 #address-cells = <1>;
116 interrupt-parent = <&intc>;
119 timers2: timer@40000000 {
120 #address-cells = <1>;
122 compatible = "st,stm32-timers";
123 reg = <0x40000000 0x400>;
124 clocks = <&rcc TIM2_K>;
126 dmas = <&dmamux1 18 0x400 0x1>,
127 <&dmamux1 19 0x400 0x1>,
128 <&dmamux1 20 0x400 0x1>,
129 <&dmamux1 21 0x400 0x1>,
130 <&dmamux1 22 0x400 0x1>;
131 dma-names = "ch1", "ch2", "ch3", "ch4", "up";
135 compatible = "st,stm32-pwm";
140 compatible = "st,stm32h7-timer-trigger";
146 timers3: timer@40001000 {
147 #address-cells = <1>;
149 compatible = "st,stm32-timers";
150 reg = <0x40001000 0x400>;
151 clocks = <&rcc TIM3_K>;
153 dmas = <&dmamux1 23 0x400 0x1>,
154 <&dmamux1 24 0x400 0x1>,
155 <&dmamux1 25 0x400 0x1>,
156 <&dmamux1 26 0x400 0x1>,
157 <&dmamux1 27 0x400 0x1>,
158 <&dmamux1 28 0x400 0x1>;
159 dma-names = "ch1", "ch2", "ch3", "ch4", "up", "trig";
163 compatible = "st,stm32-pwm";
168 compatible = "st,stm32h7-timer-trigger";
174 timers4: timer@40002000 {
175 #address-cells = <1>;
177 compatible = "st,stm32-timers";
178 reg = <0x40002000 0x400>;
179 clocks = <&rcc TIM4_K>;
181 dmas = <&dmamux1 29 0x400 0x1>,
182 <&dmamux1 30 0x400 0x1>,
183 <&dmamux1 31 0x400 0x1>,
184 <&dmamux1 32 0x400 0x1>;
185 dma-names = "ch1", "ch2", "ch3", "ch4";
189 compatible = "st,stm32-pwm";
194 compatible = "st,stm32h7-timer-trigger";
200 timers5: timer@40003000 {
201 #address-cells = <1>;
203 compatible = "st,stm32-timers";
204 reg = <0x40003000 0x400>;
205 clocks = <&rcc TIM5_K>;
207 dmas = <&dmamux1 55 0x400 0x1>,
208 <&dmamux1 56 0x400 0x1>,
209 <&dmamux1 57 0x400 0x1>,
210 <&dmamux1 58 0x400 0x1>,
211 <&dmamux1 59 0x400 0x1>,
212 <&dmamux1 60 0x400 0x1>;
213 dma-names = "ch1", "ch2", "ch3", "ch4", "up", "trig";
217 compatible = "st,stm32-pwm";
222 compatible = "st,stm32h7-timer-trigger";
228 timers6: timer@40004000 {
229 #address-cells = <1>;
231 compatible = "st,stm32-timers";
232 reg = <0x40004000 0x400>;
233 clocks = <&rcc TIM6_K>;
235 dmas = <&dmamux1 69 0x400 0x1>;
240 compatible = "st,stm32h7-timer-trigger";
246 timers7: timer@40005000 {
247 #address-cells = <1>;
249 compatible = "st,stm32-timers";
250 reg = <0x40005000 0x400>;
251 clocks = <&rcc TIM7_K>;
253 dmas = <&dmamux1 70 0x400 0x1>;
258 compatible = "st,stm32h7-timer-trigger";
264 timers12: timer@40006000 {
265 #address-cells = <1>;
267 compatible = "st,stm32-timers";
268 reg = <0x40006000 0x400>;
269 clocks = <&rcc TIM12_K>;
274 compatible = "st,stm32-pwm";
279 compatible = "st,stm32h7-timer-trigger";
285 timers13: timer@40007000 {
286 #address-cells = <1>;
288 compatible = "st,stm32-timers";
289 reg = <0x40007000 0x400>;
290 clocks = <&rcc TIM13_K>;
295 compatible = "st,stm32-pwm";
300 compatible = "st,stm32h7-timer-trigger";
306 timers14: timer@40008000 {
307 #address-cells = <1>;
309 compatible = "st,stm32-timers";
310 reg = <0x40008000 0x400>;
311 clocks = <&rcc TIM14_K>;
316 compatible = "st,stm32-pwm";
321 compatible = "st,stm32h7-timer-trigger";
327 lptimer1: timer@40009000 {
328 #address-cells = <1>;
330 compatible = "st,stm32-lptimer";
331 reg = <0x40009000 0x400>;
332 clocks = <&rcc LPTIM1_K>;
337 compatible = "st,stm32-pwm-lp";
343 compatible = "st,stm32-lptimer-trigger";
349 compatible = "st,stm32-lptimer-counter";
355 #address-cells = <1>;
357 compatible = "st,stm32h7-spi";
358 reg = <0x4000b000 0x400>;
359 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
360 clocks = <&rcc SPI2_K>;
361 resets = <&rcc SPI2_R>;
362 dmas = <&dmamux1 39 0x400 0x05>,
363 <&dmamux1 40 0x400 0x05>;
364 dma-names = "rx", "tx";
369 #address-cells = <1>;
371 compatible = "st,stm32h7-spi";
372 reg = <0x4000c000 0x400>;
373 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
374 clocks = <&rcc SPI3_K>;
375 resets = <&rcc SPI3_R>;
376 dmas = <&dmamux1 61 0x400 0x05>,
377 <&dmamux1 62 0x400 0x05>;
378 dma-names = "rx", "tx";
382 usart2: serial@4000e000 {
383 compatible = "st,stm32h7-uart";
384 reg = <0x4000e000 0x400>;
385 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
386 clocks = <&rcc USART2_K>;
390 usart3: serial@4000f000 {
391 compatible = "st,stm32h7-uart";
392 reg = <0x4000f000 0x400>;
393 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
394 clocks = <&rcc USART3_K>;
398 uart4: serial@40010000 {
399 compatible = "st,stm32h7-uart";
400 reg = <0x40010000 0x400>;
401 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
402 clocks = <&rcc UART4_K>;
406 uart5: serial@40011000 {
407 compatible = "st,stm32h7-uart";
408 reg = <0x40011000 0x400>;
409 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
410 clocks = <&rcc UART5_K>;
415 compatible = "st,stm32f7-i2c";
416 reg = <0x40012000 0x400>;
417 interrupt-names = "event", "error";
418 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
419 <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
420 clocks = <&rcc I2C1_K>;
421 resets = <&rcc I2C1_R>;
422 #address-cells = <1>;
428 compatible = "st,stm32f7-i2c";
429 reg = <0x40013000 0x400>;
430 interrupt-names = "event", "error";
431 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
432 <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
433 clocks = <&rcc I2C2_K>;
434 resets = <&rcc I2C2_R>;
435 #address-cells = <1>;
441 compatible = "st,stm32f7-i2c";
442 reg = <0x40014000 0x400>;
443 interrupt-names = "event", "error";
444 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
445 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
446 clocks = <&rcc I2C3_K>;
447 resets = <&rcc I2C3_R>;
448 #address-cells = <1>;
454 compatible = "st,stm32f7-i2c";
455 reg = <0x40015000 0x400>;
456 interrupt-names = "event", "error";
457 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
458 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
459 clocks = <&rcc I2C5_K>;
460 resets = <&rcc I2C5_R>;
461 #address-cells = <1>;
467 compatible = "st,stm32-cec";
468 reg = <0x40016000 0x400>;
469 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
470 clocks = <&rcc CEC_K>, <&clk_lse>;
471 clock-names = "cec", "hdmi-cec";
476 compatible = "st,stm32h7-dac-core";
477 reg = <0x40017000 0x400>;
478 clocks = <&rcc DAC12>;
479 clock-names = "pclk";
480 #address-cells = <1>;
485 compatible = "st,stm32-dac";
486 #io-channels-cells = <1>;
492 compatible = "st,stm32-dac";
493 #io-channels-cells = <1>;
499 uart7: serial@40018000 {
500 compatible = "st,stm32h7-uart";
501 reg = <0x40018000 0x400>;
502 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
503 clocks = <&rcc UART7_K>;
507 uart8: serial@40019000 {
508 compatible = "st,stm32h7-uart";
509 reg = <0x40019000 0x400>;
510 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
511 clocks = <&rcc UART8_K>;
515 timers1: timer@44000000 {
516 #address-cells = <1>;
518 compatible = "st,stm32-timers";
519 reg = <0x44000000 0x400>;
520 clocks = <&rcc TIM1_K>;
522 dmas = <&dmamux1 11 0x400 0x1>,
523 <&dmamux1 12 0x400 0x1>,
524 <&dmamux1 13 0x400 0x1>,
525 <&dmamux1 14 0x400 0x1>,
526 <&dmamux1 15 0x400 0x1>,
527 <&dmamux1 16 0x400 0x1>,
528 <&dmamux1 17 0x400 0x1>;
529 dma-names = "ch1", "ch2", "ch3", "ch4",
534 compatible = "st,stm32-pwm";
539 compatible = "st,stm32h7-timer-trigger";
545 timers8: timer@44001000 {
546 #address-cells = <1>;
548 compatible = "st,stm32-timers";
549 reg = <0x44001000 0x400>;
550 clocks = <&rcc TIM8_K>;
552 dmas = <&dmamux1 47 0x400 0x1>,
553 <&dmamux1 48 0x400 0x1>,
554 <&dmamux1 49 0x400 0x1>,
555 <&dmamux1 50 0x400 0x1>,
556 <&dmamux1 51 0x400 0x1>,
557 <&dmamux1 52 0x400 0x1>,
558 <&dmamux1 53 0x400 0x1>;
559 dma-names = "ch1", "ch2", "ch3", "ch4",
564 compatible = "st,stm32-pwm";
569 compatible = "st,stm32h7-timer-trigger";
575 usart6: serial@44003000 {
576 compatible = "st,stm32h7-uart";
577 reg = <0x44003000 0x400>;
578 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
579 clocks = <&rcc USART6_K>;
584 #address-cells = <1>;
586 compatible = "st,stm32h7-spi";
587 reg = <0x44004000 0x400>;
588 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
589 clocks = <&rcc SPI1_K>;
590 resets = <&rcc SPI1_R>;
591 dmas = <&dmamux1 37 0x400 0x05>,
592 <&dmamux1 38 0x400 0x05>;
593 dma-names = "rx", "tx";
598 #address-cells = <1>;
600 compatible = "st,stm32h7-spi";
601 reg = <0x44005000 0x400>;
602 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
603 clocks = <&rcc SPI4_K>;
604 resets = <&rcc SPI4_R>;
605 dmas = <&dmamux1 83 0x400 0x05>,
606 <&dmamux1 84 0x400 0x05>;
607 dma-names = "rx", "tx";
611 timers15: timer@44006000 {
612 #address-cells = <1>;
614 compatible = "st,stm32-timers";
615 reg = <0x44006000 0x400>;
616 clocks = <&rcc TIM15_K>;
618 dmas = <&dmamux1 105 0x400 0x1>,
619 <&dmamux1 106 0x400 0x1>,
620 <&dmamux1 107 0x400 0x1>,
621 <&dmamux1 108 0x400 0x1>;
622 dma-names = "ch1", "up", "trig", "com";
626 compatible = "st,stm32-pwm";
631 compatible = "st,stm32h7-timer-trigger";
637 timers16: timer@44007000 {
638 #address-cells = <1>;
640 compatible = "st,stm32-timers";
641 reg = <0x44007000 0x400>;
642 clocks = <&rcc TIM16_K>;
644 dmas = <&dmamux1 109 0x400 0x1>,
645 <&dmamux1 110 0x400 0x1>;
646 dma-names = "ch1", "up";
650 compatible = "st,stm32-pwm";
654 compatible = "st,stm32h7-timer-trigger";
660 timers17: timer@44008000 {
661 #address-cells = <1>;
663 compatible = "st,stm32-timers";
664 reg = <0x44008000 0x400>;
665 clocks = <&rcc TIM17_K>;
667 dmas = <&dmamux1 111 0x400 0x1>,
668 <&dmamux1 112 0x400 0x1>;
669 dma-names = "ch1", "up";
673 compatible = "st,stm32-pwm";
678 compatible = "st,stm32h7-timer-trigger";
685 #address-cells = <1>;
687 compatible = "st,stm32h7-spi";
688 reg = <0x44009000 0x400>;
689 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
690 clocks = <&rcc SPI5_K>;
691 resets = <&rcc SPI5_R>;
692 dmas = <&dmamux1 85 0x400 0x05>,
693 <&dmamux1 86 0x400 0x05>;
694 dma-names = "rx", "tx";
698 dfsdm: dfsdm@4400d000 {
699 compatible = "st,stm32mp1-dfsdm";
700 reg = <0x4400d000 0x800>;
701 clocks = <&rcc DFSDM_K>;
702 clock-names = "dfsdm";
703 #address-cells = <1>;
708 compatible = "st,stm32-dfsdm-adc";
709 #io-channel-cells = <1>;
711 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
712 dmas = <&dmamux1 101 0x400 0x01>;
718 compatible = "st,stm32-dfsdm-adc";
719 #io-channel-cells = <1>;
721 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
722 dmas = <&dmamux1 102 0x400 0x01>;
728 compatible = "st,stm32-dfsdm-adc";
729 #io-channel-cells = <1>;
731 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
732 dmas = <&dmamux1 103 0x400 0x01>;
738 compatible = "st,stm32-dfsdm-adc";
739 #io-channel-cells = <1>;
741 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
742 dmas = <&dmamux1 104 0x400 0x01>;
748 compatible = "st,stm32-dfsdm-adc";
749 #io-channel-cells = <1>;
751 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
752 dmas = <&dmamux1 91 0x400 0x01>;
758 compatible = "st,stm32-dfsdm-adc";
759 #io-channel-cells = <1>;
761 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
762 dmas = <&dmamux1 92 0x400 0x01>;
768 m_can1: can@4400e000 {
769 compatible = "bosch,m_can";
770 reg = <0x4400e000 0x400>, <0x44011000 0x1400>;
771 reg-names = "m_can", "message_ram";
772 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
773 <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
774 interrupt-names = "int0", "int1";
775 clocks = <&rcc CK_HSE>, <&rcc FDCAN_K>;
776 clock-names = "hclk", "cclk";
777 bosch,mram-cfg = <0x1400 0 0 32 0 0 2 2>;
781 m_can2: can@4400f000 {
782 compatible = "bosch,m_can";
783 reg = <0x4400f000 0x400>, <0x44011000 0x2800>;
784 reg-names = "m_can", "message_ram";
785 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
786 <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
787 interrupt-names = "int0", "int1";
788 clocks = <&rcc CK_HSE>, <&rcc FDCAN_K>;
789 clock-names = "hclk", "cclk";
790 bosch,mram-cfg = <0x0 0 0 32 0 0 2 2>;
795 compatible = "st,stm32-dma";
796 reg = <0x48000000 0x400>;
797 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
798 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
799 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
800 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
801 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
802 <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
803 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
804 <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
805 clocks = <&rcc DMA1>;
812 compatible = "st,stm32-dma";
813 reg = <0x48001000 0x400>;
814 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
815 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
816 <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
817 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
818 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
819 <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
820 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
821 <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
822 clocks = <&rcc DMA2>;
828 dmamux1: dma-router@48002000 {
829 compatible = "st,stm32h7-dmamux";
830 reg = <0x48002000 0x1c>;
832 dma-requests = <128>;
833 dma-masters = <&dma1 &dma2>;
835 clocks = <&rcc DMAMUX>;
839 compatible = "st,stm32mp1-adc-core";
840 reg = <0x48003000 0x400>;
841 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
842 <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
843 clocks = <&rcc ADC12>, <&rcc ADC12_K>;
844 clock-names = "bus", "adc";
845 interrupt-controller;
846 #interrupt-cells = <1>;
847 #address-cells = <1>;
852 compatible = "st,stm32mp1-adc";
853 #io-channel-cells = <1>;
855 interrupt-parent = <&adc>;
857 dmas = <&dmamux1 9 0x400 0x01>;
863 compatible = "st,stm32mp1-adc";
864 #io-channel-cells = <1>;
866 interrupt-parent = <&adc>;
868 dmas = <&dmamux1 10 0x400 0x01>;
874 usbotg_hs: usb-otg@49000000 {
875 compatible = "snps,dwc2";
876 reg = <0x49000000 0x10000>;
877 clocks = <&rcc USBO_K>;
879 resets = <&rcc USBO_R>;
880 reset-names = "dwc2";
881 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
882 g-rx-fifo-size = <256>;
883 g-np-tx-fifo-size = <32>;
884 g-tx-fifo-size = <128 128 64 64 64 64 32 32>;
890 compatible = "st,stm32mp1-rcc", "syscon";
891 reg = <0x50000000 0x1000>;
896 exti: interrupt-controller@5000d000 {
897 compatible = "st,stm32mp1-exti", "syscon";
898 interrupt-controller;
899 #interrupt-cells = <2>;
900 reg = <0x5000d000 0x400>;
903 syscfg: syscon@50020000 {
904 compatible = "st,stm32mp157-syscfg", "syscon";
905 reg = <0x50020000 0x400>;
908 lptimer2: timer@50021000 {
909 #address-cells = <1>;
911 compatible = "st,stm32-lptimer";
912 reg = <0x50021000 0x400>;
913 clocks = <&rcc LPTIM2_K>;
918 compatible = "st,stm32-pwm-lp";
924 compatible = "st,stm32-lptimer-trigger";
930 compatible = "st,stm32-lptimer-counter";
935 lptimer3: timer@50022000 {
936 #address-cells = <1>;
938 compatible = "st,stm32-lptimer";
939 reg = <0x50022000 0x400>;
940 clocks = <&rcc LPTIM3_K>;
945 compatible = "st,stm32-pwm-lp";
951 compatible = "st,stm32-lptimer-trigger";
957 lptimer4: timer@50023000 {
958 compatible = "st,stm32-lptimer";
959 reg = <0x50023000 0x400>;
960 clocks = <&rcc LPTIM4_K>;
965 compatible = "st,stm32-pwm-lp";
971 lptimer5: timer@50024000 {
972 compatible = "st,stm32-lptimer";
973 reg = <0x50024000 0x400>;
974 clocks = <&rcc LPTIM5_K>;
979 compatible = "st,stm32-pwm-lp";
985 vrefbuf: vrefbuf@50025000 {
986 compatible = "st,stm32-vrefbuf";
987 reg = <0x50025000 0x8>;
988 regulator-min-microvolt = <1500000>;
989 regulator-max-microvolt = <2500000>;
990 clocks = <&rcc VREF>;
994 dts: thermal@50028000 {
995 compatible = "st,stm32-thermal";
996 reg = <0x50028000 0x100>;
997 interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
998 clocks = <&rcc TMPSENS>;
999 clock-names = "pclk";
1000 #thermal-sensor-cells = <0>;
1001 status = "disabled";
1004 cryp1: cryp@54001000 {
1005 compatible = "st,stm32mp1-cryp";
1006 reg = <0x54001000 0x400>;
1007 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
1008 clocks = <&rcc CRYP1>;
1009 resets = <&rcc CRYP1_R>;
1010 status = "disabled";
1013 hash1: hash@54002000 {
1014 compatible = "st,stm32f756-hash";
1015 reg = <0x54002000 0x400>;
1016 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
1017 clocks = <&rcc HASH1>;
1018 resets = <&rcc HASH1_R>;
1019 dmas = <&mdma1 31 0x10 0x1000A02 0x0 0x0>;
1022 status = "disabled";
1025 rng1: rng@54003000 {
1026 compatible = "st,stm32-rng";
1027 reg = <0x54003000 0x400>;
1028 clocks = <&rcc RNG1_K>;
1029 resets = <&rcc RNG1_R>;
1030 status = "disabled";
1033 mdma1: dma@58000000 {
1034 compatible = "st,stm32h7-mdma";
1035 reg = <0x58000000 0x1000>;
1036 interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
1037 clocks = <&rcc MDMA>;
1039 dma-channels = <32>;
1040 dma-requests = <48>;
1043 qspi: spi@58003000 {
1044 compatible = "st,stm32f469-qspi";
1045 reg = <0x58003000 0x1000>, <0x70000000 0x10000000>;
1046 reg-names = "qspi", "qspi_mm";
1047 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
1048 clocks = <&rcc QSPI_K>;
1049 resets = <&rcc QSPI_R>;
1050 status = "disabled";
1053 crc1: crc@58009000 {
1054 compatible = "st,stm32f7-crc";
1055 reg = <0x58009000 0x400>;
1056 clocks = <&rcc CRC1>;
1057 status = "disabled";
1060 stmmac_axi_config_0: stmmac-axi-config {
1061 snps,wr_osr_lmt = <0x7>;
1062 snps,rd_osr_lmt = <0x7>;
1063 snps,blen = <0 0 0 0 16 8 4>;
1066 ethernet0: ethernet@5800a000 {
1067 compatible = "st,stm32mp1-dwmac", "snps,dwmac-4.20a";
1068 reg = <0x5800a000 0x2000>;
1069 reg-names = "stmmaceth";
1070 interrupts-extended = <&intc GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
1071 interrupt-names = "macirq";
1072 clock-names = "stmmaceth",
1077 clocks = <&rcc ETHMAC>,
1082 st,syscon = <&syscfg 0x4>;
1085 snps,axi-config = <&stmmac_axi_config_0>;
1087 status = "disabled";
1090 usbh_ohci: usbh-ohci@5800c000 {
1091 compatible = "generic-ohci";
1092 reg = <0x5800c000 0x1000>;
1093 clocks = <&rcc USBH>;
1094 resets = <&rcc USBH_R>;
1095 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
1096 status = "disabled";
1099 usbh_ehci: usbh-ehci@5800d000 {
1100 compatible = "generic-ehci";
1101 reg = <0x5800d000 0x1000>;
1102 clocks = <&rcc USBH>;
1103 resets = <&rcc USBH_R>;
1104 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
1105 companion = <&usbh_ohci>;
1106 status = "disabled";
1110 compatible = "st,stm32-dsi";
1111 reg = <0x5a000000 0x800>;
1112 clocks = <&rcc DSI_K>, <&clk_hse>, <&rcc DSI_PX>;
1113 clock-names = "pclk", "ref", "px_clk";
1114 resets = <&rcc DSI_R>;
1115 reset-names = "apb";
1116 status = "disabled";
1119 ltdc: display-controller@5a001000 {
1120 compatible = "st,stm32-ltdc";
1121 reg = <0x5a001000 0x400>;
1122 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
1123 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
1124 clocks = <&rcc LTDC_PX>;
1125 clock-names = "lcd";
1126 resets = <&rcc LTDC_R>;
1127 status = "disabled";
1130 iwdg2: watchdog@5a002000 {
1131 compatible = "st,stm32mp1-iwdg";
1132 reg = <0x5a002000 0x400>;
1133 clocks = <&rcc IWDG2>, <&rcc CK_LSI>;
1134 clock-names = "pclk", "lsi";
1135 status = "disabled";
1138 usbphyc: usbphyc@5a006000 {
1139 #address-cells = <1>;
1141 compatible = "st,stm32mp1-usbphyc";
1142 reg = <0x5a006000 0x1000>;
1143 clocks = <&rcc USBPHY_K>;
1144 resets = <&rcc USBPHY_R>;
1145 status = "disabled";
1147 usbphyc_port0: usb-phy@0 {
1152 usbphyc_port1: usb-phy@1 {
1158 usart1: serial@5c000000 {
1159 compatible = "st,stm32h7-uart";
1160 reg = <0x5c000000 0x400>;
1161 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
1162 clocks = <&rcc USART1_K>;
1163 status = "disabled";
1166 spi6: spi@5c001000 {
1167 #address-cells = <1>;
1169 compatible = "st,stm32h7-spi";
1170 reg = <0x5c001000 0x400>;
1171 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
1172 clocks = <&rcc SPI6_K>;
1173 resets = <&rcc SPI6_R>;
1174 dmas = <&mdma1 34 0x0 0x40008 0x0 0x0>,
1175 <&mdma1 35 0x0 0x40002 0x0 0x0>;
1176 dma-names = "rx", "tx";
1177 status = "disabled";
1180 i2c4: i2c@5c002000 {
1181 compatible = "st,stm32f7-i2c";
1182 reg = <0x5c002000 0x400>;
1183 interrupt-names = "event", "error";
1184 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
1185 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
1186 clocks = <&rcc I2C4_K>;
1187 resets = <&rcc I2C4_R>;
1188 #address-cells = <1>;
1190 status = "disabled";
1194 compatible = "st,stm32mp1-rtc";
1195 reg = <0x5c004000 0x400>;
1196 clocks = <&rcc RTCAPB>, <&rcc RTC>;
1197 clock-names = "pclk", "rtc_ck";
1198 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
1199 status = "disabled";
1202 i2c6: i2c@5c009000 {
1203 compatible = "st,stm32f7-i2c";
1204 reg = <0x5c009000 0x400>;
1205 interrupt-names = "event", "error";
1206 interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
1207 <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
1208 clocks = <&rcc I2C6_K>;
1209 resets = <&rcc I2C6_R>;
1210 #address-cells = <1>;
1212 status = "disabled";