2 * Copyright 2013 Maxime Ripard
4 * Maxime Ripard <maxime.ripard@free-electrons.com>
6 * This file is dual-licensed: you can use it either under the terms
7 * of the GPL or the X11 license, at your option. Note that this dual
8 * licensing only applies to this file, and not this project as a
11 * a) This file is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of the
14 * License, or (at your option) any later version.
16 * This file is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
23 * b) Permission is hereby granted, free of charge, to any person
24 * obtaining a copy of this software and associated documentation
25 * files (the "Software"), to deal in the Software without
26 * restriction, including without limitation the rights to use,
27 * copy, modify, merge, publish, distribute, sublicense, and/or
28 * sell copies of the Software, and to permit persons to whom the
29 * Software is furnished to do so, subject to the following
32 * The above copyright notice and this permission notice shall be
33 * included in all copies or substantial portions of the Software.
35 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
36 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
37 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
38 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
39 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
40 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
41 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
42 * OTHER DEALINGS IN THE SOFTWARE.
45 #include <dt-bindings/interrupt-controller/arm-gic.h>
46 #include <dt-bindings/thermal/thermal.h>
47 #include <dt-bindings/dma/sun4i-a10.h>
48 #include <dt-bindings/clock/sun7i-a20-ccu.h>
49 #include <dt-bindings/reset/sun4i-a10-ccu.h>
52 interrupt-parent = <&gic>;
65 framebuffer-lcd0-hdmi {
66 compatible = "allwinner,simple-framebuffer",
68 allwinner,pipeline = "de_be0-lcd0-hdmi";
69 clocks = <&ccu CLK_AHB_LCD0>, <&ccu CLK_AHB_HDMI0>,
70 <&ccu CLK_AHB_DE_BE0>, <&ccu CLK_DE_BE0>,
71 <&ccu CLK_TCON0_CH1>, <&ccu CLK_DRAM_DE_BE0>,
77 compatible = "allwinner,simple-framebuffer",
79 allwinner,pipeline = "de_be0-lcd0";
80 clocks = <&ccu CLK_AHB_LCD0>, <&ccu CLK_AHB_DE_BE0>,
81 <&ccu CLK_DE_BE0>, <&ccu CLK_TCON0_CH0>,
82 <&ccu CLK_DRAM_DE_BE0>;
86 framebuffer-lcd0-tve0 {
87 compatible = "allwinner,simple-framebuffer",
89 allwinner,pipeline = "de_be0-lcd0-tve0";
90 clocks = <&ccu CLK_AHB_TVE0>, <&ccu CLK_AHB_LCD0>,
91 <&ccu CLK_AHB_DE_BE0>,
92 <&ccu CLK_DE_BE0>, <&ccu CLK_TCON0_CH1>,
93 <&ccu CLK_DRAM_TVE0>, <&ccu CLK_DRAM_DE_BE0>;
103 compatible = "arm,cortex-a7";
106 clocks = <&ccu CLK_CPU>;
107 clock-latency = <244144>; /* 8 32k periods */
118 #cooling-cells = <2>;
122 compatible = "arm,cortex-a7";
125 clocks = <&ccu CLK_CPU>;
126 clock-latency = <244144>; /* 8 32k periods */
137 #cooling-cells = <2>;
144 polling-delay-passive = <250>;
145 polling-delay = <1000>;
146 thermal-sensors = <&rtp>;
150 trip = <&cpu_alert0>;
151 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
152 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
157 cpu_alert0: cpu_alert0 {
159 temperature = <75000>;
166 temperature = <100000>;
175 #address-cells = <1>;
179 /* Address must be kept in the lower 256 MiBs of DRAM for VE. */
181 compatible = "shared-dma-pool";
183 alloc-ranges = <0x4a000000 0x6000000>;
190 compatible = "arm,armv7-timer";
191 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
192 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
193 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
194 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
198 compatible = "arm,cortex-a7-pmu";
199 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
200 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
204 #address-cells = <1>;
210 compatible = "fixed-clock";
211 clock-frequency = <24000000>;
212 clock-output-names = "osc24M";
217 compatible = "fixed-clock";
218 clock-frequency = <32768>;
219 clock-output-names = "osc32k";
223 * The following two are dummy clocks, placeholders
224 * used in the gmac_tx clock. The gmac driver will
225 * choose one parent depending on the PHY interface
226 * mode, using clk_set_rate auto-reparenting.
228 * The actual TX clock rate is not controlled by the
231 mii_phy_tx_clk: clk-mii-phy-tx {
233 compatible = "fixed-clock";
234 clock-frequency = <25000000>;
235 clock-output-names = "mii_phy_tx";
238 gmac_int_tx_clk: clk-gmac-int-tx {
240 compatible = "fixed-clock";
241 clock-frequency = <125000000>;
242 clock-output-names = "gmac_int_tx";
245 gmac_tx_clk: clk@1c20164 {
247 compatible = "allwinner,sun7i-a20-gmac-clk";
248 reg = <0x01c20164 0x4>;
249 clocks = <&mii_phy_tx_clk>, <&gmac_int_tx_clk>;
250 clock-output-names = "gmac_tx";
256 compatible = "allwinner,sun7i-a20-display-engine";
257 allwinner,pipelines = <&fe0>, <&fe1>;
262 compatible = "simple-bus";
263 #address-cells = <1>;
267 system-control@1c00000 {
268 compatible = "allwinner,sun7i-a20-system-control",
269 "allwinner,sun4i-a10-system-control";
270 reg = <0x01c00000 0x30>;
271 #address-cells = <1>;
276 compatible = "mmio-sram";
277 reg = <0x00000000 0xc000>;
278 #address-cells = <1>;
280 ranges = <0 0x00000000 0xc000>;
282 emac_sram: sram-section@8000 {
283 compatible = "allwinner,sun7i-a20-sram-a3-a4",
284 "allwinner,sun4i-a10-sram-a3-a4";
285 reg = <0x8000 0x4000>;
291 compatible = "mmio-sram";
292 reg = <0x00010000 0x1000>;
293 #address-cells = <1>;
295 ranges = <0 0x00010000 0x1000>;
297 otg_sram: sram-section@0 {
298 compatible = "allwinner,sun7i-a20-sram-d",
299 "allwinner,sun4i-a10-sram-d";
300 reg = <0x0000 0x1000>;
305 sram_c: sram@1d00000 {
306 compatible = "mmio-sram";
307 reg = <0x01d00000 0xd0000>;
308 #address-cells = <1>;
310 ranges = <0 0x01d00000 0xd0000>;
312 ve_sram: sram-section@0 {
313 compatible = "allwinner,sun7i-a20-sram-c1",
314 "allwinner,sun4i-a10-sram-c1";
315 reg = <0x000000 0x80000>;
320 nmi_intc: interrupt-controller@1c00030 {
321 compatible = "allwinner,sun7i-a20-sc-nmi";
322 interrupt-controller;
323 #interrupt-cells = <2>;
324 reg = <0x01c00030 0x0c>;
325 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
328 dma: dma-controller@1c02000 {
329 compatible = "allwinner,sun4i-a10-dma";
330 reg = <0x01c02000 0x1000>;
331 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
332 clocks = <&ccu CLK_AHB_DMA>;
336 nfc: nand-controller@1c03000 {
337 compatible = "allwinner,sun4i-a10-nand";
338 reg = <0x01c03000 0x1000>;
339 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
340 clocks = <&ccu CLK_AHB_NAND>, <&ccu CLK_NAND>;
341 clock-names = "ahb", "mod";
342 dmas = <&dma SUN4I_DMA_DEDICATED 3>;
345 #address-cells = <1>;
350 compatible = "allwinner,sun4i-a10-spi";
351 reg = <0x01c05000 0x1000>;
352 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
353 clocks = <&ccu CLK_AHB_SPI0>, <&ccu CLK_SPI0>;
354 clock-names = "ahb", "mod";
355 dmas = <&dma SUN4I_DMA_DEDICATED 27>,
356 <&dma SUN4I_DMA_DEDICATED 26>;
357 dma-names = "rx", "tx";
359 #address-cells = <1>;
365 compatible = "allwinner,sun4i-a10-spi";
366 reg = <0x01c06000 0x1000>;
367 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
368 clocks = <&ccu CLK_AHB_SPI1>, <&ccu CLK_SPI1>;
369 clock-names = "ahb", "mod";
370 dmas = <&dma SUN4I_DMA_DEDICATED 9>,
371 <&dma SUN4I_DMA_DEDICATED 8>;
372 dma-names = "rx", "tx";
374 #address-cells = <1>;
380 compatible = "allwinner,sun7i-a20-csi0";
381 reg = <0x01c09000 0x1000>;
382 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
383 clocks = <&ccu CLK_AHB_CSI0>, <&ccu CLK_CSI_SCLK>, <&ccu CLK_DRAM_CSI0>;
384 clock-names = "bus", "isp", "ram";
385 resets = <&ccu RST_CSI0>;
389 emac: ethernet@1c0b000 {
390 compatible = "allwinner,sun4i-a10-emac";
391 reg = <0x01c0b000 0x1000>;
392 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
393 clocks = <&ccu CLK_AHB_EMAC>;
394 allwinner,sram = <&emac_sram 1>;
399 compatible = "allwinner,sun4i-a10-mdio";
400 reg = <0x01c0b080 0x14>;
402 #address-cells = <1>;
406 tcon0: lcd-controller@1c0c000 {
407 compatible = "allwinner,sun7i-a20-tcon";
408 reg = <0x01c0c000 0x1000>;
409 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
410 resets = <&ccu RST_TCON0>;
412 clocks = <&ccu CLK_AHB_LCD0>,
413 <&ccu CLK_TCON0_CH0>,
414 <&ccu CLK_TCON0_CH1>;
418 clock-output-names = "tcon0-pixel-clock";
420 dmas = <&dma SUN4I_DMA_DEDICATED 14>;
423 #address-cells = <1>;
427 #address-cells = <1>;
431 tcon0_in_be0: endpoint@0 {
433 remote-endpoint = <&be0_out_tcon0>;
436 tcon0_in_be1: endpoint@1 {
438 remote-endpoint = <&be1_out_tcon0>;
443 #address-cells = <1>;
447 tcon0_out_hdmi: endpoint@1 {
449 remote-endpoint = <&hdmi_in_tcon0>;
450 allwinner,tcon-channel = <1>;
456 tcon1: lcd-controller@1c0d000 {
457 compatible = "allwinner,sun7i-a20-tcon";
458 reg = <0x01c0d000 0x1000>;
459 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
460 resets = <&ccu RST_TCON1>;
462 clocks = <&ccu CLK_AHB_LCD1>,
463 <&ccu CLK_TCON1_CH0>,
464 <&ccu CLK_TCON1_CH1>;
468 clock-output-names = "tcon1-pixel-clock";
470 dmas = <&dma SUN4I_DMA_DEDICATED 15>;
473 #address-cells = <1>;
477 #address-cells = <1>;
481 tcon1_in_be0: endpoint@0 {
483 remote-endpoint = <&be0_out_tcon1>;
486 tcon1_in_be1: endpoint@1 {
488 remote-endpoint = <&be1_out_tcon1>;
493 #address-cells = <1>;
497 tcon1_out_hdmi: endpoint@1 {
499 remote-endpoint = <&hdmi_in_tcon1>;
500 allwinner,tcon-channel = <1>;
506 video-codec@1c0e000 {
507 compatible = "allwinner,sun7i-a20-video-engine";
508 reg = <0x01c0e000 0x1000>;
509 clocks = <&ccu CLK_AHB_VE>, <&ccu CLK_VE>,
511 clock-names = "ahb", "mod", "ram";
512 resets = <&ccu RST_VE>;
513 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
514 allwinner,sram = <&ve_sram 1>;
518 compatible = "allwinner,sun7i-a20-mmc";
519 reg = <0x01c0f000 0x1000>;
520 clocks = <&ccu CLK_AHB_MMC0>,
522 <&ccu CLK_MMC0_OUTPUT>,
523 <&ccu CLK_MMC0_SAMPLE>;
528 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
529 pinctrl-names = "default";
530 pinctrl-0 = <&mmc0_pins>;
532 #address-cells = <1>;
537 compatible = "allwinner,sun7i-a20-mmc";
538 reg = <0x01c10000 0x1000>;
539 clocks = <&ccu CLK_AHB_MMC1>,
541 <&ccu CLK_MMC1_OUTPUT>,
542 <&ccu CLK_MMC1_SAMPLE>;
547 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
549 #address-cells = <1>;
554 compatible = "allwinner,sun7i-a20-mmc";
555 reg = <0x01c11000 0x1000>;
556 clocks = <&ccu CLK_AHB_MMC2>,
558 <&ccu CLK_MMC2_OUTPUT>,
559 <&ccu CLK_MMC2_SAMPLE>;
564 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
565 pinctrl-names = "default";
566 pinctrl-0 = <&mmc2_pins>;
568 #address-cells = <1>;
573 compatible = "allwinner,sun7i-a20-mmc";
574 reg = <0x01c12000 0x1000>;
575 clocks = <&ccu CLK_AHB_MMC3>,
577 <&ccu CLK_MMC3_OUTPUT>,
578 <&ccu CLK_MMC3_SAMPLE>;
583 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
584 pinctrl-names = "default";
585 pinctrl-0 = <&mmc3_pins>;
587 #address-cells = <1>;
591 usb_otg: usb@1c13000 {
592 compatible = "allwinner,sun4i-a10-musb";
593 reg = <0x01c13000 0x0400>;
594 clocks = <&ccu CLK_AHB_OTG>;
595 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
596 interrupt-names = "mc";
599 extcon = <&usbphy 0>;
600 allwinner,sram = <&otg_sram 1>;
605 usbphy: phy@1c13400 {
607 compatible = "allwinner,sun7i-a20-usb-phy";
608 reg = <0x01c13400 0x10>, <0x01c14800 0x4>, <0x01c1c800 0x4>;
609 reg-names = "phy_ctrl", "pmu1", "pmu2";
610 clocks = <&ccu CLK_USB_PHY>;
611 clock-names = "usb_phy";
612 resets = <&ccu RST_USB_PHY0>,
615 reset-names = "usb0_reset", "usb1_reset", "usb2_reset";
620 compatible = "allwinner,sun7i-a20-ehci", "generic-ehci";
621 reg = <0x01c14000 0x100>;
622 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
623 clocks = <&ccu CLK_AHB_EHCI0>;
630 compatible = "allwinner,sun7i-a20-ohci", "generic-ohci";
631 reg = <0x01c14400 0x100>;
632 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
633 clocks = <&ccu CLK_USB_OHCI0>, <&ccu CLK_AHB_OHCI0>;
639 crypto: crypto-engine@1c15000 {
640 compatible = "allwinner,sun7i-a20-crypto",
641 "allwinner,sun4i-a10-crypto";
642 reg = <0x01c15000 0x1000>;
643 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
644 clocks = <&ccu CLK_AHB_SS>, <&ccu CLK_SS>;
645 clock-names = "ahb", "mod";
649 compatible = "allwinner,sun7i-a20-hdmi",
650 "allwinner,sun5i-a10s-hdmi";
651 reg = <0x01c16000 0x1000>;
652 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
653 clocks = <&ccu CLK_AHB_HDMI0>, <&ccu CLK_HDMI>,
654 <&ccu CLK_PLL_VIDEO0_2X>,
655 <&ccu CLK_PLL_VIDEO1_2X>;
656 clock-names = "ahb", "mod", "pll-0", "pll-1";
657 dmas = <&dma SUN4I_DMA_NORMAL 16>,
658 <&dma SUN4I_DMA_NORMAL 16>,
659 <&dma SUN4I_DMA_DEDICATED 24>;
660 dma-names = "ddc-tx", "ddc-rx", "audio-tx";
664 #address-cells = <1>;
668 #address-cells = <1>;
672 hdmi_in_tcon0: endpoint@0 {
674 remote-endpoint = <&tcon0_out_hdmi>;
677 hdmi_in_tcon1: endpoint@1 {
679 remote-endpoint = <&tcon1_out_hdmi>;
690 compatible = "allwinner,sun4i-a10-spi";
691 reg = <0x01c17000 0x1000>;
692 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
693 clocks = <&ccu CLK_AHB_SPI2>, <&ccu CLK_SPI2>;
694 clock-names = "ahb", "mod";
695 dmas = <&dma SUN4I_DMA_DEDICATED 29>,
696 <&dma SUN4I_DMA_DEDICATED 28>;
697 dma-names = "rx", "tx";
699 #address-cells = <1>;
705 compatible = "allwinner,sun4i-a10-ahci";
706 reg = <0x01c18000 0x1000>;
707 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
708 clocks = <&ccu CLK_AHB_SATA>, <&ccu CLK_SATA>;
713 compatible = "allwinner,sun7i-a20-ehci", "generic-ehci";
714 reg = <0x01c1c000 0x100>;
715 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
716 clocks = <&ccu CLK_AHB_EHCI1>;
723 compatible = "allwinner,sun7i-a20-ohci", "generic-ohci";
724 reg = <0x01c1c400 0x100>;
725 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
726 clocks = <&ccu CLK_USB_OHCI1>, <&ccu CLK_AHB_OHCI1>;
733 compatible = "allwinner,sun7i-a20-csi1",
734 "allwinner,sun4i-a10-csi1";
735 reg = <0x01c1d000 0x1000>;
736 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
737 clocks = <&ccu CLK_AHB_CSI1>, <&ccu CLK_DRAM_CSI1>;
738 clock-names = "bus", "ram";
739 resets = <&ccu RST_CSI1>;
744 compatible = "allwinner,sun4i-a10-spi";
745 reg = <0x01c1f000 0x1000>;
746 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
747 clocks = <&ccu CLK_AHB_SPI3>, <&ccu CLK_SPI3>;
748 clock-names = "ahb", "mod";
749 dmas = <&dma SUN4I_DMA_DEDICATED 31>,
750 <&dma SUN4I_DMA_DEDICATED 30>;
751 dma-names = "rx", "tx";
753 #address-cells = <1>;
759 compatible = "allwinner,sun7i-a20-ccu";
760 reg = <0x01c20000 0x400>;
761 clocks = <&osc24M>, <&osc32k>;
762 clock-names = "hosc", "losc";
767 pio: pinctrl@1c20800 {
768 compatible = "allwinner,sun7i-a20-pinctrl";
769 reg = <0x01c20800 0x400>;
770 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
771 clocks = <&ccu CLK_APB0_PIO>, <&osc24M>, <&osc32k>;
772 clock-names = "apb", "hosc", "losc";
774 interrupt-controller;
775 #interrupt-cells = <3>;
779 can_pa_pins: can-pa-pins {
780 pins = "PA16", "PA17";
785 can_ph_pins: can-ph-pins {
786 pins = "PH20", "PH21";
791 clk_out_a_pin: clk-out-a-pin {
793 function = "clk_out_a";
797 clk_out_b_pin: clk-out-b-pin {
799 function = "clk_out_b";
803 csi0_8bits_pins: csi-8bits-pins {
804 pins = "PE0", "PE2", "PE3", "PE4", "PE5",
805 "PE6", "PE7", "PE8", "PE9", "PE10",
811 csi0_clk_pin: csi-clk-pin {
817 csi1_8bits_pg_pins: csi1-8bits-pg-pins {
818 pins = "PG0", "PG2", "PG3", "PG4", "PG5",
819 "PG6", "PG7", "PG8", "PG9", "PG10",
825 csi1_24bits_ph_pins: csi1-24bits-ph-pins {
826 pins = "PH0", "PH1", "PH2", "PH3", "PH4",
827 "PH5", "PH6", "PH7", "PH8", "PH9",
828 "PH10", "PH11", "PH12", "PH13", "PH14",
829 "PH15", "PH16", "PH17", "PH18", "PH19",
830 "PH20", "PH21", "PH22", "PH23", "PH24",
831 "PH25", "PH26", "PH27";
836 csi1_clk_pg_pin: csi1-clk-pg-pin {
842 emac_pa_pins: emac-pa-pins {
843 pins = "PA0", "PA1", "PA2",
844 "PA3", "PA4", "PA5", "PA6",
845 "PA7", "PA8", "PA9", "PA10",
846 "PA11", "PA12", "PA13", "PA14",
852 emac_ph_pins: emac-ph-pins {
853 pins = "PH8", "PH9", "PH10", "PH11",
854 "PH14", "PH15", "PH16", "PH17",
855 "PH18", "PH19", "PH20", "PH21",
856 "PH22", "PH23", "PH24", "PH25",
862 gmac_mii_pins: gmac-mii-pins {
863 pins = "PA0", "PA1", "PA2",
864 "PA3", "PA4", "PA5", "PA6",
865 "PA7", "PA8", "PA9", "PA10",
866 "PA11", "PA12", "PA13", "PA14",
872 gmac_rgmii_pins: gmac-rgmii-pins {
873 pins = "PA0", "PA1", "PA2",
874 "PA3", "PA4", "PA5", "PA6",
875 "PA7", "PA8", "PA10",
876 "PA11", "PA12", "PA13",
880 * data lines in RGMII mode use DDR mode
881 * and need a higher signal drive strength
883 drive-strength = <40>;
887 i2c0_pins: i2c0-pins {
893 i2c1_pins: i2c1-pins {
894 pins = "PB18", "PB19";
899 i2c2_pins: i2c2-pins {
900 pins = "PB20", "PB21";
905 i2c3_pins: i2c3-pins {
911 ir0_rx_pin: ir0-rx-pin {
917 ir0_tx_pin: ir0-tx-pin {
923 ir1_rx_pin: ir1-rx-pin {
929 ir1_tx_pin: ir1-tx-pin {
935 mmc0_pins: mmc0-pins {
936 pins = "PF0", "PF1", "PF2",
939 drive-strength = <30>;
944 mmc2_pins: mmc2-pins {
945 pins = "PC6", "PC7", "PC8",
946 "PC9", "PC10", "PC11";
948 drive-strength = <30>;
953 mmc3_pins: mmc3-pins {
954 pins = "PI4", "PI5", "PI6",
957 drive-strength = <30>;
962 ps2_0_pins: ps2-0-pins {
963 pins = "PI20", "PI21";
968 ps2_1_ph_pins: ps2-1-ph-pins {
969 pins = "PH12", "PH13";
986 spdif_tx_pin: spdif-tx-pin {
993 spi0_pi_pins: spi0-pi-pins {
994 pins = "PI11", "PI12", "PI13";
999 spi0_cs0_pi_pin: spi0-cs0-pi-pin {
1005 spi0_cs1_pi_pin: spi0-cs1-pi-pin {
1011 spi1_pi_pins: spi1-pi-pins {
1012 pins = "PI17", "PI18", "PI19";
1017 spi1_cs0_pi_pin: spi1-cs0-pi-pin {
1023 spi2_pb_pins: spi2-pb-pins {
1024 pins = "PB15", "PB16", "PB17";
1029 spi2_cs0_pb_pin: spi2-cs0-pb-pin {
1035 spi2_pc_pins: spi2-pc-pins {
1036 pins = "PC20", "PC21", "PC22";
1041 spi2_cs0_pc_pin: spi2-cs0-pc-pin {
1047 uart0_pb_pins: uart0-pb-pins {
1048 pins = "PB22", "PB23";
1053 uart0_pf_pins: uart0-pf-pins {
1054 pins = "PF2", "PF4";
1059 uart1_pa_pins: uart1-pa-pins {
1060 pins = "PA10", "PA11";
1065 uart1_cts_rts_pa_pins: uart1-cts-rts-pa-pins {
1066 pins = "PA12", "PA13";
1071 uart2_pa_pins: uart2-pa-pins {
1072 pins = "PA2", "PA3";
1077 uart2_cts_rts_pa_pins: uart2-cts-rts-pa-pins {
1078 pins = "PA0", "PA1";
1083 uart2_pi_pins: uart2-pi-pins {
1084 pins = "PI18", "PI19";
1089 uart2_cts_rts_pi_pins: uart2-cts-rts-pi-pins {
1090 pins = "PI16", "PI17";
1095 uart3_pg_pins: uart3-pg-pins {
1096 pins = "PG6", "PG7";
1101 uart3_cts_rts_pg_pins: uart3-cts-rts-pg-pins {
1102 pins = "PG8", "PG9";
1107 uart3_ph_pins: uart3-ph-pins {
1108 pins = "PH0", "PH1";
1113 uart3_cts_rts_ph_pins: uart3-cts-rts-ph-pins {
1114 pins = "PH2", "PH3";
1119 uart4_pg_pins: uart4-pg-pins {
1120 pins = "PG10", "PG11";
1125 uart4_ph_pins: uart4-ph-pins {
1126 pins = "PH4", "PH5";
1131 uart5_ph_pins: uart5-ph-pins {
1132 pins = "PH6", "PH7";
1137 uart5_pi_pins: uart5-pi-pins {
1138 pins = "PI10", "PI11";
1143 uart6_pa_pins: uart6-pa-pins {
1144 pins = "PA12", "PA13";
1149 uart6_pi_pins: uart6-pi-pins {
1150 pins = "PI12", "PI13";
1155 uart7_pa_pins: uart7-pa-pins {
1156 pins = "PA14", "PA15";
1161 uart7_pi_pins: uart7-pi-pins {
1162 pins = "PI20", "PI21";
1168 compatible = "allwinner,sun4i-a10-timer";
1169 reg = <0x01c20c00 0x90>;
1170 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
1171 <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>,
1172 <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
1173 <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
1174 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
1175 <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
1179 wdt: watchdog@1c20c90 {
1180 compatible = "allwinner,sun4i-a10-wdt";
1181 reg = <0x01c20c90 0x10>;
1182 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
1187 compatible = "allwinner,sun7i-a20-rtc";
1188 reg = <0x01c20d00 0x20>;
1189 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
1193 compatible = "allwinner,sun7i-a20-pwm";
1194 reg = <0x01c20e00 0xc>;
1197 status = "disabled";
1200 spdif: spdif@1c21000 {
1201 #sound-dai-cells = <0>;
1202 compatible = "allwinner,sun4i-a10-spdif";
1203 reg = <0x01c21000 0x400>;
1204 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
1205 clocks = <&ccu CLK_APB0_SPDIF>, <&ccu CLK_SPDIF>;
1206 clock-names = "apb", "spdif";
1207 dmas = <&dma SUN4I_DMA_NORMAL 2>,
1208 <&dma SUN4I_DMA_NORMAL 2>;
1209 dma-names = "rx", "tx";
1210 status = "disabled";
1214 compatible = "allwinner,sun4i-a10-ir";
1215 clocks = <&ccu CLK_APB0_IR0>, <&ccu CLK_IR0>;
1216 clock-names = "apb", "ir";
1217 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
1218 reg = <0x01c21800 0x40>;
1219 status = "disabled";
1223 compatible = "allwinner,sun4i-a10-ir";
1224 clocks = <&ccu CLK_APB0_IR1>, <&ccu CLK_IR1>;
1225 clock-names = "apb", "ir";
1226 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
1227 reg = <0x01c21c00 0x40>;
1228 status = "disabled";
1232 #sound-dai-cells = <0>;
1233 compatible = "allwinner,sun4i-a10-i2s";
1234 reg = <0x01c22000 0x400>;
1235 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
1236 clocks = <&ccu CLK_APB0_I2S1>, <&ccu CLK_I2S1>;
1237 clock-names = "apb", "mod";
1238 dmas = <&dma SUN4I_DMA_NORMAL 4>,
1239 <&dma SUN4I_DMA_NORMAL 4>;
1240 dma-names = "rx", "tx";
1241 status = "disabled";
1245 #sound-dai-cells = <0>;
1246 compatible = "allwinner,sun4i-a10-i2s";
1247 reg = <0x01c22400 0x400>;
1248 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
1249 clocks = <&ccu CLK_APB0_I2S0>, <&ccu CLK_I2S0>;
1250 clock-names = "apb", "mod";
1251 dmas = <&dma SUN4I_DMA_NORMAL 3>,
1252 <&dma SUN4I_DMA_NORMAL 3>;
1253 dma-names = "rx", "tx";
1254 status = "disabled";
1257 lradc: lradc@1c22800 {
1258 compatible = "allwinner,sun4i-a10-lradc-keys";
1259 reg = <0x01c22800 0x100>;
1260 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
1261 status = "disabled";
1264 codec: codec@1c22c00 {
1265 #sound-dai-cells = <0>;
1266 compatible = "allwinner,sun7i-a20-codec";
1267 reg = <0x01c22c00 0x40>;
1268 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
1269 clocks = <&ccu CLK_APB0_CODEC>, <&ccu CLK_CODEC>;
1270 clock-names = "apb", "codec";
1271 dmas = <&dma SUN4I_DMA_NORMAL 19>,
1272 <&dma SUN4I_DMA_NORMAL 19>;
1273 dma-names = "rx", "tx";
1274 status = "disabled";
1277 sid: eeprom@1c23800 {
1278 compatible = "allwinner,sun7i-a20-sid";
1279 reg = <0x01c23800 0x200>;
1283 #sound-dai-cells = <0>;
1284 compatible = "allwinner,sun4i-a10-i2s";
1285 reg = <0x01c24400 0x400>;
1286 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
1287 clocks = <&ccu CLK_APB0_I2S2>, <&ccu CLK_I2S2>;
1288 clock-names = "apb", "mod";
1289 dmas = <&dma SUN4I_DMA_NORMAL 6>,
1290 <&dma SUN4I_DMA_NORMAL 6>;
1291 dma-names = "rx", "tx";
1292 status = "disabled";
1296 compatible = "allwinner,sun5i-a13-ts";
1297 reg = <0x01c25000 0x100>;
1298 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
1299 #thermal-sensor-cells = <0>;
1302 uart0: serial@1c28000 {
1303 compatible = "snps,dw-apb-uart";
1304 reg = <0x01c28000 0x400>;
1305 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
1308 clocks = <&ccu CLK_APB1_UART0>;
1309 status = "disabled";
1312 uart1: serial@1c28400 {
1313 compatible = "snps,dw-apb-uart";
1314 reg = <0x01c28400 0x400>;
1315 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
1318 clocks = <&ccu CLK_APB1_UART1>;
1319 status = "disabled";
1322 uart2: serial@1c28800 {
1323 compatible = "snps,dw-apb-uart";
1324 reg = <0x01c28800 0x400>;
1325 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
1328 clocks = <&ccu CLK_APB1_UART2>;
1329 status = "disabled";
1332 uart3: serial@1c28c00 {
1333 compatible = "snps,dw-apb-uart";
1334 reg = <0x01c28c00 0x400>;
1335 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
1338 clocks = <&ccu CLK_APB1_UART3>;
1339 status = "disabled";
1342 uart4: serial@1c29000 {
1343 compatible = "snps,dw-apb-uart";
1344 reg = <0x01c29000 0x400>;
1345 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
1348 clocks = <&ccu CLK_APB1_UART4>;
1349 status = "disabled";
1352 uart5: serial@1c29400 {
1353 compatible = "snps,dw-apb-uart";
1354 reg = <0x01c29400 0x400>;
1355 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
1358 clocks = <&ccu CLK_APB1_UART5>;
1359 status = "disabled";
1362 uart6: serial@1c29800 {
1363 compatible = "snps,dw-apb-uart";
1364 reg = <0x01c29800 0x400>;
1365 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
1368 clocks = <&ccu CLK_APB1_UART6>;
1369 status = "disabled";
1372 uart7: serial@1c29c00 {
1373 compatible = "snps,dw-apb-uart";
1374 reg = <0x01c29c00 0x400>;
1375 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
1378 clocks = <&ccu CLK_APB1_UART7>;
1379 status = "disabled";
1383 compatible = "allwinner,sun4i-a10-ps2";
1384 reg = <0x01c2a000 0x400>;
1385 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
1386 clocks = <&ccu CLK_APB1_PS20>;
1387 status = "disabled";
1391 compatible = "allwinner,sun4i-a10-ps2";
1392 reg = <0x01c2a400 0x400>;
1393 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
1394 clocks = <&ccu CLK_APB1_PS21>;
1395 status = "disabled";
1399 compatible = "allwinner,sun7i-a20-i2c",
1400 "allwinner,sun4i-a10-i2c";
1401 reg = <0x01c2ac00 0x400>;
1402 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
1403 clocks = <&ccu CLK_APB1_I2C0>;
1404 pinctrl-names = "default";
1405 pinctrl-0 = <&i2c0_pins>;
1406 status = "disabled";
1407 #address-cells = <1>;
1412 compatible = "allwinner,sun7i-a20-i2c",
1413 "allwinner,sun4i-a10-i2c";
1414 reg = <0x01c2b000 0x400>;
1415 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
1416 clocks = <&ccu CLK_APB1_I2C1>;
1417 pinctrl-names = "default";
1418 pinctrl-0 = <&i2c1_pins>;
1419 status = "disabled";
1420 #address-cells = <1>;
1425 compatible = "allwinner,sun7i-a20-i2c",
1426 "allwinner,sun4i-a10-i2c";
1427 reg = <0x01c2b400 0x400>;
1428 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
1429 clocks = <&ccu CLK_APB1_I2C2>;
1430 pinctrl-names = "default";
1431 pinctrl-0 = <&i2c2_pins>;
1432 status = "disabled";
1433 #address-cells = <1>;
1438 compatible = "allwinner,sun7i-a20-i2c",
1439 "allwinner,sun4i-a10-i2c";
1440 reg = <0x01c2b800 0x400>;
1441 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
1442 clocks = <&ccu CLK_APB1_I2C3>;
1443 pinctrl-names = "default";
1444 pinctrl-0 = <&i2c3_pins>;
1445 status = "disabled";
1446 #address-cells = <1>;
1451 compatible = "allwinner,sun7i-a20-can",
1452 "allwinner,sun4i-a10-can";
1453 reg = <0x01c2bc00 0x400>;
1454 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
1455 clocks = <&ccu CLK_APB1_CAN>;
1456 status = "disabled";
1460 compatible = "allwinner,sun7i-a20-i2c",
1461 "allwinner,sun4i-a10-i2c";
1462 reg = <0x01c2c000 0x400>;
1463 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
1464 clocks = <&ccu CLK_APB1_I2C4>;
1465 status = "disabled";
1466 #address-cells = <1>;
1471 compatible = "allwinner,sun7i-a20-mali", "arm,mali-400";
1472 reg = <0x01c40000 0x10000>;
1473 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
1474 <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
1475 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>,
1476 <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
1477 <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
1478 <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>,
1479 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
1480 interrupt-names = "gp",
1487 clocks = <&ccu CLK_AHB_GPU>, <&ccu CLK_GPU>;
1488 clock-names = "bus", "core";
1489 resets = <&ccu RST_GPU>;
1491 assigned-clocks = <&ccu CLK_GPU>;
1492 assigned-clock-rates = <384000000>;
1495 gmac: ethernet@1c50000 {
1496 compatible = "allwinner,sun7i-a20-gmac";
1497 reg = <0x01c50000 0x10000>;
1498 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
1499 interrupt-names = "macirq";
1500 clocks = <&ccu CLK_AHB_GMAC>, <&gmac_tx_clk>;
1501 clock-names = "stmmaceth", "allwinner_gmac_tx";
1504 snps,force_sf_dma_mode;
1505 status = "disabled";
1508 compatible = "snps,dwmac-mdio";
1509 #address-cells = <1>;
1515 compatible = "allwinner,sun7i-a20-hstimer";
1516 reg = <0x01c60000 0x1000>;
1517 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>,
1518 <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>,
1519 <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>,
1520 <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
1521 clocks = <&ccu CLK_AHB_HSTIMER>;
1524 gic: interrupt-controller@1c81000 {
1525 compatible = "arm,gic-400";
1526 reg = <0x01c81000 0x1000>,
1527 <0x01c82000 0x2000>,
1528 <0x01c84000 0x2000>,
1529 <0x01c86000 0x2000>;
1530 interrupt-controller;
1531 #interrupt-cells = <3>;
1532 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
1535 fe0: display-frontend@1e00000 {
1536 compatible = "allwinner,sun7i-a20-display-frontend";
1537 reg = <0x01e00000 0x20000>;
1538 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
1539 clocks = <&ccu CLK_AHB_DE_FE0>, <&ccu CLK_DE_FE0>,
1540 <&ccu CLK_DRAM_DE_FE0>;
1541 clock-names = "ahb", "mod",
1543 resets = <&ccu RST_DE_FE0>;
1546 #address-cells = <1>;
1550 #address-cells = <1>;
1554 fe0_out_be0: endpoint@0 {
1556 remote-endpoint = <&be0_in_fe0>;
1559 fe0_out_be1: endpoint@1 {
1561 remote-endpoint = <&be1_in_fe0>;
1567 fe1: display-frontend@1e20000 {
1568 compatible = "allwinner,sun7i-a20-display-frontend";
1569 reg = <0x01e20000 0x20000>;
1570 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
1571 clocks = <&ccu CLK_AHB_DE_FE1>, <&ccu CLK_DE_FE1>,
1572 <&ccu CLK_DRAM_DE_FE1>;
1573 clock-names = "ahb", "mod",
1575 resets = <&ccu RST_DE_FE1>;
1578 #address-cells = <1>;
1582 #address-cells = <1>;
1586 fe1_out_be0: endpoint@0 {
1588 remote-endpoint = <&be0_in_fe1>;
1591 fe1_out_be1: endpoint@1 {
1593 remote-endpoint = <&be1_in_fe1>;
1599 be1: display-backend@1e40000 {
1600 compatible = "allwinner,sun7i-a20-display-backend";
1601 reg = <0x01e40000 0x10000>;
1602 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
1603 clocks = <&ccu CLK_AHB_DE_BE1>, <&ccu CLK_DE_BE1>,
1604 <&ccu CLK_DRAM_DE_BE1>;
1605 clock-names = "ahb", "mod",
1607 resets = <&ccu RST_DE_BE1>;
1610 #address-cells = <1>;
1614 #address-cells = <1>;
1618 be1_in_fe0: endpoint@0 {
1620 remote-endpoint = <&fe0_out_be1>;
1623 be1_in_fe1: endpoint@1 {
1625 remote-endpoint = <&fe1_out_be1>;
1630 #address-cells = <1>;
1634 be1_out_tcon0: endpoint@0 {
1636 remote-endpoint = <&tcon0_in_be1>;
1639 be1_out_tcon1: endpoint@1 {
1641 remote-endpoint = <&tcon1_in_be1>;
1647 be0: display-backend@1e60000 {
1648 compatible = "allwinner,sun7i-a20-display-backend";
1649 reg = <0x01e60000 0x10000>;
1650 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
1651 clocks = <&ccu CLK_AHB_DE_BE0>, <&ccu CLK_DE_BE0>,
1652 <&ccu CLK_DRAM_DE_BE0>;
1653 clock-names = "ahb", "mod",
1655 resets = <&ccu RST_DE_BE0>;
1658 #address-cells = <1>;
1662 #address-cells = <1>;
1666 be0_in_fe0: endpoint@0 {
1668 remote-endpoint = <&fe0_out_be0>;
1671 be0_in_fe1: endpoint@1 {
1673 remote-endpoint = <&fe1_out_be0>;
1678 #address-cells = <1>;
1682 be0_out_tcon0: endpoint@0 {
1684 remote-endpoint = <&tcon0_in_be0>;
1687 be0_out_tcon1: endpoint@1 {
1689 remote-endpoint = <&tcon1_in_be0>;