2 * Copyright 2013 Maxime Ripard
4 * Maxime Ripard <maxime.ripard@free-electrons.com>
6 * This file is dual-licensed: you can use it either under the terms
7 * of the GPL or the X11 license, at your option. Note that this dual
8 * licensing only applies to this file, and not this project as a
11 * a) This file is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of the
14 * License, or (at your option) any later version.
16 * This file is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
23 * b) Permission is hereby granted, free of charge, to any person
24 * obtaining a copy of this software and associated documentation
25 * files (the "Software"), to deal in the Software without
26 * restriction, including without limitation the rights to use,
27 * copy, modify, merge, publish, distribute, sublicense, and/or
28 * sell copies of the Software, and to permit persons to whom the
29 * Software is furnished to do so, subject to the following
32 * The above copyright notice and this permission notice shall be
33 * included in all copies or substantial portions of the Software.
35 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
36 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
37 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
38 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
39 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
40 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
41 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
42 * OTHER DEALINGS IN THE SOFTWARE.
45 #include "skeleton.dtsi"
47 #include <dt-bindings/interrupt-controller/arm-gic.h>
48 #include <dt-bindings/thermal/thermal.h>
49 #include <dt-bindings/dma/sun4i-a10.h>
50 #include <dt-bindings/clock/sun7i-a20-ccu.h>
51 #include <dt-bindings/reset/sun4i-a10-ccu.h>
54 interrupt-parent = <&gic>;
66 compatible = "allwinner,simple-framebuffer",
68 allwinner,pipeline = "de_be0-lcd0-hdmi";
69 clocks = <&ccu CLK_AHB_LCD0>, <&ccu CLK_AHB_HDMI0>,
70 <&ccu CLK_AHB_DE_BE0>, <&ccu CLK_DE_BE0>,
71 <&ccu CLK_TCON0_CH1>, <&ccu CLK_DRAM_DE_BE0>,
77 compatible = "allwinner,simple-framebuffer",
79 allwinner,pipeline = "de_be0-lcd0";
80 clocks = <&ccu CLK_AHB_LCD0>, <&ccu CLK_AHB_DE_BE0>,
81 <&ccu CLK_DE_BE0>, <&ccu CLK_TCON0_CH0>,
82 <&ccu CLK_DRAM_DE_BE0>;
87 compatible = "allwinner,simple-framebuffer",
89 allwinner,pipeline = "de_be0-lcd0-tve0";
90 clocks = <&ccu CLK_AHB_TVE0>, <&ccu CLK_AHB_LCD0>,
91 <&ccu CLK_AHB_DE_BE0>,
92 <&ccu CLK_DE_BE0>, <&ccu CLK_TCON0_CH1>,
93 <&ccu CLK_DRAM_TVE0>, <&ccu CLK_DRAM_DE_BE0>;
103 compatible = "arm,cortex-a7";
106 clocks = <&ccu CLK_CPU>;
107 clock-latency = <244144>; /* 8 32k periods */
118 #cooling-cells = <2>;
122 compatible = "arm,cortex-a7";
125 clocks = <&ccu CLK_CPU>;
126 clock-latency = <244144>; /* 8 32k periods */
137 #cooling-cells = <2>;
144 polling-delay-passive = <250>;
145 polling-delay = <1000>;
146 thermal-sensors = <&rtp>;
150 trip = <&cpu_alert0>;
151 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
156 cpu_alert0: cpu_alert0 {
158 temperature = <75000>;
165 temperature = <100000>;
174 reg = <0x40000000 0x80000000>;
178 #address-cells = <1>;
182 /* Address must be kept in the lower 256 MiBs of DRAM for VE. */
183 cma_pool: cma@4a000000 {
184 compatible = "shared-dma-pool";
186 alloc-ranges = <0x4a000000 0x6000000>;
193 compatible = "arm,armv7-timer";
194 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
195 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
196 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
197 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
201 compatible = "arm,cortex-a7-pmu", "arm,cortex-a15-pmu";
202 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
203 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
207 #address-cells = <1>;
211 osc24M: clk@1c20050 {
213 compatible = "fixed-clock";
214 clock-frequency = <24000000>;
215 clock-output-names = "osc24M";
220 compatible = "fixed-clock";
221 clock-frequency = <32768>;
222 clock-output-names = "osc32k";
226 * The following two are dummy clocks, placeholders
227 * used in the gmac_tx clock. The gmac driver will
228 * choose one parent depending on the PHY interface
229 * mode, using clk_set_rate auto-reparenting.
231 * The actual TX clock rate is not controlled by the
234 mii_phy_tx_clk: clk@1 {
236 compatible = "fixed-clock";
237 clock-frequency = <25000000>;
238 clock-output-names = "mii_phy_tx";
241 gmac_int_tx_clk: clk@2 {
243 compatible = "fixed-clock";
244 clock-frequency = <125000000>;
245 clock-output-names = "gmac_int_tx";
248 gmac_tx_clk: clk@1c20164 {
250 compatible = "allwinner,sun7i-a20-gmac-clk";
251 reg = <0x01c20164 0x4>;
252 clocks = <&mii_phy_tx_clk>, <&gmac_int_tx_clk>;
253 clock-output-names = "gmac_tx";
259 compatible = "allwinner,sun7i-a20-display-engine";
260 allwinner,pipelines = <&fe0>, <&fe1>;
265 compatible = "simple-bus";
266 #address-cells = <1>;
270 system-control@1c00000 {
271 compatible = "allwinner,sun7i-a20-system-control",
272 "allwinner,sun4i-a10-system-control";
273 reg = <0x01c00000 0x30>;
274 #address-cells = <1>;
279 compatible = "mmio-sram";
280 reg = <0x00000000 0xc000>;
281 #address-cells = <1>;
283 ranges = <0 0x00000000 0xc000>;
285 emac_sram: sram-section@8000 {
286 compatible = "allwinner,sun7i-a20-sram-a3-a4",
287 "allwinner,sun4i-a10-sram-a3-a4";
288 reg = <0x8000 0x4000>;
294 compatible = "mmio-sram";
295 reg = <0x00010000 0x1000>;
296 #address-cells = <1>;
298 ranges = <0 0x00010000 0x1000>;
300 otg_sram: sram-section@0 {
301 compatible = "allwinner,sun7i-a20-sram-d",
302 "allwinner,sun4i-a10-sram-d";
303 reg = <0x0000 0x1000>;
308 sram_c: sram@1d00000 {
309 compatible = "mmio-sram";
310 reg = <0x01d00000 0xd0000>;
311 #address-cells = <1>;
313 ranges = <0 0x01d00000 0xd0000>;
315 ve_sram: sram-section@0 {
316 compatible = "allwinner,sun7i-a20-sram-c1",
317 "allwinner,sun4i-a10-sram-c1";
318 reg = <0x000000 0x80000>;
323 nmi_intc: interrupt-controller@1c00030 {
324 compatible = "allwinner,sun7i-a20-sc-nmi";
325 interrupt-controller;
326 #interrupt-cells = <2>;
327 reg = <0x01c00030 0x0c>;
328 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
331 dma: dma-controller@1c02000 {
332 compatible = "allwinner,sun4i-a10-dma";
333 reg = <0x01c02000 0x1000>;
334 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
335 clocks = <&ccu CLK_AHB_DMA>;
340 compatible = "allwinner,sun4i-a10-nand";
341 reg = <0x01c03000 0x1000>;
342 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
343 clocks = <&ccu CLK_AHB_NAND>, <&ccu CLK_NAND>;
344 clock-names = "ahb", "mod";
345 dmas = <&dma SUN4I_DMA_DEDICATED 3>;
348 #address-cells = <1>;
353 compatible = "allwinner,sun4i-a10-spi";
354 reg = <0x01c05000 0x1000>;
355 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
356 clocks = <&ccu CLK_AHB_SPI0>, <&ccu CLK_SPI0>;
357 clock-names = "ahb", "mod";
358 dmas = <&dma SUN4I_DMA_DEDICATED 27>,
359 <&dma SUN4I_DMA_DEDICATED 26>;
360 dma-names = "rx", "tx";
362 #address-cells = <1>;
368 compatible = "allwinner,sun4i-a10-spi";
369 reg = <0x01c06000 0x1000>;
370 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
371 clocks = <&ccu CLK_AHB_SPI1>, <&ccu CLK_SPI1>;
372 clock-names = "ahb", "mod";
373 dmas = <&dma SUN4I_DMA_DEDICATED 9>,
374 <&dma SUN4I_DMA_DEDICATED 8>;
375 dma-names = "rx", "tx";
377 #address-cells = <1>;
382 emac: ethernet@1c0b000 {
383 compatible = "allwinner,sun4i-a10-emac";
384 reg = <0x01c0b000 0x1000>;
385 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
386 clocks = <&ccu CLK_AHB_EMAC>;
387 allwinner,sram = <&emac_sram 1>;
392 compatible = "allwinner,sun4i-a10-mdio";
393 reg = <0x01c0b080 0x14>;
395 #address-cells = <1>;
399 tcon0: lcd-controller@1c0c000 {
400 compatible = "allwinner,sun7i-a20-tcon";
401 reg = <0x01c0c000 0x1000>;
402 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
403 resets = <&ccu RST_TCON0>;
405 clocks = <&ccu CLK_AHB_LCD0>,
406 <&ccu CLK_TCON0_CH0>,
407 <&ccu CLK_TCON0_CH1>;
411 clock-output-names = "tcon0-pixel-clock";
412 dmas = <&dma SUN4I_DMA_DEDICATED 14>;
415 #address-cells = <1>;
419 #address-cells = <1>;
423 tcon0_in_be0: endpoint@0 {
425 remote-endpoint = <&be0_out_tcon0>;
428 tcon0_in_be1: endpoint@1 {
430 remote-endpoint = <&be1_out_tcon0>;
435 #address-cells = <1>;
439 tcon0_out_hdmi: endpoint@1 {
441 remote-endpoint = <&hdmi_in_tcon0>;
442 allwinner,tcon-channel = <1>;
448 tcon1: lcd-controller@1c0d000 {
449 compatible = "allwinner,sun7i-a20-tcon";
450 reg = <0x01c0d000 0x1000>;
451 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
452 resets = <&ccu RST_TCON1>;
454 clocks = <&ccu CLK_AHB_LCD1>,
455 <&ccu CLK_TCON1_CH0>,
456 <&ccu CLK_TCON1_CH1>;
460 clock-output-names = "tcon1-pixel-clock";
461 dmas = <&dma SUN4I_DMA_DEDICATED 15>;
464 #address-cells = <1>;
468 #address-cells = <1>;
472 tcon1_in_be0: endpoint@0 {
474 remote-endpoint = <&be0_out_tcon1>;
477 tcon1_in_be1: endpoint@1 {
479 remote-endpoint = <&be1_out_tcon1>;
484 #address-cells = <1>;
488 tcon1_out_hdmi: endpoint@1 {
490 remote-endpoint = <&hdmi_in_tcon1>;
491 allwinner,tcon-channel = <1>;
497 video-codec@1c0e000 {
498 compatible = "allwinner,sun7i-a20-video-engine";
499 reg = <0x01c0e000 0x1000>;
500 clocks = <&ccu CLK_AHB_VE>, <&ccu CLK_VE>,
502 clock-names = "ahb", "mod", "ram";
503 resets = <&ccu RST_VE>;
504 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
505 allwinner,sram = <&ve_sram 1>;
509 compatible = "allwinner,sun7i-a20-mmc";
510 reg = <0x01c0f000 0x1000>;
511 clocks = <&ccu CLK_AHB_MMC0>,
513 <&ccu CLK_MMC0_OUTPUT>,
514 <&ccu CLK_MMC0_SAMPLE>;
519 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
521 #address-cells = <1>;
526 compatible = "allwinner,sun7i-a20-mmc";
527 reg = <0x01c10000 0x1000>;
528 clocks = <&ccu CLK_AHB_MMC1>,
530 <&ccu CLK_MMC1_OUTPUT>,
531 <&ccu CLK_MMC1_SAMPLE>;
536 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
538 #address-cells = <1>;
543 compatible = "allwinner,sun7i-a20-mmc";
544 reg = <0x01c11000 0x1000>;
545 clocks = <&ccu CLK_AHB_MMC2>,
547 <&ccu CLK_MMC2_OUTPUT>,
548 <&ccu CLK_MMC2_SAMPLE>;
553 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
555 #address-cells = <1>;
560 compatible = "allwinner,sun7i-a20-mmc";
561 reg = <0x01c12000 0x1000>;
562 clocks = <&ccu CLK_AHB_MMC3>,
564 <&ccu CLK_MMC3_OUTPUT>,
565 <&ccu CLK_MMC3_SAMPLE>;
570 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
572 #address-cells = <1>;
576 usb_otg: usb@1c13000 {
577 compatible = "allwinner,sun4i-a10-musb";
578 reg = <0x01c13000 0x0400>;
579 clocks = <&ccu CLK_AHB_OTG>;
580 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
581 interrupt-names = "mc";
584 extcon = <&usbphy 0>;
585 allwinner,sram = <&otg_sram 1>;
589 usbphy: phy@1c13400 {
591 compatible = "allwinner,sun7i-a20-usb-phy";
592 reg = <0x01c13400 0x10 0x01c14800 0x4 0x01c1c800 0x4>;
593 reg-names = "phy_ctrl", "pmu1", "pmu2";
594 clocks = <&ccu CLK_USB_PHY>;
595 clock-names = "usb_phy";
596 resets = <&ccu RST_USB_PHY0>,
599 reset-names = "usb0_reset", "usb1_reset", "usb2_reset";
604 compatible = "allwinner,sun7i-a20-ehci", "generic-ehci";
605 reg = <0x01c14000 0x100>;
606 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
607 clocks = <&ccu CLK_AHB_EHCI0>;
614 compatible = "allwinner,sun7i-a20-ohci", "generic-ohci";
615 reg = <0x01c14400 0x100>;
616 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
617 clocks = <&ccu CLK_USB_OHCI0>, <&ccu CLK_AHB_OHCI0>;
623 crypto: crypto-engine@1c15000 {
624 compatible = "allwinner,sun7i-a20-crypto",
625 "allwinner,sun4i-a10-crypto";
626 reg = <0x01c15000 0x1000>;
627 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
628 clocks = <&ccu CLK_AHB_SS>, <&ccu CLK_SS>;
629 clock-names = "ahb", "mod";
633 compatible = "allwinner,sun7i-a20-hdmi",
634 "allwinner,sun5i-a10s-hdmi";
635 reg = <0x01c16000 0x1000>;
636 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
637 clocks = <&ccu CLK_AHB_HDMI0>, <&ccu CLK_HDMI>,
638 <&ccu CLK_PLL_VIDEO0_2X>,
639 <&ccu CLK_PLL_VIDEO1_2X>;
640 clock-names = "ahb", "mod", "pll-0", "pll-1";
641 dmas = <&dma SUN4I_DMA_NORMAL 16>,
642 <&dma SUN4I_DMA_NORMAL 16>,
643 <&dma SUN4I_DMA_DEDICATED 24>;
644 dma-names = "ddc-tx", "ddc-rx", "audio-tx";
648 #address-cells = <1>;
652 #address-cells = <1>;
656 hdmi_in_tcon0: endpoint@0 {
658 remote-endpoint = <&tcon0_out_hdmi>;
661 hdmi_in_tcon1: endpoint@1 {
663 remote-endpoint = <&tcon1_out_hdmi>;
668 #address-cells = <1>;
676 compatible = "allwinner,sun4i-a10-spi";
677 reg = <0x01c17000 0x1000>;
678 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
679 clocks = <&ccu CLK_AHB_SPI2>, <&ccu CLK_SPI2>;
680 clock-names = "ahb", "mod";
681 dmas = <&dma SUN4I_DMA_DEDICATED 29>,
682 <&dma SUN4I_DMA_DEDICATED 28>;
683 dma-names = "rx", "tx";
685 #address-cells = <1>;
691 compatible = "allwinner,sun4i-a10-ahci";
692 reg = <0x01c18000 0x1000>;
693 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
694 clocks = <&ccu CLK_AHB_SATA>, <&ccu CLK_SATA>;
699 compatible = "allwinner,sun7i-a20-ehci", "generic-ehci";
700 reg = <0x01c1c000 0x100>;
701 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
702 clocks = <&ccu CLK_AHB_EHCI1>;
709 compatible = "allwinner,sun7i-a20-ohci", "generic-ohci";
710 reg = <0x01c1c400 0x100>;
711 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
712 clocks = <&ccu CLK_USB_OHCI1>, <&ccu CLK_AHB_OHCI1>;
719 compatible = "allwinner,sun4i-a10-spi";
720 reg = <0x01c1f000 0x1000>;
721 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
722 clocks = <&ccu CLK_AHB_SPI3>, <&ccu CLK_SPI3>;
723 clock-names = "ahb", "mod";
724 dmas = <&dma SUN4I_DMA_DEDICATED 31>,
725 <&dma SUN4I_DMA_DEDICATED 30>;
726 dma-names = "rx", "tx";
728 #address-cells = <1>;
734 compatible = "allwinner,sun7i-a20-ccu";
735 reg = <0x01c20000 0x400>;
736 clocks = <&osc24M>, <&osc32k>;
737 clock-names = "hosc", "losc";
742 pio: pinctrl@1c20800 {
743 compatible = "allwinner,sun7i-a20-pinctrl";
744 reg = <0x01c20800 0x400>;
745 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
746 clocks = <&ccu CLK_APB0_PIO>, <&osc24M>, <&osc32k>;
747 clock-names = "apb", "hosc", "losc";
749 interrupt-controller;
750 #interrupt-cells = <3>;
753 can0_pins_a: can0@0 {
754 pins = "PH20", "PH21";
758 clk_out_a_pins_a: clk_out_a@0 {
760 function = "clk_out_a";
763 clk_out_b_pins_a: clk_out_b@0 {
765 function = "clk_out_b";
768 emac_pins_a: emac0@0 {
769 pins = "PA0", "PA1", "PA2",
770 "PA3", "PA4", "PA5", "PA6",
771 "PA7", "PA8", "PA9", "PA10",
772 "PA11", "PA12", "PA13", "PA14",
777 gmac_pins_mii_a: gmac_mii@0 {
778 pins = "PA0", "PA1", "PA2",
779 "PA3", "PA4", "PA5", "PA6",
780 "PA7", "PA8", "PA9", "PA10",
781 "PA11", "PA12", "PA13", "PA14",
786 gmac_pins_rgmii_a: gmac_rgmii@0 {
787 pins = "PA0", "PA1", "PA2",
788 "PA3", "PA4", "PA5", "PA6",
789 "PA7", "PA8", "PA10",
790 "PA11", "PA12", "PA13",
794 * data lines in RGMII mode use DDR mode
795 * and need a higher signal drive strength
797 drive-strength = <40>;
800 i2c0_pins_a: i2c0@0 {
805 i2c1_pins_a: i2c1@0 {
806 pins = "PB18", "PB19";
810 i2c2_pins_a: i2c2@0 {
811 pins = "PB20", "PB21";
815 i2c3_pins_a: i2c3@0 {
820 ir0_rx_pins_a: ir0@0 {
825 ir0_tx_pins_a: ir0@1 {
830 ir1_rx_pins_a: ir1@0 {
835 ir1_tx_pins_a: ir1@1 {
840 mmc0_pins_a: mmc0@0 {
841 pins = "PF0", "PF1", "PF2",
844 drive-strength = <30>;
848 mmc2_pins_a: mmc2@0 {
849 pins = "PC6", "PC7", "PC8",
850 "PC9", "PC10", "PC11";
852 drive-strength = <30>;
856 mmc3_pins_a: mmc3@0 {
857 pins = "PI4", "PI5", "PI6",
860 drive-strength = <30>;
864 ps20_pins_a: ps20@0 {
865 pins = "PI20", "PI21";
869 ps21_pins_a: ps21@0 {
870 pins = "PH12", "PH13";
874 pwm0_pins_a: pwm0@0 {
879 pwm1_pins_a: pwm1@0 {
884 spdif_tx_pins_a: spdif@0 {
890 spi0_pins_a: spi0@0 {
891 pins = "PI11", "PI12", "PI13";
895 spi0_cs0_pins_a: spi0_cs0@0 {
900 spi0_cs1_pins_a: spi0_cs1@0 {
905 spi1_pins_a: spi1@0 {
906 pins = "PI17", "PI18", "PI19";
910 spi1_cs0_pins_a: spi1_cs0@0 {
915 spi2_pins_a: spi2@0 {
916 pins = "PC20", "PC21", "PC22";
920 spi2_pins_b: spi2@1 {
921 pins = "PB15", "PB16", "PB17";
925 spi2_cs0_pins_a: spi2_cs0@0 {
930 spi2_cs0_pins_b: spi2_cs0@1 {
935 uart0_pins_a: uart0@0 {
936 pins = "PB22", "PB23";
940 uart2_pins_a: uart2@0 {
941 pins = "PI16", "PI17", "PI18", "PI19";
945 uart3_pins_a: uart3@0 {
946 pins = "PG6", "PG7", "PG8", "PG9";
950 uart3_pins_b: uart3@1 {
955 uart4_pins_a: uart4@0 {
956 pins = "PG10", "PG11";
960 uart4_pins_b: uart4@1 {
965 uart5_pins_a: uart5@0 {
966 pins = "PI10", "PI11";
970 uart6_pins_a: uart6@0 {
971 pins = "PI12", "PI13";
975 uart7_pins_a: uart7@0 {
976 pins = "PI20", "PI21";
982 compatible = "allwinner,sun4i-a10-timer";
983 reg = <0x01c20c00 0x90>;
984 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
985 <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>,
986 <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
987 <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
988 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
989 <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
993 wdt: watchdog@1c20c90 {
994 compatible = "allwinner,sun4i-a10-wdt";
995 reg = <0x01c20c90 0x10>;
999 compatible = "allwinner,sun7i-a20-rtc";
1000 reg = <0x01c20d00 0x20>;
1001 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
1005 compatible = "allwinner,sun7i-a20-pwm";
1006 reg = <0x01c20e00 0xc>;
1009 status = "disabled";
1012 spdif: spdif@1c21000 {
1013 #sound-dai-cells = <0>;
1014 compatible = "allwinner,sun4i-a10-spdif";
1015 reg = <0x01c21000 0x400>;
1016 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
1017 clocks = <&ccu CLK_APB0_SPDIF>, <&ccu CLK_SPDIF>;
1018 clock-names = "apb", "spdif";
1019 dmas = <&dma SUN4I_DMA_NORMAL 2>,
1020 <&dma SUN4I_DMA_NORMAL 2>;
1021 dma-names = "rx", "tx";
1022 status = "disabled";
1026 compatible = "allwinner,sun4i-a10-ir";
1027 clocks = <&ccu CLK_APB0_IR0>, <&ccu CLK_IR0>;
1028 clock-names = "apb", "ir";
1029 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
1030 reg = <0x01c21800 0x40>;
1031 status = "disabled";
1035 compatible = "allwinner,sun4i-a10-ir";
1036 clocks = <&ccu CLK_APB0_IR1>, <&ccu CLK_IR1>;
1037 clock-names = "apb", "ir";
1038 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
1039 reg = <0x01c21c00 0x40>;
1040 status = "disabled";
1044 #sound-dai-cells = <0>;
1045 compatible = "allwinner,sun4i-a10-i2s";
1046 reg = <0x01c22000 0x400>;
1047 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
1048 clocks = <&ccu CLK_APB0_I2S1>, <&ccu CLK_I2S1>;
1049 clock-names = "apb", "mod";
1050 dmas = <&dma SUN4I_DMA_NORMAL 4>,
1051 <&dma SUN4I_DMA_NORMAL 4>;
1052 dma-names = "rx", "tx";
1053 status = "disabled";
1057 #sound-dai-cells = <0>;
1058 compatible = "allwinner,sun4i-a10-i2s";
1059 reg = <0x01c22400 0x400>;
1060 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
1061 clocks = <&ccu CLK_APB0_I2S0>, <&ccu CLK_I2S0>;
1062 clock-names = "apb", "mod";
1063 dmas = <&dma SUN4I_DMA_NORMAL 3>,
1064 <&dma SUN4I_DMA_NORMAL 3>;
1065 dma-names = "rx", "tx";
1066 status = "disabled";
1069 lradc: lradc@1c22800 {
1070 compatible = "allwinner,sun4i-a10-lradc-keys";
1071 reg = <0x01c22800 0x100>;
1072 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
1073 status = "disabled";
1076 codec: codec@1c22c00 {
1077 #sound-dai-cells = <0>;
1078 compatible = "allwinner,sun7i-a20-codec";
1079 reg = <0x01c22c00 0x40>;
1080 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
1081 clocks = <&ccu CLK_APB0_CODEC>, <&ccu CLK_CODEC>;
1082 clock-names = "apb", "codec";
1083 dmas = <&dma SUN4I_DMA_NORMAL 19>,
1084 <&dma SUN4I_DMA_NORMAL 19>;
1085 dma-names = "rx", "tx";
1086 status = "disabled";
1089 sid: eeprom@1c23800 {
1090 compatible = "allwinner,sun7i-a20-sid";
1091 reg = <0x01c23800 0x200>;
1095 #sound-dai-cells = <0>;
1096 compatible = "allwinner,sun4i-a10-i2s";
1097 reg = <0x01c24400 0x400>;
1098 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
1099 clocks = <&ccu CLK_APB0_I2S2>, <&ccu CLK_I2S2>;
1100 clock-names = "apb", "mod";
1101 dmas = <&dma SUN4I_DMA_NORMAL 6>,
1102 <&dma SUN4I_DMA_NORMAL 6>;
1103 dma-names = "rx", "tx";
1104 status = "disabled";
1108 compatible = "allwinner,sun5i-a13-ts";
1109 reg = <0x01c25000 0x100>;
1110 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
1111 #thermal-sensor-cells = <0>;
1114 uart0: serial@1c28000 {
1115 compatible = "snps,dw-apb-uart";
1116 reg = <0x01c28000 0x400>;
1117 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
1120 clocks = <&ccu CLK_APB1_UART0>;
1121 status = "disabled";
1124 uart1: serial@1c28400 {
1125 compatible = "snps,dw-apb-uart";
1126 reg = <0x01c28400 0x400>;
1127 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
1130 clocks = <&ccu CLK_APB1_UART1>;
1131 status = "disabled";
1134 uart2: serial@1c28800 {
1135 compatible = "snps,dw-apb-uart";
1136 reg = <0x01c28800 0x400>;
1137 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
1140 clocks = <&ccu CLK_APB1_UART2>;
1141 status = "disabled";
1144 uart3: serial@1c28c00 {
1145 compatible = "snps,dw-apb-uart";
1146 reg = <0x01c28c00 0x400>;
1147 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
1150 clocks = <&ccu CLK_APB1_UART3>;
1151 status = "disabled";
1154 uart4: serial@1c29000 {
1155 compatible = "snps,dw-apb-uart";
1156 reg = <0x01c29000 0x400>;
1157 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
1160 clocks = <&ccu CLK_APB1_UART4>;
1161 status = "disabled";
1164 uart5: serial@1c29400 {
1165 compatible = "snps,dw-apb-uart";
1166 reg = <0x01c29400 0x400>;
1167 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
1170 clocks = <&ccu CLK_APB1_UART5>;
1171 status = "disabled";
1174 uart6: serial@1c29800 {
1175 compatible = "snps,dw-apb-uart";
1176 reg = <0x01c29800 0x400>;
1177 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
1180 clocks = <&ccu CLK_APB1_UART6>;
1181 status = "disabled";
1184 uart7: serial@1c29c00 {
1185 compatible = "snps,dw-apb-uart";
1186 reg = <0x01c29c00 0x400>;
1187 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
1190 clocks = <&ccu CLK_APB1_UART7>;
1191 status = "disabled";
1195 compatible = "allwinner,sun4i-a10-ps2";
1196 reg = <0x01c2a000 0x400>;
1197 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
1198 clocks = <&ccu CLK_APB1_PS20>;
1199 status = "disabled";
1203 compatible = "allwinner,sun4i-a10-ps2";
1204 reg = <0x01c2a400 0x400>;
1205 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
1206 clocks = <&ccu CLK_APB1_PS21>;
1207 status = "disabled";
1211 compatible = "allwinner,sun7i-a20-i2c",
1212 "allwinner,sun4i-a10-i2c";
1213 reg = <0x01c2ac00 0x400>;
1214 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
1215 clocks = <&ccu CLK_APB1_I2C0>;
1216 status = "disabled";
1217 #address-cells = <1>;
1222 compatible = "allwinner,sun7i-a20-i2c",
1223 "allwinner,sun4i-a10-i2c";
1224 reg = <0x01c2b000 0x400>;
1225 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
1226 clocks = <&ccu CLK_APB1_I2C1>;
1227 status = "disabled";
1228 #address-cells = <1>;
1233 compatible = "allwinner,sun7i-a20-i2c",
1234 "allwinner,sun4i-a10-i2c";
1235 reg = <0x01c2b400 0x400>;
1236 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
1237 clocks = <&ccu CLK_APB1_I2C2>;
1238 status = "disabled";
1239 #address-cells = <1>;
1244 compatible = "allwinner,sun7i-a20-i2c",
1245 "allwinner,sun4i-a10-i2c";
1246 reg = <0x01c2b800 0x400>;
1247 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
1248 clocks = <&ccu CLK_APB1_I2C3>;
1249 status = "disabled";
1250 #address-cells = <1>;
1255 compatible = "allwinner,sun7i-a20-can",
1256 "allwinner,sun4i-a10-can";
1257 reg = <0x01c2bc00 0x400>;
1258 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
1259 clocks = <&ccu CLK_APB1_CAN>;
1260 status = "disabled";
1264 compatible = "allwinner,sun7i-a20-i2c",
1265 "allwinner,sun4i-a10-i2c";
1266 reg = <0x01c2c000 0x400>;
1267 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
1268 clocks = <&ccu CLK_APB1_I2C4>;
1269 status = "disabled";
1270 #address-cells = <1>;
1275 compatible = "allwinner,sun7i-a20-mali", "arm,mali-400";
1276 reg = <0x01c40000 0x10000>;
1277 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
1278 <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
1279 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>,
1280 <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
1281 <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
1282 <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>,
1283 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
1284 interrupt-names = "gp",
1291 clocks = <&ccu CLK_AHB_GPU>, <&ccu CLK_GPU>;
1292 clock-names = "bus", "core";
1293 resets = <&ccu RST_GPU>;
1295 assigned-clocks = <&ccu CLK_GPU>;
1296 assigned-clock-rates = <384000000>;
1299 gmac: ethernet@1c50000 {
1300 compatible = "allwinner,sun7i-a20-gmac";
1301 reg = <0x01c50000 0x10000>;
1302 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
1303 interrupt-names = "macirq";
1304 clocks = <&ccu CLK_AHB_GMAC>, <&gmac_tx_clk>;
1305 clock-names = "stmmaceth", "allwinner_gmac_tx";
1308 snps,force_sf_dma_mode;
1309 status = "disabled";
1310 #address-cells = <1>;
1315 compatible = "allwinner,sun7i-a20-hstimer";
1316 reg = <0x01c60000 0x1000>;
1317 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>,
1318 <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>,
1319 <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>,
1320 <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
1321 clocks = <&ccu CLK_AHB_HSTIMER>;
1324 gic: interrupt-controller@1c81000 {
1325 compatible = "arm,gic-400", "arm,cortex-a7-gic", "arm,cortex-a15-gic";
1326 reg = <0x01c81000 0x1000>,
1327 <0x01c82000 0x2000>,
1328 <0x01c84000 0x2000>,
1329 <0x01c86000 0x2000>;
1330 interrupt-controller;
1331 #interrupt-cells = <3>;
1332 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
1335 fe0: display-frontend@1e00000 {
1336 compatible = "allwinner,sun7i-a20-display-frontend";
1337 reg = <0x01e00000 0x20000>;
1338 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
1339 clocks = <&ccu CLK_AHB_DE_FE0>, <&ccu CLK_DE_FE0>,
1340 <&ccu CLK_DRAM_DE_FE0>;
1341 clock-names = "ahb", "mod",
1343 resets = <&ccu RST_DE_FE0>;
1346 #address-cells = <1>;
1350 #address-cells = <1>;
1354 fe0_out_be0: endpoint@0 {
1356 remote-endpoint = <&be0_in_fe0>;
1359 fe0_out_be1: endpoint@1 {
1361 remote-endpoint = <&be1_in_fe0>;
1367 fe1: display-frontend@1e20000 {
1368 compatible = "allwinner,sun7i-a20-display-frontend";
1369 reg = <0x01e20000 0x20000>;
1370 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
1371 clocks = <&ccu CLK_AHB_DE_FE1>, <&ccu CLK_DE_FE1>,
1372 <&ccu CLK_DRAM_DE_FE1>;
1373 clock-names = "ahb", "mod",
1375 resets = <&ccu RST_DE_FE1>;
1378 #address-cells = <1>;
1382 #address-cells = <1>;
1386 fe1_out_be0: endpoint@0 {
1388 remote-endpoint = <&be0_in_fe1>;
1391 fe1_out_be1: endpoint@1 {
1393 remote-endpoint = <&be1_in_fe1>;
1399 be1: display-backend@1e40000 {
1400 compatible = "allwinner,sun7i-a20-display-backend";
1401 reg = <0x01e40000 0x10000>;
1402 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
1403 clocks = <&ccu CLK_AHB_DE_BE1>, <&ccu CLK_DE_BE1>,
1404 <&ccu CLK_DRAM_DE_BE1>;
1405 clock-names = "ahb", "mod",
1407 resets = <&ccu RST_DE_BE1>;
1410 #address-cells = <1>;
1414 #address-cells = <1>;
1418 be1_in_fe0: endpoint@0 {
1420 remote-endpoint = <&fe0_out_be1>;
1423 be1_in_fe1: endpoint@1 {
1425 remote-endpoint = <&fe1_out_be1>;
1430 #address-cells = <1>;
1434 be1_out_tcon0: endpoint@0 {
1436 remote-endpoint = <&tcon0_in_be1>;
1439 be1_out_tcon1: endpoint@1 {
1441 remote-endpoint = <&tcon1_in_be1>;
1447 be0: display-backend@1e60000 {
1448 compatible = "allwinner,sun7i-a20-display-backend";
1449 reg = <0x01e60000 0x10000>;
1450 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
1451 clocks = <&ccu CLK_AHB_DE_BE0>, <&ccu CLK_DE_BE0>,
1452 <&ccu CLK_DRAM_DE_BE0>;
1453 clock-names = "ahb", "mod",
1455 resets = <&ccu RST_DE_BE0>;
1458 #address-cells = <1>;
1462 #address-cells = <1>;
1466 be0_in_fe0: endpoint@0 {
1468 remote-endpoint = <&fe0_out_be0>;
1471 be0_in_fe1: endpoint@1 {
1473 remote-endpoint = <&fe1_out_be0>;
1478 #address-cells = <1>;
1482 be0_out_tcon0: endpoint@0 {
1484 remote-endpoint = <&tcon0_in_be0>;
1487 be0_out_tcon1: endpoint@1 {
1489 remote-endpoint = <&tcon1_in_be0>;