2 * Copyright 2014 Chen-Yu Tsai
4 * Chen-Yu Tsai <wens@csie.org>
6 * This file is dual-licensed: you can use it either under the terms
7 * of the GPL or the X11 license, at your option. Note that this dual
8 * licensing only applies to this file, and not this project as a
11 * a) This file is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of the
14 * License, or (at your option) any later version.
16 * This file is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
23 * b) Permission is hereby granted, free of charge, to any person
24 * obtaining a copy of this software and associated documentation
25 * files (the "Software"), to deal in the Software without
26 * restriction, including without limitation the rights to use,
27 * copy, modify, merge, publish, distribute, sublicense, and/or
28 * sell copies of the Software, and to permit persons to whom the
29 * Software is furnished to do so, subject to the following
32 * The above copyright notice and this permission notice shall be
33 * included in all copies or substantial portions of the Software.
35 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
36 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
37 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
38 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
39 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
40 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
41 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
42 * OTHER DEALINGS IN THE SOFTWARE.
45 #include "sun8i-a23-a33.dtsi"
46 #include <dt-bindings/thermal/thermal.h>
49 cpu0_opp_table: opp_table0 {
50 compatible = "operating-points-v2";
54 opp-hz = /bits/ 64 <120000000>;
55 opp-microvolt = <1040000>;
56 clock-latency-ns = <244144>; /* 8 32k periods */
60 opp-hz = /bits/ 64 <240000000>;
61 opp-microvolt = <1040000>;
62 clock-latency-ns = <244144>; /* 8 32k periods */
66 opp-hz = /bits/ 64 <312000000>;
67 opp-microvolt = <1040000>;
68 clock-latency-ns = <244144>; /* 8 32k periods */
72 opp-hz = /bits/ 64 <408000000>;
73 opp-microvolt = <1040000>;
74 clock-latency-ns = <244144>; /* 8 32k periods */
78 opp-hz = /bits/ 64 <480000000>;
79 opp-microvolt = <1040000>;
80 clock-latency-ns = <244144>; /* 8 32k periods */
84 opp-hz = /bits/ 64 <504000000>;
85 opp-microvolt = <1040000>;
86 clock-latency-ns = <244144>; /* 8 32k periods */
90 opp-hz = /bits/ 64 <600000000>;
91 opp-microvolt = <1040000>;
92 clock-latency-ns = <244144>; /* 8 32k periods */
96 opp-hz = /bits/ 64 <648000000>;
97 opp-microvolt = <1040000>;
98 clock-latency-ns = <244144>; /* 8 32k periods */
102 opp-hz = /bits/ 64 <720000000>;
103 opp-microvolt = <1100000>;
104 clock-latency-ns = <244144>; /* 8 32k periods */
108 opp-hz = /bits/ 64 <816000000>;
109 opp-microvolt = <1100000>;
110 clock-latency-ns = <244144>; /* 8 32k periods */
114 opp-hz = /bits/ 64 <912000000>;
115 opp-microvolt = <1200000>;
116 clock-latency-ns = <244144>; /* 8 32k periods */
120 opp-hz = /bits/ 64 <1008000000>;
121 opp-microvolt = <1200000>;
122 clock-latency-ns = <244144>; /* 8 32k periods */
128 clocks = <&ccu CLK_CPUX>;
130 operating-points-v2 = <&cpu0_opp_table>;
131 #cooling-cells = <2>;
135 clocks = <&ccu CLK_CPUX>;
137 operating-points-v2 = <&cpu0_opp_table>;
138 #cooling-cells = <2>;
142 compatible = "arm,cortex-a7";
145 clocks = <&ccu CLK_CPUX>;
147 operating-points-v2 = <&cpu0_opp_table>;
148 #cooling-cells = <2>;
152 compatible = "arm,cortex-a7";
155 clocks = <&ccu CLK_CPUX>;
157 operating-points-v2 = <&cpu0_opp_table>;
158 #cooling-cells = <2>;
163 compatible = "allwinner,sun8i-a33-display-engine";
164 allwinner,pipelines = <&fe0>;
169 compatible = "iio-hwmon";
170 io-channels = <&ths>;
173 mali_opp_table: gpu-opp-table {
174 compatible = "operating-points-v2";
177 opp-hz = /bits/ 64 <144000000>;
181 opp-hz = /bits/ 64 <240000000>;
185 opp-hz = /bits/ 64 <384000000>;
190 reg = <0x40000000 0x80000000>;
194 #address-cells = <1>;
198 /* Address must be kept in the lower 256 MiBs of DRAM for VE. */
199 cma_pool: cma@4a000000 {
200 compatible = "shared-dma-pool";
202 alloc-ranges = <0x4a000000 0x6000000>;
209 compatible = "simple-audio-card";
210 simple-audio-card,name = "sun8i-a33-audio";
211 simple-audio-card,format = "i2s";
212 simple-audio-card,frame-master = <&link_codec>;
213 simple-audio-card,bitclock-master = <&link_codec>;
214 simple-audio-card,mclk-fs = <512>;
215 simple-audio-card,aux-devs = <&codec_analog>;
216 simple-audio-card,routing =
217 "Left DAC", "AIF1 Slot 0 Left",
218 "Right DAC", "AIF1 Slot 0 Right";
221 simple-audio-card,cpu {
225 link_codec: simple-audio-card,codec {
226 sound-dai = <&codec>;
231 tcon0: lcd-controller@1c0c000 {
232 compatible = "allwinner,sun8i-a33-tcon";
233 reg = <0x01c0c000 0x1000>;
234 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
235 clocks = <&ccu CLK_BUS_LCD>,
239 clock-output-names = "tcon-pixel-clock";
240 resets = <&ccu RST_BUS_LCD>;
245 #address-cells = <1>;
249 #address-cells = <1>;
253 tcon0_in_drc0: endpoint@0 {
255 remote-endpoint = <&drc0_out_tcon0>;
260 #address-cells = <1>;
264 tcon0_out_dsi: endpoint@1 {
266 remote-endpoint = <&dsi_in_tcon0>;
272 video-codec@01c0e000 {
273 compatible = "allwinner,sun8i-a33-video-engine";
274 reg = <0x01c0e000 0x1000>;
275 clocks = <&ccu CLK_BUS_VE>, <&ccu CLK_VE>,
277 clock-names = "ahb", "mod", "ram";
278 resets = <&ccu RST_BUS_VE>;
279 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
280 allwinner,sram = <&ve_sram 1>;
283 crypto: crypto-engine@1c15000 {
284 compatible = "allwinner,sun4i-a10-crypto";
285 reg = <0x01c15000 0x1000>;
286 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
287 clocks = <&ccu CLK_BUS_SS>, <&ccu CLK_SS>;
288 clock-names = "ahb", "mod";
289 resets = <&ccu RST_BUS_SS>;
294 #sound-dai-cells = <0>;
295 compatible = "allwinner,sun6i-a31-i2s";
296 reg = <0x01c22c00 0x200>;
297 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
298 clocks = <&ccu CLK_BUS_CODEC>, <&ccu CLK_AC_DIG>;
299 clock-names = "apb", "mod";
300 resets = <&ccu RST_BUS_CODEC>;
301 dmas = <&dma 15>, <&dma 15>;
302 dma-names = "rx", "tx";
306 codec: codec@1c22e00 {
307 #sound-dai-cells = <0>;
308 compatible = "allwinner,sun8i-a33-codec";
309 reg = <0x01c22e00 0x400>;
310 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
311 clocks = <&ccu CLK_BUS_CODEC>, <&ccu CLK_AC_DIG>;
312 clock-names = "bus", "mod";
317 compatible = "allwinner,sun8i-a33-ths";
318 reg = <0x01c25000 0x100>;
319 #thermal-sensor-cells = <0>;
320 #io-channel-cells = <0>;
324 compatible = "allwinner,sun6i-a31-mipi-dsi";
325 reg = <0x01ca0000 0x1000>;
326 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
327 clocks = <&ccu CLK_BUS_MIPI_DSI>,
329 clock-names = "bus", "mod";
330 resets = <&ccu RST_BUS_MIPI_DSI>;
336 #address-cells = <1>;
340 #address-cells = <1>;
344 dsi_in_tcon0: endpoint {
345 remote-endpoint = <&tcon0_out_dsi>;
351 dphy: d-phy@1ca1000 {
352 compatible = "allwinner,sun6i-a31-mipi-dphy";
353 reg = <0x01ca1000 0x1000>;
354 clocks = <&ccu CLK_BUS_MIPI_DSI>,
356 clock-names = "bus", "mod";
357 resets = <&ccu RST_BUS_MIPI_DSI>;
362 fe0: display-frontend@1e00000 {
363 compatible = "allwinner,sun8i-a33-display-frontend";
364 reg = <0x01e00000 0x20000>;
365 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
366 clocks = <&ccu CLK_BUS_DE_FE>, <&ccu CLK_DE_FE>,
367 <&ccu CLK_DRAM_DE_FE>;
368 clock-names = "ahb", "mod",
370 resets = <&ccu RST_BUS_DE_FE>;
373 #address-cells = <1>;
377 #address-cells = <1>;
381 fe0_out_be0: endpoint@0 {
383 remote-endpoint = <&be0_in_fe0>;
389 be0: display-backend@1e60000 {
390 compatible = "allwinner,sun8i-a33-display-backend";
391 reg = <0x01e60000 0x10000>, <0x01e80000 0x1000>;
392 reg-names = "be", "sat";
393 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
394 clocks = <&ccu CLK_BUS_DE_BE>, <&ccu CLK_DE_BE>,
395 <&ccu CLK_DRAM_DE_BE>, <&ccu CLK_BUS_SAT>;
396 clock-names = "ahb", "mod",
398 resets = <&ccu RST_BUS_DE_BE>, <&ccu RST_BUS_SAT>;
399 reset-names = "be", "sat";
400 assigned-clocks = <&ccu CLK_DE_BE>;
401 assigned-clock-rates = <300000000>;
404 #address-cells = <1>;
408 #address-cells = <1>;
412 be0_in_fe0: endpoint@0 {
414 remote-endpoint = <&fe0_out_be0>;
419 #address-cells = <1>;
423 be0_out_drc0: endpoint@0 {
425 remote-endpoint = <&drc0_in_be0>;
432 compatible = "allwinner,sun8i-a33-drc";
433 reg = <0x01e70000 0x10000>;
434 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
435 clocks = <&ccu CLK_BUS_DRC>, <&ccu CLK_DRC>,
437 clock-names = "ahb", "mod", "ram";
438 resets = <&ccu RST_BUS_DRC>;
440 assigned-clocks = <&ccu CLK_DRC>;
441 assigned-clock-rates = <300000000>;
444 #address-cells = <1>;
448 #address-cells = <1>;
452 drc0_in_be0: endpoint@0 {
454 remote-endpoint = <&be0_out_drc0>;
459 #address-cells = <1>;
463 drc0_out_tcon0: endpoint@0 {
465 remote-endpoint = <&tcon0_in_drc0>;
475 polling-delay-passive = <250>;
476 polling-delay = <1000>;
477 thermal-sensors = <&ths>;
481 trip = <&cpu_alert0>;
482 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
485 trip = <&cpu_alert1>;
486 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
490 trip = <&gpu_alert0>;
491 cooling-device = <&mali 1 THERMAL_NO_LIMIT>;
495 trip = <&gpu_alert1>;
496 cooling-device = <&mali 2 THERMAL_NO_LIMIT>;
501 cpu_alert0: cpu_alert0 {
503 temperature = <75000>;
508 gpu_alert0: gpu_alert0 {
510 temperature = <85000>;
515 cpu_alert1: cpu_alert1 {
517 temperature = <90000>;
522 gpu_alert1: gpu_alert1 {
524 temperature = <95000>;
531 temperature = <110000>;
541 compatible = "allwinner,sun8i-a33-ccu";
545 operating-points-v2 = <&mali_opp_table>;
549 compatible = "allwinner,sun8i-a33-pinctrl";
550 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
551 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
553 uart0_pins_b: uart0@1 {
561 compatible = "allwinner,sun8i-a33-musb";
565 compatible = "allwinner,sun8i-a33-usb-phy";
566 reg = <0x01c19400 0x14>, <0x01c1a800 0x4>;
567 reg-names = "phy_ctrl", "pmu1";