2 * Copyright 2017 Chen-Yu Tsai
4 * Chen-Yu Tsai <wens@csie.org>
6 * This file is dual-licensed: you can use it either under the terms
7 * of the GPL or the X11 license, at your option. Note that this dual
8 * licensing only applies to this file, and not this project as a
11 * a) This file is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of the
14 * License, or (at your option) any later version.
16 * This file is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
23 * b) Permission is hereby granted, free of charge, to any person
24 * obtaining a copy of this software and associated documentation
25 * files (the "Software"), to deal in the Software without
26 * restriction, including without limitation the rights to use,
27 * copy, modify, merge, publish, distribute, sublicense, and/or
28 * sell copies of the Software, and to permit persons to whom the
29 * Software is furnished to do so, subject to the following
32 * The above copyright notice and this permission notice shall be
33 * included in all copies or substantial portions of the Software.
35 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
36 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
37 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
38 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
39 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
40 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
41 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
42 * OTHER DEALINGS IN THE SOFTWARE.
46 #include "sun8i-a83t.dtsi"
48 #include <dt-bindings/gpio/gpio.h>
51 model = "Banana Pi BPI-M3";
52 compatible = "sinovoip,bpi-m3", "allwinner,sun8i-a83t";
60 stdout-path = "serial0:115200n8";
63 reg_usb1_vbus: reg-usb1-vbus {
64 compatible = "regulator-fixed";
65 regulator-name = "usb1-vbus";
66 regulator-min-microvolt = <5000000>;
67 regulator-max-microvolt = <5000000>;
70 gpio = <&pio 3 24 GPIO_ACTIVE_HIGH>; /* PD24 */
73 wifi_pwrseq: wifi_pwrseq {
74 compatible = "mmc-pwrseq-simple";
75 clocks = <&ac100_rtc 1>;
76 clock-names = "ext_clock";
77 /* The WiFi low power clock must be 32768 Hz */
78 assigned-clocks = <&ac100_rtc 1>;
79 assigned-clock-rates = <32768>;
80 /* enables internal regulator and de-asserts reset */
81 reset-gpios = <&r_pio 0 2 GPIO_ACTIVE_LOW>; /* PL2 WL-PMU-EN */
86 /* Terminus Tech FE 1.1s 4-port USB 2.0 hub here */
89 /* TODO GL830 USB-to-SATA bridge downstream w/ GPIO power controls */
93 pinctrl-names = "default";
94 pinctrl-0 = <&emac_rgmii_pins>;
95 phy-supply = <®_sw>;
96 phy-handle = <&rgmii_phy>;
98 allwinner,rx-delay-ps = <700>;
99 allwinner,tx-delay-ps = <700>;
104 rgmii_phy: ethernet-phy@1 {
105 compatible = "ethernet-phy-ieee802.3-c22";
111 pinctrl-names = "default";
112 pinctrl-0 = <&mmc0_pins>;
113 vmmc-supply = <®_dcdc1>;
115 cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>; /* PF6 */
121 vmmc-supply = <®_dldo1>;
122 vqmmc-supply = <®_dldo1>;
123 mmc-pwrseq = <&wifi_pwrseq>;
130 compatible = "brcm,bcm4329-fmac";
131 interrupt-parent = <&r_pio>;
132 interrupts = <0 3 IRQ_TYPE_LEVEL_LOW>;
133 interrupt-names = "host-wake";
138 pinctrl-names = "default";
139 pinctrl-0 = <&mmc2_8bit_emmc_pins>;
140 vmmc-supply = <®_dcdc1>;
141 vqmmc-supply = <®_dcdc1>;
152 compatible = "x-powers,axp813";
154 interrupt-parent = <&r_intc>;
155 interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
156 eldoin-supply = <®_dcdc1>;
157 fldoin-supply = <®_dcdc5>;
158 swin-supply = <®_dcdc1>;
159 x-powers,drive-vbus-en;
163 compatible = "x-powers,ac100";
167 compatible = "x-powers,ac100-codec";
168 interrupt-parent = <&r_pio>;
169 interrupts = <0 11 IRQ_TYPE_LEVEL_LOW>; /* PL11 */
171 clock-output-names = "4M_adda";
175 compatible = "x-powers,ac100-rtc";
176 interrupt-parent = <&r_intc>;
177 interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
178 clocks = <&ac100_codec>;
180 clock-output-names = "cko1_rtc",
187 #include "axp81x.dtsi"
191 regulator-min-microvolt = <1800000>;
192 regulator-max-microvolt = <1800000>;
193 regulator-name = "vcc-1v8";
198 regulator-min-microvolt = <1800000>;
199 regulator-max-microvolt = <1800000>;
200 regulator-name = "dram-pll";
205 regulator-min-microvolt = <3000000>;
206 regulator-max-microvolt = <3000000>;
207 regulator-name = "avcc";
211 /* schematics says 3.1V but FEX file says 3.3V */
213 regulator-min-microvolt = <3300000>;
214 regulator-max-microvolt = <3300000>;
215 regulator-name = "vcc-3v3";
220 regulator-min-microvolt = <700000>;
221 regulator-max-microvolt = <1100000>;
222 regulator-name = "vdd-cpua";
227 regulator-min-microvolt = <700000>;
228 regulator-max-microvolt = <1100000>;
229 regulator-name = "vdd-cpub";
233 regulator-min-microvolt = <700000>;
234 regulator-max-microvolt = <1100000>;
235 regulator-name = "vdd-gpu";
240 regulator-min-microvolt = <1200000>;
241 regulator-max-microvolt = <1200000>;
242 regulator-name = "vcc-dram";
247 regulator-min-microvolt = <900000>;
248 regulator-max-microvolt = <900000>;
249 regulator-name = "vdd-sys";
254 * This powers both the WiFi/BT module's main power, I/O supply,
255 * and external pull-ups on all the data lines. It should be set
256 * to the same voltage as the I/O supply (DCDC1 in this case) to
257 * avoid any leakage or mismatch.
259 regulator-min-microvolt = <3300000>;
260 regulator-max-microvolt = <3300000>;
261 regulator-name = "vcc-wifi";
266 regulator-min-microvolt = <2500000>;
267 regulator-max-microvolt = <2500000>;
268 regulator-name = "vcc-pd";
272 regulator-name = "usb0-vbus";
277 regulator-min-microvolt = <1080000>;
278 regulator-max-microvolt = <1320000>;
279 regulator-name = "vdd12-hsic";
284 * Despite the embedded CPUs core not being used in any way,
285 * this must remain on or the system will hang.
288 regulator-min-microvolt = <700000>;
289 regulator-max-microvolt = <1100000>;
290 regulator-name = "vdd-cpus";
294 regulator-name = "vcc-rtc";
299 * The PHY requires 20ms after all voltages
300 * are applied until core logic is ready and
301 * 30ms after the reset pin is de-asserted.
302 * Set a 100ms delay to account for PMIC
303 * ramp time and board traces.
305 regulator-enable-ramp-delay = <100000>;
306 regulator-name = "vcc-ephy";
310 pinctrl-names = "default";
311 pinctrl-0 = <&uart0_pb_pins>;
316 usb1_vbus-supply = <®_usb1_vbus>;