2 * Copyright 2015 Vishnu Patekar
4 * Vishnu Patekar <vishnupatekar0510@gmail.com>
6 * This file is dual-licensed: you can use it either under the terms
7 * of the GPL or the X11 license, at your option. Note that this dual
8 * licensing only applies to this file, and not this project as a
11 * a) This file is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of the
14 * License, or (at your option) any later version.
16 * This file is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
23 * b) Permission is hereby granted, free of charge, to any person
24 * obtaining a copy of this software and associated documentation
25 * files (the "Software"), to deal in the Software without
26 * restriction, including without limitation the rights to use,
27 * copy, modify, merge, publish, distribute, sublicense, and/or
28 * sell copies of the Software, and to permit persons to whom the
29 * Software is furnished to do so, subject to the following
32 * The above copyright notice and this permission notice shall be
33 * included in all copies or substantial portions of the Software.
35 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
36 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
37 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
38 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
39 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
40 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
41 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
42 * OTHER DEALINGS IN THE SOFTWARE.
46 #include "skeleton.dtsi"
48 #include <dt-bindings/interrupt-controller/arm-gic.h>
51 interrupt-parent = <&gic>;
58 compatible = "arm,cortex-a7";
64 compatible = "arm,cortex-a7";
70 compatible = "arm,cortex-a7";
76 compatible = "arm,cortex-a7";
82 compatible = "arm,cortex-a7";
88 compatible = "arm,cortex-a7";
94 compatible = "arm,cortex-a7";
100 compatible = "arm,cortex-a7";
107 compatible = "arm,armv7-timer";
108 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
109 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
110 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
111 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
115 #address-cells = <1>;
119 /* TODO: PRCM block has a mux for this. */
122 compatible = "fixed-clock";
123 clock-frequency = <24000000>;
124 clock-output-names = "osc24M";
128 * This is called "internal OSC" in some places.
129 * It is an internal RC-based oscillator.
130 * TODO: Its controls are in the PRCM block.
134 compatible = "fixed-clock";
135 clock-frequency = <16000000>;
136 clock-output-names = "osc16M";
139 osc16Md512: osc16Md512_clk {
141 compatible = "fixed-factor-clock";
145 clock-output-names = "osc16M-d512";
150 compatible = "simple-bus";
151 #address-cells = <1>;
155 pio: pinctrl@01c20800 {
156 compatible = "allwinner,sun8i-a83t-pinctrl";
157 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
158 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
159 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
160 reg = <0x01c20800 0x400>;
163 interrupt-controller;
164 #interrupt-cells = <3>;
167 mmc0_pins_a: mmc0@0 {
168 pins = "PF0", "PF1", "PF2",
171 drive-strength = <30>;
175 uart0_pins_a: uart0@0 {
180 uart0_pins_b: uart0@1 {
181 pins = "PB9", "PB10";
187 compatible = "allwinner,sun4i-a10-timer";
188 reg = <0x01c20c00 0xa0>;
189 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
190 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
195 compatible = "allwinner,sun6i-a31-wdt";
196 reg = <0x01c20ca0 0x20>;
197 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
201 uart0: serial@01c28000 {
202 compatible = "snps,dw-apb-uart";
203 reg = <0x01c28000 0x400>;
204 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
211 gic: interrupt-controller@01c81000 {
212 compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
213 reg = <0x01c81000 0x1000>,
217 interrupt-controller;
218 #interrupt-cells = <3>;
219 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;