2 * Copyright 2015 Vishnu Patekar
4 * Vishnu Patekar <vishnupatekar0510@gmail.com>
6 * This file is dual-licensed: you can use it either under the terms
7 * of the GPL or the X11 license, at your option. Note that this dual
8 * licensing only applies to this file, and not this project as a
11 * a) This file is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of the
14 * License, or (at your option) any later version.
16 * This file is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
23 * b) Permission is hereby granted, free of charge, to any person
24 * obtaining a copy of this software and associated documentation
25 * files (the "Software"), to deal in the Software without
26 * restriction, including without limitation the rights to use,
27 * copy, modify, merge, publish, distribute, sublicense, and/or
28 * sell copies of the Software, and to permit persons to whom the
29 * Software is furnished to do so, subject to the following
32 * The above copyright notice and this permission notice shall be
33 * included in all copies or substantial portions of the Software.
35 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
36 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
37 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
38 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
39 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
40 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
41 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
42 * OTHER DEALINGS IN THE SOFTWARE.
45 #include <dt-bindings/interrupt-controller/arm-gic.h>
47 #include <dt-bindings/clock/sun8i-a83t-ccu.h>
48 #include <dt-bindings/clock/sun8i-de2.h>
49 #include <dt-bindings/clock/sun8i-r-ccu.h>
50 #include <dt-bindings/reset/sun8i-a83t-ccu.h>
51 #include <dt-bindings/reset/sun8i-de2.h>
52 #include <dt-bindings/reset/sun8i-r-ccu.h>
55 interrupt-parent = <&gic>;
64 clocks = <&ccu CLK_C0CPUX>;
66 compatible = "arm,cortex-a7";
68 operating-points-v2 = <&cpu0_opp_table>;
73 compatible = "arm,cortex-a7";
75 operating-points-v2 = <&cpu0_opp_table>;
80 compatible = "arm,cortex-a7";
82 operating-points-v2 = <&cpu0_opp_table>;
87 compatible = "arm,cortex-a7";
89 operating-points-v2 = <&cpu0_opp_table>;
94 clocks = <&ccu CLK_C1CPUX>;
96 compatible = "arm,cortex-a7";
98 operating-points-v2 = <&cpu1_opp_table>;
103 compatible = "arm,cortex-a7";
105 operating-points-v2 = <&cpu1_opp_table>;
110 compatible = "arm,cortex-a7";
112 operating-points-v2 = <&cpu1_opp_table>;
117 compatible = "arm,cortex-a7";
119 operating-points-v2 = <&cpu1_opp_table>;
125 compatible = "arm,armv7-timer";
126 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
127 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
128 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
129 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
133 #address-cells = <1>;
137 /* TODO: PRCM block has a mux for this. */
140 compatible = "fixed-clock";
141 clock-frequency = <24000000>;
142 clock-accuracy = <50000>;
143 clock-output-names = "osc24M";
147 * This is called "internal OSC" in some places.
148 * It is an internal RC-based oscillator.
149 * TODO: Its controls are in the PRCM block.
153 compatible = "fixed-clock";
154 clock-frequency = <16000000>;
155 clock-output-names = "osc16M";
158 osc16Md512: osc16Md512_clk {
160 compatible = "fixed-factor-clock";
164 clock-output-names = "osc16M-d512";
169 compatible = "allwinner,sun8i-a83t-display-engine";
170 allwinner,pipelines = <&mixer0>, <&mixer1>;
175 reg = <0x40000000 0x80000000>;
176 device_type = "memory";
179 cpu0_opp_table: opp_table0 {
180 compatible = "operating-points-v2";
184 opp-hz = /bits/ 64 <480000000>;
185 opp-microvolt = <840000>;
186 clock-latency-ns = <244144>; /* 8 32k periods */
190 opp-hz = /bits/ 64 <600000000>;
191 opp-microvolt = <840000>;
192 clock-latency-ns = <244144>; /* 8 32k periods */
196 opp-hz = /bits/ 64 <720000000>;
197 opp-microvolt = <840000>;
198 clock-latency-ns = <244144>; /* 8 32k periods */
202 opp-hz = /bits/ 64 <864000000>;
203 opp-microvolt = <840000>;
204 clock-latency-ns = <244144>; /* 8 32k periods */
208 opp-hz = /bits/ 64 <912000000>;
209 opp-microvolt = <840000>;
210 clock-latency-ns = <244144>; /* 8 32k periods */
214 opp-hz = /bits/ 64 <1008000000>;
215 opp-microvolt = <840000>;
216 clock-latency-ns = <244144>; /* 8 32k periods */
220 opp-hz = /bits/ 64 <1128000000>;
221 opp-microvolt = <840000>;
222 clock-latency-ns = <244144>; /* 8 32k periods */
226 opp-hz = /bits/ 64 <1200000000>;
227 opp-microvolt = <840000>;
228 clock-latency-ns = <244144>; /* 8 32k periods */
232 cpu1_opp_table: opp_table1 {
233 compatible = "operating-points-v2";
237 opp-hz = /bits/ 64 <480000000>;
238 opp-microvolt = <840000>;
239 clock-latency-ns = <244144>; /* 8 32k periods */
243 opp-hz = /bits/ 64 <600000000>;
244 opp-microvolt = <840000>;
245 clock-latency-ns = <244144>; /* 8 32k periods */
249 opp-hz = /bits/ 64 <720000000>;
250 opp-microvolt = <840000>;
251 clock-latency-ns = <244144>; /* 8 32k periods */
255 opp-hz = /bits/ 64 <864000000>;
256 opp-microvolt = <840000>;
257 clock-latency-ns = <244144>; /* 8 32k periods */
261 opp-hz = /bits/ 64 <912000000>;
262 opp-microvolt = <840000>;
263 clock-latency-ns = <244144>; /* 8 32k periods */
267 opp-hz = /bits/ 64 <1008000000>;
268 opp-microvolt = <840000>;
269 clock-latency-ns = <244144>; /* 8 32k periods */
273 opp-hz = /bits/ 64 <1128000000>;
274 opp-microvolt = <840000>;
275 clock-latency-ns = <244144>; /* 8 32k periods */
279 opp-hz = /bits/ 64 <1200000000>;
280 opp-microvolt = <840000>;
281 clock-latency-ns = <244144>; /* 8 32k periods */
286 compatible = "simple-bus";
287 #address-cells = <1>;
291 display_clocks: clock@1000000 {
292 compatible = "allwinner,sun8i-a83t-de2-clk";
293 reg = <0x01000000 0x100000>;
294 clocks = <&ccu CLK_PLL_DE>,
298 resets = <&ccu RST_BUS_DE>;
303 mixer0: mixer@1100000 {
304 compatible = "allwinner,sun8i-a83t-de2-mixer-0";
305 reg = <0x01100000 0x100000>;
306 clocks = <&display_clocks CLK_BUS_MIXER0>,
307 <&display_clocks CLK_MIXER0>;
310 resets = <&display_clocks RST_MIXER0>;
313 #address-cells = <1>;
317 #address-cells = <1>;
321 mixer0_out_tcon0: endpoint@0 {
323 remote-endpoint = <&tcon0_in_mixer0>;
329 mixer1: mixer@1200000 {
330 compatible = "allwinner,sun8i-a83t-de2-mixer-1";
331 reg = <0x01200000 0x100000>;
332 clocks = <&display_clocks CLK_BUS_MIXER1>,
333 <&display_clocks CLK_MIXER1>;
336 resets = <&display_clocks RST_WB>;
339 #address-cells = <1>;
345 mixer1_out_tcon1: endpoint {
346 remote-endpoint = <&tcon1_in_mixer1>;
352 syscon: syscon@1c00000 {
353 compatible = "allwinner,sun8i-a83t-system-controller",
355 reg = <0x01c00000 0x1000>;
358 dma: dma-controller@1c02000 {
359 compatible = "allwinner,sun8i-a83t-dma";
360 reg = <0x01c02000 0x1000>;
361 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
362 clocks = <&ccu CLK_BUS_DMA>;
363 resets = <&ccu RST_BUS_DMA>;
367 tcon0: lcd-controller@1c0c000 {
368 compatible = "allwinner,sun8i-a83t-tcon-lcd";
369 reg = <0x01c0c000 0x1000>;
370 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
371 clocks = <&ccu CLK_BUS_TCON0>, <&ccu CLK_TCON0>;
372 clock-names = "ahb", "tcon-ch0";
373 clock-output-names = "tcon-pixel-clock";
374 resets = <&ccu RST_BUS_TCON0>, <&ccu RST_BUS_LVDS>;
375 reset-names = "lcd", "lvds";
378 #address-cells = <1>;
382 #address-cells = <1>;
386 tcon0_in_mixer0: endpoint@0 {
388 remote-endpoint = <&mixer0_out_tcon0>;
393 #address-cells = <1>;
400 tcon1: lcd-controller@1c0d000 {
401 compatible = "allwinner,sun8i-a83t-tcon-tv";
402 reg = <0x01c0d000 0x1000>;
403 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
404 clocks = <&ccu CLK_BUS_TCON1>, <&ccu CLK_TCON1>;
405 clock-names = "ahb", "tcon-ch1";
406 resets = <&ccu RST_BUS_TCON1>;
410 #address-cells = <1>;
416 tcon1_in_mixer1: endpoint {
417 remote-endpoint = <&mixer1_out_tcon1>;
422 #address-cells = <1>;
426 tcon1_out_hdmi: endpoint@1 {
428 remote-endpoint = <&hdmi_in_tcon1>;
435 compatible = "allwinner,sun8i-a83t-mmc",
436 "allwinner,sun7i-a20-mmc";
437 reg = <0x01c0f000 0x1000>;
438 clocks = <&ccu CLK_BUS_MMC0>,
440 <&ccu CLK_MMC0_OUTPUT>,
441 <&ccu CLK_MMC0_SAMPLE>;
446 resets = <&ccu RST_BUS_MMC0>;
448 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
450 #address-cells = <1>;
455 compatible = "allwinner,sun8i-a83t-mmc",
456 "allwinner,sun7i-a20-mmc";
457 reg = <0x01c10000 0x1000>;
458 clocks = <&ccu CLK_BUS_MMC1>,
460 <&ccu CLK_MMC1_OUTPUT>,
461 <&ccu CLK_MMC1_SAMPLE>;
466 resets = <&ccu RST_BUS_MMC1>;
468 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
469 pinctrl-names = "default";
470 pinctrl-0 = <&mmc1_pins>;
472 #address-cells = <1>;
477 compatible = "allwinner,sun8i-a83t-emmc";
478 reg = <0x01c11000 0x1000>;
479 clocks = <&ccu CLK_BUS_MMC2>,
481 <&ccu CLK_MMC2_OUTPUT>,
482 <&ccu CLK_MMC2_SAMPLE>;
487 resets = <&ccu RST_BUS_MMC2>;
489 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
491 #address-cells = <1>;
495 usb_otg: usb@1c19000 {
496 compatible = "allwinner,sun8i-a83t-musb",
497 "allwinner,sun8i-a33-musb";
498 reg = <0x01c19000 0x0400>;
499 clocks = <&ccu CLK_BUS_OTG>;
500 resets = <&ccu RST_BUS_OTG>;
501 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
502 interrupt-names = "mc";
505 extcon = <&usbphy 0>;
509 usbphy: phy@1c19400 {
510 compatible = "allwinner,sun8i-a83t-usb-phy";
511 reg = <0x01c19400 0x10>,
514 reg-names = "phy_ctrl",
517 clocks = <&ccu CLK_USB_PHY0>,
520 <&ccu CLK_USB_HSIC_12M>;
521 clock-names = "usb0_phy",
525 resets = <&ccu RST_USB_PHY0>,
528 reset-names = "usb0_reset",
536 compatible = "allwinner,sun8i-a83t-ehci",
538 reg = <0x01c1a000 0x100>;
539 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
540 clocks = <&ccu CLK_BUS_EHCI0>;
541 resets = <&ccu RST_BUS_EHCI0>;
548 compatible = "allwinner,sun8i-a83t-ohci",
550 reg = <0x01c1a400 0x100>;
551 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
552 clocks = <&ccu CLK_BUS_OHCI0>, <&ccu CLK_USB_OHCI0>;
553 resets = <&ccu RST_BUS_OHCI0>;
560 compatible = "allwinner,sun8i-a83t-ehci",
562 reg = <0x01c1b000 0x100>;
563 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
564 clocks = <&ccu CLK_BUS_EHCI1>;
565 resets = <&ccu RST_BUS_EHCI1>;
572 compatible = "allwinner,sun8i-a83t-ccu";
573 reg = <0x01c20000 0x400>;
574 clocks = <&osc24M>, <&osc16Md512>;
575 clock-names = "hosc", "losc";
580 pio: pinctrl@1c20800 {
581 compatible = "allwinner,sun8i-a83t-pinctrl";
582 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
583 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
584 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
585 reg = <0x01c20800 0x400>;
586 clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&osc16Md512>;
587 clock-names = "apb", "hosc", "losc";
589 interrupt-controller;
590 #interrupt-cells = <3>;
593 emac_rgmii_pins: emac-rgmii-pins {
594 pins = "PD2", "PD3", "PD4", "PD5", "PD6", "PD7",
595 "PD11", "PD12", "PD13", "PD14", "PD18",
596 "PD19", "PD21", "PD22", "PD23";
599 * data lines in RGMII mode use DDR mode
600 * and need a higher signal drive strength
602 drive-strength = <40>;
605 hdmi_pins: hdmi-pins {
606 pins = "PH6", "PH7", "PH8";
610 i2c0_pins: i2c0-pins {
615 i2c1_pins: i2c1-pins {
620 i2c2_ph_pins: i2c2-ph-pins {
625 i2s1_pins: i2s1-pins {
626 /* I2S1 does not have external MCLK pin */
627 pins = "PG10", "PG11", "PG12", "PG13";
631 lcd_lvds_pins: lcd-lvds-pins {
632 pins = "PD18", "PD19", "PD20", "PD21", "PD22",
633 "PD23", "PD24", "PD25", "PD26", "PD27";
637 mmc0_pins: mmc0-pins {
638 pins = "PF0", "PF1", "PF2",
641 drive-strength = <30>;
645 mmc1_pins: mmc1-pins {
646 pins = "PG0", "PG1", "PG2",
649 drive-strength = <30>;
653 mmc2_8bit_emmc_pins: mmc2-8bit-emmc-pins {
654 pins = "PC5", "PC6", "PC8", "PC9",
655 "PC10", "PC11", "PC12", "PC13",
656 "PC14", "PC15", "PC16";
658 drive-strength = <30>;
667 spdif_tx_pin: spdif-tx-pin {
672 uart0_pb_pins: uart0-pb-pins {
673 pins = "PB9", "PB10";
677 uart0_pf_pins: uart0-pf-pins {
682 uart1_pins: uart1-pins {
687 uart1_rts_cts_pins: uart1-rts-cts-pins {
694 compatible = "allwinner,sun4i-a10-timer";
695 reg = <0x01c20c00 0xa0>;
696 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
697 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
702 compatible = "allwinner,sun6i-a31-wdt";
703 reg = <0x01c20ca0 0x20>;
704 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
708 spdif: spdif@1c21000 {
709 #sound-dai-cells = <0>;
710 compatible = "allwinner,sun8i-a83t-spdif",
711 "allwinner,sun8i-h3-spdif";
712 reg = <0x01c21000 0x400>;
713 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
714 clocks = <&ccu CLK_BUS_SPDIF>, <&ccu CLK_SPDIF>;
715 resets = <&ccu RST_BUS_SPDIF>;
716 clock-names = "apb", "spdif";
719 pinctrl-names = "default";
720 pinctrl-0 = <&spdif_tx_pin>;
725 #sound-dai-cells = <0>;
726 compatible = "allwinner,sun8i-a83t-i2s";
727 reg = <0x01c22000 0x400>;
728 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
729 clocks = <&ccu CLK_BUS_I2S0>, <&ccu CLK_I2S0>;
730 clock-names = "apb", "mod";
731 dmas = <&dma 3>, <&dma 3>;
732 resets = <&ccu RST_BUS_I2S0>;
733 dma-names = "rx", "tx";
738 #sound-dai-cells = <0>;
739 compatible = "allwinner,sun8i-a83t-i2s";
740 reg = <0x01c22400 0x400>;
741 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
742 clocks = <&ccu CLK_BUS_I2S1>, <&ccu CLK_I2S1>;
743 clock-names = "apb", "mod";
744 dmas = <&dma 4>, <&dma 4>;
745 resets = <&ccu RST_BUS_I2S1>;
746 dma-names = "rx", "tx";
747 pinctrl-names = "default";
748 pinctrl-0 = <&i2s1_pins>;
753 #sound-dai-cells = <0>;
754 compatible = "allwinner,sun8i-a83t-i2s";
755 reg = <0x01c22800 0x400>;
756 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
757 clocks = <&ccu CLK_BUS_I2S2>, <&ccu CLK_I2S2>;
758 clock-names = "apb", "mod";
760 resets = <&ccu RST_BUS_I2S2>;
766 compatible = "allwinner,sun8i-a83t-pwm",
767 "allwinner,sun8i-h3-pwm";
768 reg = <0x01c21400 0x400>;
774 uart0: serial@1c28000 {
775 compatible = "snps,dw-apb-uart";
776 reg = <0x01c28000 0x400>;
777 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
780 clocks = <&ccu CLK_BUS_UART0>;
781 resets = <&ccu RST_BUS_UART0>;
785 uart1: serial@1c28400 {
786 compatible = "snps,dw-apb-uart";
787 reg = <0x01c28400 0x400>;
788 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
791 clocks = <&ccu CLK_BUS_UART1>;
792 resets = <&ccu RST_BUS_UART1>;
797 compatible = "allwinner,sun8i-a83t-i2c",
798 "allwinner,sun6i-a31-i2c";
799 reg = <0x01c2ac00 0x400>;
800 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
801 clocks = <&ccu CLK_BUS_I2C0>;
802 resets = <&ccu RST_BUS_I2C0>;
803 pinctrl-names = "default";
804 pinctrl-0 = <&i2c0_pins>;
806 #address-cells = <1>;
811 compatible = "allwinner,sun8i-a83t-i2c",
812 "allwinner,sun6i-a31-i2c";
813 reg = <0x01c2b000 0x400>;
814 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
815 clocks = <&ccu CLK_BUS_I2C1>;
816 resets = <&ccu RST_BUS_I2C1>;
817 pinctrl-names = "default";
818 pinctrl-0 = <&i2c1_pins>;
820 #address-cells = <1>;
825 compatible = "allwinner,sun8i-a83t-i2c",
826 "allwinner,sun6i-a31-i2c";
827 reg = <0x01c2b400 0x400>;
828 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
829 clocks = <&ccu CLK_BUS_I2C2>;
830 resets = <&ccu RST_BUS_I2C2>;
832 #address-cells = <1>;
836 emac: ethernet@1c30000 {
837 compatible = "allwinner,sun8i-a83t-emac";
839 reg = <0x01c30000 0x104>;
840 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
841 interrupt-names = "macirq";
843 reset-names = "stmmaceth";
845 clock-names = "stmmaceth";
846 #address-cells = <1>;
851 compatible = "snps,dwmac-mdio";
852 #address-cells = <1>;
857 gic: interrupt-controller@1c81000 {
858 compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
859 reg = <0x01c81000 0x1000>,
863 interrupt-controller;
864 #interrupt-cells = <3>;
865 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
869 compatible = "allwinner,sun8i-a83t-dw-hdmi";
870 reg = <0x01ee0000 0x10000>;
872 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
873 clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_SLOW>,
875 clock-names = "iahb", "isfr", "tmds";
876 resets = <&ccu RST_BUS_HDMI1>;
877 reset-names = "ctrl";
879 phy-names = "hdmi-phy";
880 pinctrl-names = "default";
881 pinctrl-0 = <&hdmi_pins>;
885 #address-cells = <1>;
891 hdmi_in_tcon1: endpoint {
892 remote-endpoint = <&tcon1_out_hdmi>;
902 hdmi_phy: hdmi-phy@1ef0000 {
903 compatible = "allwinner,sun8i-a83t-hdmi-phy";
904 reg = <0x01ef0000 0x10000>;
905 clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_SLOW>;
906 clock-names = "bus", "mod";
907 resets = <&ccu RST_BUS_HDMI0>;
912 r_intc: interrupt-controller@1f00c00 {
913 compatible = "allwinner,sun8i-a83t-r-intc",
914 "allwinner,sun6i-a31-r-intc";
915 interrupt-controller;
916 #interrupt-cells = <2>;
917 reg = <0x01f00c00 0x400>;
918 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
921 r_ccu: clock@1f01400 {
922 compatible = "allwinner,sun8i-a83t-r-ccu";
923 reg = <0x01f01400 0x400>;
924 clocks = <&osc24M>, <&osc16Md512>, <&osc16M>,
926 clock-names = "hosc", "losc", "iosc", "pll-periph";
931 r_pio: pinctrl@1f02c00 {
932 compatible = "allwinner,sun8i-a83t-r-pinctrl";
933 reg = <0x01f02c00 0x400>;
934 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
935 clocks = <&r_ccu CLK_APB0_PIO>, <&osc24M>,
937 clock-names = "apb", "hosc", "losc";
940 interrupt-controller;
941 #interrupt-cells = <3>;
943 r_rsb_pins: r-rsb-pins {
946 drive-strength = <20>;
952 compatible = "allwinner,sun8i-a83t-rsb",
953 "allwinner,sun8i-a23-rsb";
954 reg = <0x01f03400 0x400>;
955 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
956 clocks = <&r_ccu CLK_APB0_RSB>;
957 clock-frequency = <3000000>;
958 resets = <&r_ccu RST_APB0_RSB>;
959 pinctrl-names = "default";
960 pinctrl-0 = <&r_rsb_pins>;
962 #address-cells = <1>;