sys/gnu/dts/arm/sun8i-a83t.dtsi

   1 /*
   2  * Copyright 2015 Vishnu Patekar
   3  *
   4  * Vishnu Patekar <vishnupatekar0510@gmail.com>
   5  *
   6  * This file is dual-licensed: you can use it either under the terms
   7  * of the GPL or the X11 license, at your option. Note that this dual
   8  * licensing only applies to this file, and not this project as a
   9  * whole.
  10  *
  11  *  a) This file is free software; you can redistribute it and/or
  12  *     modify it under the terms of the GNU General Public License as
  13  *     published by the Free Software Foundation; either version 2 of the
  14  *     License, or (at your option) any later version.
  15  *
  16  *     This file is distributed in the hope that it will be useful,
  17  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  18  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  19  *     GNU General Public License for more details.
  20  *
  21  * Or, alternatively,
  22  *
  23  *  b) Permission is hereby granted, free of charge, to any person
  24  *     obtaining a copy of this software and associated documentation
  25  *     files (the "Software"), to deal in the Software without
  26  *     restriction, including without limitation the rights to use,
  27  *     copy, modify, merge, publish, distribute, sublicense, and/or
  28  *     sell copies of the Software, and to permit persons to whom the
  29  *     Software is furnished to do so, subject to the following
  30  *     conditions:
  31  *
  32  *     The above copyright notice and this permission notice shall be
  33  *     included in all copies or substantial portions of the Software.
  34  *
  35  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  36  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  37  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  38  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  39  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  40  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  41  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  42  *     OTHER DEALINGS IN THE SOFTWARE.
  43  */
  44
  45 #include <dt-bindings/interrupt-controller/arm-gic.h>
  46
  47 #include <dt-bindings/clock/sun8i-a83t-ccu.h>
  48 #include <dt-bindings/clock/sun8i-de2.h>
  49 #include <dt-bindings/clock/sun8i-r-ccu.h>
  50 #include <dt-bindings/reset/sun8i-a83t-ccu.h>
  51 #include <dt-bindings/reset/sun8i-de2.h>
  52 #include <dt-bindings/reset/sun8i-r-ccu.h>
  53
  54 / {
  55         interrupt-parent = <&gic>;
  56         #address-cells = <1>;
  57         #size-cells = <1>;
  58
  59         cpus {
  60                 #address-cells = <1>;
  61                 #size-cells = <0>;
  62
  63                 cpu0: cpu@0 {
  64                         clocks = <&ccu CLK_C0CPUX>;
  65                         clock-names = "cpu";
  66                         compatible = "arm,cortex-a7";
  67                         device_type = "cpu";
  68                         operating-points-v2 = <&cpu0_opp_table>;
  69                         reg = <0>;
  70                 };
  71
  72                 cpu@1 {
  73                         compatible = "arm,cortex-a7";
  74                         device_type = "cpu";
  75                         operating-points-v2 = <&cpu0_opp_table>;
  76                         reg = <1>;
  77                 };
  78
  79                 cpu@2 {
  80                         compatible = "arm,cortex-a7";
  81                         device_type = "cpu";
  82                         operating-points-v2 = <&cpu0_opp_table>;
  83                         reg = <2>;
  84                 };
  85
  86                 cpu@3 {
  87                         compatible = "arm,cortex-a7";
  88                         device_type = "cpu";
  89                         operating-points-v2 = <&cpu0_opp_table>;
  90                         reg = <3>;
  91                 };
  92
  93                 cpu100: cpu@100 {
  94                         clocks = <&ccu CLK_C1CPUX>;
  95                         clock-names = "cpu";
  96                         compatible = "arm,cortex-a7";
  97                         device_type = "cpu";
  98                         operating-points-v2 = <&cpu1_opp_table>;
  99                         reg = <0x100>;
 100                 };
 101
 102                 cpu@101 {
 103                         compatible = "arm,cortex-a7";
 104                         device_type = "cpu";
 105                         operating-points-v2 = <&cpu1_opp_table>;
 106                         reg = <0x101>;
 107                 };
 108
 109                 cpu@102 {
 110                         compatible = "arm,cortex-a7";
 111                         device_type = "cpu";
 112                         operating-points-v2 = <&cpu1_opp_table>;
 113                         reg = <0x102>;
 114                 };
 115
 116                 cpu@103 {
 117                         compatible = "arm,cortex-a7";
 118                         device_type = "cpu";
 119                         operating-points-v2 = <&cpu1_opp_table>;
 120                         reg = <0x103>;
 121                 };
 122         };
 123
 124         timer {
 125                 compatible = "arm,armv7-timer";
 126                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
 127                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
 128                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
 129                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
 130         };
 131
 132         clocks {
 133                 #address-cells = <1>;
 134                 #size-cells = <1>;
 135                 ranges;
 136
 137                 /* TODO: PRCM block has a mux for this. */
 138                 osc24M: osc24M_clk {
 139                         #clock-cells = <0>;
 140                         compatible = "fixed-clock";
 141                         clock-frequency = <24000000>;
 142                         clock-accuracy = <50000>;
 143                         clock-output-names = "osc24M";
 144                 };
 145
 146                 /*
 147                  * This is called "internal OSC" in some places.
 148                  * It is an internal RC-based oscillator.
 149                  * TODO: Its controls are in the PRCM block.
 150                  */
 151                 osc16M: osc16M_clk {
 152                         #clock-cells = <0>;
 153                         compatible = "fixed-clock";
 154                         clock-frequency = <16000000>;
 155                         clock-output-names = "osc16M";
 156                 };
 157
 158                 osc16Md512: osc16Md512_clk {
 159                         #clock-cells = <0>;
 160                         compatible = "fixed-factor-clock";
 161                         clock-div = <512>;
 162                         clock-mult = <1>;
 163                         clocks = <&osc16M>;
 164                         clock-output-names = "osc16M-d512";
 165                 };
 166         };
 167
 168         de: display-engine {
 169                 compatible = "allwinner,sun8i-a83t-display-engine";
 170                 allwinner,pipelines = <&mixer0>, <&mixer1>;
 171                 status = "disabled";
 172         };
 173
 174         memory {
 175                 reg = <0x40000000 0x80000000>;
 176                 device_type = "memory";
 177         };
 178
 179         cpu0_opp_table: opp_table0 {
 180                 compatible = "operating-points-v2";
 181                 opp-shared;
 182
 183                 opp-480000000 {
 184                         opp-hz = /bits/ 64 <480000000>;
 185                         opp-microvolt = <840000>;
 186                         clock-latency-ns = <244144>; /* 8 32k periods */
 187                 };
 188
 189                 opp-600000000 {
 190                         opp-hz = /bits/ 64 <600000000>;
 191                         opp-microvolt = <840000>;
 192                         clock-latency-ns = <244144>; /* 8 32k periods */
 193                 };
 194
 195                 opp-720000000 {
 196                         opp-hz = /bits/ 64 <720000000>;
 197                         opp-microvolt = <840000>;
 198                         clock-latency-ns = <244144>; /* 8 32k periods */
 199                 };
 200
 201                 opp-864000000 {
 202                         opp-hz = /bits/ 64 <864000000>;
 203                         opp-microvolt = <840000>;
 204                         clock-latency-ns = <244144>; /* 8 32k periods */
 205                 };
 206
 207                 opp-912000000 {
 208                         opp-hz = /bits/ 64 <912000000>;
 209                         opp-microvolt = <840000>;
 210                         clock-latency-ns = <244144>; /* 8 32k periods */
 211                 };
 212
 213                 opp-1008000000 {
 214                         opp-hz = /bits/ 64 <1008000000>;
 215                         opp-microvolt = <840000>;
 216                         clock-latency-ns = <244144>; /* 8 32k periods */
 217                 };
 218
 219                 opp-1128000000 {
 220                         opp-hz = /bits/ 64 <1128000000>;
 221                         opp-microvolt = <840000>;
 222                         clock-latency-ns = <244144>; /* 8 32k periods */
 223                 };
 224
 225                 opp-1200000000 {
 226                         opp-hz = /bits/ 64 <1200000000>;
 227                         opp-microvolt = <840000>;
 228                         clock-latency-ns = <244144>; /* 8 32k periods */
 229                 };
 230         };
 231
 232         cpu1_opp_table: opp_table1 {
 233                 compatible = "operating-points-v2";
 234                 opp-shared;
 235
 236                 opp-480000000 {
 237                         opp-hz = /bits/ 64 <480000000>;
 238                         opp-microvolt = <840000>;
 239                         clock-latency-ns = <244144>; /* 8 32k periods */
 240                 };
 241
 242                 opp-600000000 {
 243                         opp-hz = /bits/ 64 <600000000>;
 244                         opp-microvolt = <840000>;
 245                         clock-latency-ns = <244144>; /* 8 32k periods */
 246                 };
 247
 248                 opp-720000000 {
 249                         opp-hz = /bits/ 64 <720000000>;
 250                         opp-microvolt = <840000>;
 251                         clock-latency-ns = <244144>; /* 8 32k periods */
 252                 };
 253
 254                 opp-864000000 {
 255                         opp-hz = /bits/ 64 <864000000>;
 256                         opp-microvolt = <840000>;
 257                         clock-latency-ns = <244144>; /* 8 32k periods */
 258                 };
 259
 260                 opp-912000000 {
 261                         opp-hz = /bits/ 64 <912000000>;
 262                         opp-microvolt = <840000>;
 263                         clock-latency-ns = <244144>; /* 8 32k periods */
 264                 };
 265
 266                 opp-1008000000 {
 267                         opp-hz = /bits/ 64 <1008000000>;
 268                         opp-microvolt = <840000>;
 269                         clock-latency-ns = <244144>; /* 8 32k periods */
 270                 };
 271
 272                 opp-1128000000 {
 273                         opp-hz = /bits/ 64 <1128000000>;
 274                         opp-microvolt = <840000>;
 275                         clock-latency-ns = <244144>; /* 8 32k periods */
 276                 };
 277
 278                 opp-1200000000 {
 279                         opp-hz = /bits/ 64 <1200000000>;
 280                         opp-microvolt = <840000>;
 281                         clock-latency-ns = <244144>; /* 8 32k periods */
 282                 };
 283         };
 284
 285         soc {
 286                 compatible = "simple-bus";
 287                 #address-cells = <1>;
 288                 #size-cells = <1>;
 289                 ranges;
 290
 291                 display_clocks: clock@1000000 {
 292                         compatible = "allwinner,sun8i-a83t-de2-clk";
 293                         reg = <0x01000000 0x100000>;
 294                         clocks = <&ccu CLK_PLL_DE>,
 295                                  <&ccu CLK_BUS_DE>;
 296                         clock-names = "mod",
 297                                       "bus";
 298                         resets = <&ccu RST_BUS_DE>;
 299                         #clock-cells = <1>;
 300                         #reset-cells = <1>;
 301                 };
 302
 303                 mixer0: mixer@1100000 {
 304                         compatible = "allwinner,sun8i-a83t-de2-mixer-0";
 305                         reg = <0x01100000 0x100000>;
 306                         clocks = <&display_clocks CLK_BUS_MIXER0>,
 307                                  <&display_clocks CLK_MIXER0>;
 308                         clock-names = "bus",
 309                                       "mod";
 310                         resets = <&display_clocks RST_MIXER0>;
 311
 312                         ports {
 313                                 #address-cells = <1>;
 314                                 #size-cells = <0>;
 315
 316                                 mixer0_out: port@1 {
 317                                         #address-cells = <1>;
 318                                         #size-cells = <0>;
 319                                         reg = <1>;
 320
 321                                         mixer0_out_tcon0: endpoint@0 {
 322                                                 reg = <0>;
 323                                                 remote-endpoint = <&tcon0_in_mixer0>;
 324                                         };
 325                                 };
 326                         };
 327                 };
 328
 329                 mixer1: mixer@1200000 {
 330                         compatible = "allwinner,sun8i-a83t-de2-mixer-1";
 331                         reg = <0x01200000 0x100000>;
 332                         clocks = <&display_clocks CLK_BUS_MIXER1>,
 333                                  <&display_clocks CLK_MIXER1>;
 334                         clock-names = "bus",
 335                                       "mod";
 336                         resets = <&display_clocks RST_WB>;
 337
 338                         ports {
 339                                 #address-cells = <1>;
 340                                 #size-cells = <0>;
 341
 342                                 mixer1_out: port@1 {
 343                                         reg = <1>;
 344
 345                                         mixer1_out_tcon1: endpoint {
 346                                                 remote-endpoint = <&tcon1_in_mixer1>;
 347                                         };
 348                                 };
 349                         };
 350                 };
 351
 352                 syscon: syscon@1c00000 {
 353                         compatible = "allwinner,sun8i-a83t-system-controller",
 354                                 "syscon";
 355                         reg = <0x01c00000 0x1000>;
 356                 };
 357
 358                 dma: dma-controller@1c02000 {
 359                         compatible = "allwinner,sun8i-a83t-dma";
 360                         reg = <0x01c02000 0x1000>;
 361                         interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
 362                         clocks = <&ccu CLK_BUS_DMA>;
 363                         resets = <&ccu RST_BUS_DMA>;
 364                         #dma-cells = <1>;
 365                 };
 366
 367                 tcon0: lcd-controller@1c0c000 {
 368                         compatible = "allwinner,sun8i-a83t-tcon-lcd";
 369                         reg = <0x01c0c000 0x1000>;
 370                         interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
 371                         clocks = <&ccu CLK_BUS_TCON0>, <&ccu CLK_TCON0>;
 372                         clock-names = "ahb", "tcon-ch0";
 373                         clock-output-names = "tcon-pixel-clock";
 374                         resets = <&ccu RST_BUS_TCON0>, <&ccu RST_BUS_LVDS>;
 375                         reset-names = "lcd", "lvds";
 376
 377                         ports {
 378                                 #address-cells = <1>;
 379                                 #size-cells = <0>;
 380
 381                                 tcon0_in: port@0 {
 382                                         #address-cells = <1>;
 383                                         #size-cells = <0>;
 384                                         reg = <0>;
 385
 386                                         tcon0_in_mixer0: endpoint@0 {
 387                                                 reg = <0>;
 388                                                 remote-endpoint = <&mixer0_out_tcon0>;
 389                                         };
 390                                 };
 391
 392                                 tcon0_out: port@1 {
 393                                         #address-cells = <1>;
 394                                         #size-cells = <0>;
 395                                         reg = <1>;
 396                                 };
 397                         };
 398                 };
 399
 400                 tcon1: lcd-controller@1c0d000 {
 401                         compatible = "allwinner,sun8i-a83t-tcon-tv";
 402                         reg = <0x01c0d000 0x1000>;
 403                         interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
 404                         clocks = <&ccu CLK_BUS_TCON1>, <&ccu CLK_TCON1>;
 405                         clock-names = "ahb", "tcon-ch1";
 406                         resets = <&ccu RST_BUS_TCON1>;
 407                         reset-names = "lcd";
 408
 409                         ports {
 410                                 #address-cells = <1>;
 411                                 #size-cells = <0>;
 412
 413                                 tcon1_in: port@0 {
 414                                         reg = <0>;
 415
 416                                         tcon1_in_mixer1: endpoint {
 417                                                 remote-endpoint = <&mixer1_out_tcon1>;
 418                                         };
 419                                 };
 420
 421                                 tcon1_out: port@1 {
 422                                         #address-cells = <1>;
 423                                         #size-cells = <0>;
 424                                         reg = <1>;
 425
 426                                         tcon1_out_hdmi: endpoint@1 {
 427                                                 reg = <1>;
 428                                                 remote-endpoint = <&hdmi_in_tcon1>;
 429                                         };
 430                                 };
 431                         };
 432                 };
 433
 434                 mmc0: mmc@1c0f000 {
 435                         compatible = "allwinner,sun8i-a83t-mmc",
 436                                      "allwinner,sun7i-a20-mmc";
 437                         reg = <0x01c0f000 0x1000>;
 438                         clocks = <&ccu CLK_BUS_MMC0>,
 439                                  <&ccu CLK_MMC0>,
 440                                  <&ccu CLK_MMC0_OUTPUT>,
 441                                  <&ccu CLK_MMC0_SAMPLE>;
 442                         clock-names = "ahb",
 443                                       "mmc",
 444                                       "output",
 445                                       "sample";
 446                         resets = <&ccu RST_BUS_MMC0>;
 447                         reset-names = "ahb";
 448                         interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
 449                         status = "disabled";
 450                         #address-cells = <1>;
 451                         #size-cells = <0>;
 452                 };
 453
 454                 mmc1: mmc@1c10000 {
 455                         compatible = "allwinner,sun8i-a83t-mmc",
 456                                      "allwinner,sun7i-a20-mmc";
 457                         reg = <0x01c10000 0x1000>;
 458                         clocks = <&ccu CLK_BUS_MMC1>,
 459                                  <&ccu CLK_MMC1>,
 460                                  <&ccu CLK_MMC1_OUTPUT>,
 461                                  <&ccu CLK_MMC1_SAMPLE>;
 462                         clock-names = "ahb",
 463                                       "mmc",
 464                                       "output",
 465                                       "sample";
 466                         resets = <&ccu RST_BUS_MMC1>;
 467                         reset-names = "ahb";
 468                         interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
 469                         pinctrl-names = "default";
 470                         pinctrl-0 = <&mmc1_pins>;
 471                         status = "disabled";
 472                         #address-cells = <1>;
 473                         #size-cells = <0>;
 474                 };
 475
 476                 mmc2: mmc@1c11000 {
 477                         compatible = "allwinner,sun8i-a83t-emmc";
 478                         reg = <0x01c11000 0x1000>;
 479                         clocks = <&ccu CLK_BUS_MMC2>,
 480                                  <&ccu CLK_MMC2>,
 481                                  <&ccu CLK_MMC2_OUTPUT>,
 482                                  <&ccu CLK_MMC2_SAMPLE>;
 483                         clock-names = "ahb",
 484                                       "mmc",
 485                                       "output",
 486                                       "sample";
 487                         resets = <&ccu RST_BUS_MMC2>;
 488                         reset-names = "ahb";
 489                         interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
 490                         status = "disabled";
 491                         #address-cells = <1>;
 492                         #size-cells = <0>;
 493                 };
 494
 495                 usb_otg: usb@1c19000 {
 496                         compatible = "allwinner,sun8i-a83t-musb",
 497                                      "allwinner,sun8i-a33-musb";
 498                         reg = <0x01c19000 0x0400>;
 499                         clocks = <&ccu CLK_BUS_OTG>;
 500                         resets = <&ccu RST_BUS_OTG>;
 501                         interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
 502                         interrupt-names = "mc";
 503                         phys = <&usbphy 0>;
 504                         phy-names = "usb";
 505                         extcon = <&usbphy 0>;
 506                         status = "disabled";
 507                 };
 508
 509                 usbphy: phy@1c19400 {
 510                         compatible = "allwinner,sun8i-a83t-usb-phy";
 511                         reg = <0x01c19400 0x10>,
 512                               <0x01c1a800 0x14>,
 513                               <0x01c1b800 0x14>;
 514                         reg-names = "phy_ctrl",
 515                                     "pmu1",
 516                                     "pmu2";
 517                         clocks = <&ccu CLK_USB_PHY0>,
 518                                  <&ccu CLK_USB_PHY1>,
 519                                  <&ccu CLK_USB_HSIC>,
 520                                  <&ccu CLK_USB_HSIC_12M>;
 521                         clock-names = "usb0_phy",
 522                                       "usb1_phy",
 523                                       "usb2_phy",
 524                                       "usb2_hsic_12M";
 525                         resets = <&ccu RST_USB_PHY0>,
 526                                  <&ccu RST_USB_PHY1>,
 527                                  <&ccu RST_USB_HSIC>;
 528                         reset-names = "usb0_reset",
 529                                       "usb1_reset",
 530                                       "usb2_reset";
 531                         status = "disabled";
 532                         #phy-cells = <1>;
 533                 };
 534
 535                 ehci0: usb@1c1a000 {
 536                         compatible = "allwinner,sun8i-a83t-ehci",
 537                                      "generic-ehci";
 538                         reg = <0x01c1a000 0x100>;
 539                         interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
 540                         clocks = <&ccu CLK_BUS_EHCI0>;
 541                         resets = <&ccu RST_BUS_EHCI0>;
 542                         phys = <&usbphy 1>;
 543                         phy-names = "usb";
 544                         status = "disabled";
 545                 };
 546
 547                 ohci0: usb@1c1a400 {
 548                         compatible = "allwinner,sun8i-a83t-ohci",
 549                                      "generic-ohci";
 550                         reg = <0x01c1a400 0x100>;
 551                         interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
 552                         clocks = <&ccu CLK_BUS_OHCI0>, <&ccu CLK_USB_OHCI0>;
 553                         resets = <&ccu RST_BUS_OHCI0>;
 554                         phys = <&usbphy 1>;
 555                         phy-names = "usb";
 556                         status = "disabled";
 557                 };
 558
 559                 ehci1: usb@1c1b000 {
 560                         compatible = "allwinner,sun8i-a83t-ehci",
 561                                      "generic-ehci";
 562                         reg = <0x01c1b000 0x100>;
 563                         interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
 564                         clocks = <&ccu CLK_BUS_EHCI1>;
 565                         resets = <&ccu RST_BUS_EHCI1>;
 566                         phys = <&usbphy 2>;
 567                         phy-names = "usb";
 568                         status = "disabled";
 569                 };
 570
 571                 ccu: clock@1c20000 {
 572                         compatible = "allwinner,sun8i-a83t-ccu";
 573                         reg = <0x01c20000 0x400>;
 574                         clocks = <&osc24M>, <&osc16Md512>;
 575                         clock-names = "hosc", "losc";
 576                         #clock-cells = <1>;
 577                         #reset-cells = <1>;
 578                 };
 579
 580                 pio: pinctrl@1c20800 {
 581                         compatible = "allwinner,sun8i-a83t-pinctrl";
 582                         interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
 583                                      <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
 584                                      <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
 585                         reg = <0x01c20800 0x400>;
 586                         clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&osc16Md512>;
 587                         clock-names = "apb", "hosc", "losc";
 588                         gpio-controller;
 589                         interrupt-controller;
 590                         #interrupt-cells = <3>;
 591                         #gpio-cells = <3>;
 592
 593                         emac_rgmii_pins: emac-rgmii-pins {
 594                                 pins = "PD2", "PD3", "PD4", "PD5", "PD6", "PD7",
 595                                        "PD11", "PD12", "PD13", "PD14", "PD18",
 596                                        "PD19", "PD21", "PD22", "PD23";
 597                                 function = "gmac";
 598                                 /*
 599                                  * data lines in RGMII mode use DDR mode
 600                                  * and need a higher signal drive strength
 601                                  */
 602                                 drive-strength = <40>;
 603                         };
 604
 605                         hdmi_pins: hdmi-pins {
 606                                 pins = "PH6", "PH7", "PH8";
 607                                 function = "hdmi";
 608                         };
 609
 610                         i2c0_pins: i2c0-pins {
 611                                 pins = "PH0", "PH1";
 612                                 function = "i2c0";
 613                         };
 614
 615                         i2c1_pins: i2c1-pins {
 616                                 pins = "PH2", "PH3";
 617                                 function = "i2c1";
 618                         };
 619
 620                         i2c2_ph_pins: i2c2-ph-pins {
 621                                 pins = "PH4", "PH5";
 622                                 function = "i2c2";
 623                         };
 624
 625                         i2s1_pins: i2s1-pins {
 626                                 /* I2S1 does not have external MCLK pin */
 627                                 pins = "PG10", "PG11", "PG12", "PG13";
 628                                 function = "i2s1";
 629                         };
 630
 631                         lcd_lvds_pins: lcd-lvds-pins {
 632                                 pins = "PD18", "PD19", "PD20", "PD21", "PD22",
 633                                        "PD23", "PD24", "PD25", "PD26", "PD27";
 634                                 function = "lvds0";
 635                         };
 636
 637                         mmc0_pins: mmc0-pins {
 638                                 pins = "PF0", "PF1", "PF2",
 639                                        "PF3", "PF4", "PF5";
 640                                 function = "mmc0";
 641                                 drive-strength = <30>;
 642                                 bias-pull-up;
 643                         };
 644
 645                         mmc1_pins: mmc1-pins {
 646                                 pins = "PG0", "PG1", "PG2",
 647                                        "PG3", "PG4", "PG5";
 648                                 function = "mmc1";
 649                                 drive-strength = <30>;
 650                                 bias-pull-up;
 651                         };
 652
 653                         mmc2_8bit_emmc_pins: mmc2-8bit-emmc-pins {
 654                                 pins = "PC5", "PC6", "PC8", "PC9",
 655                                        "PC10", "PC11", "PC12", "PC13",
 656                                        "PC14", "PC15", "PC16";
 657                                 function = "mmc2";
 658                                 drive-strength = <30>;
 659                                 bias-pull-up;
 660                         };
 661
 662                         pwm_pin: pwm-pin {
 663                                 pins = "PD28";
 664                                 function = "pwm";
 665                         };
 666
 667                         spdif_tx_pin: spdif-tx-pin {
 668                                 pins = "PE18";
 669                                 function = "spdif";
 670                         };
 671
 672                         uart0_pb_pins: uart0-pb-pins {
 673                                 pins = "PB9", "PB10";
 674                                 function = "uart0";
 675                         };
 676
 677                         uart0_pf_pins: uart0-pf-pins {
 678                                 pins = "PF2", "PF4";
 679                                 function = "uart0";
 680                         };
 681
 682                         uart1_pins: uart1-pins {
 683                                 pins = "PG6", "PG7";
 684                                 function = "uart1";
 685                         };
 686
 687                         uart1_rts_cts_pins: uart1-rts-cts-pins {
 688                                 pins = "PG8", "PG9";
 689                                 function = "uart1";
 690                         };
 691                 };
 692
 693                 timer@1c20c00 {
 694                         compatible = "allwinner,sun4i-a10-timer";
 695                         reg = <0x01c20c00 0xa0>;
 696                         interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
 697                                      <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
 698                         clocks = <&osc24M>;
 699                 };
 700
 701                 watchdog@1c20ca0 {
 702                         compatible = "allwinner,sun6i-a31-wdt";
 703                         reg = <0x01c20ca0 0x20>;
 704                         interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
 705                         clocks = <&osc24M>;
 706                 };
 707
 708                 spdif: spdif@1c21000 {
 709                         #sound-dai-cells = <0>;
 710                         compatible = "allwinner,sun8i-a83t-spdif",
 711                                      "allwinner,sun8i-h3-spdif";
 712                         reg = <0x01c21000 0x400>;
 713                         interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
 714                         clocks = <&ccu CLK_BUS_SPDIF>, <&ccu CLK_SPDIF>;
 715                         resets = <&ccu RST_BUS_SPDIF>;
 716                         clock-names = "apb", "spdif";
 717                         dmas = <&dma 2>;
 718                         dma-names = "tx";
 719                         pinctrl-names = "default";
 720                         pinctrl-0 = <&spdif_tx_pin>;
 721                         status = "disabled";
 722                 };
 723
 724                 i2s0: i2s@1c22000 {
 725                         #sound-dai-cells = <0>;
 726                         compatible = "allwinner,sun8i-a83t-i2s";
 727                         reg = <0x01c22000 0x400>;
 728                         interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
 729                         clocks = <&ccu CLK_BUS_I2S0>, <&ccu CLK_I2S0>;
 730                         clock-names = "apb", "mod";
 731                         dmas = <&dma 3>, <&dma 3>;
 732                         resets = <&ccu RST_BUS_I2S0>;
 733                         dma-names = "rx", "tx";
 734                         status = "disabled";
 735                 };
 736
 737                 i2s1: i2s@1c22400 {
 738                         #sound-dai-cells = <0>;
 739                         compatible = "allwinner,sun8i-a83t-i2s";
 740                         reg = <0x01c22400 0x400>;
 741                         interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
 742                         clocks = <&ccu CLK_BUS_I2S1>, <&ccu CLK_I2S1>;
 743                         clock-names = "apb", "mod";
 744                         dmas = <&dma 4>, <&dma 4>;
 745                         resets = <&ccu RST_BUS_I2S1>;
 746                         dma-names = "rx", "tx";
 747                         pinctrl-names = "default";
 748                         pinctrl-0 = <&i2s1_pins>;
 749                         status = "disabled";
 750                 };
 751
 752                 i2s2: i2s@1c22800 {
 753                         #sound-dai-cells = <0>;
 754                         compatible = "allwinner,sun8i-a83t-i2s";
 755                         reg = <0x01c22800 0x400>;
 756                         interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
 757                         clocks = <&ccu CLK_BUS_I2S2>, <&ccu CLK_I2S2>;
 758                         clock-names = "apb", "mod";
 759                         dmas = <&dma 27>;
 760                         resets = <&ccu RST_BUS_I2S2>;
 761                         dma-names = "tx";
 762                         status = "disabled";
 763                 };
 764
 765                 pwm: pwm@1c21400 {
 766                         compatible = "allwinner,sun8i-a83t-pwm",
 767                                      "allwinner,sun8i-h3-pwm";
 768                         reg = <0x01c21400 0x400>;
 769                         clocks = <&osc24M>;
 770                         #pwm-cells = <3>;
 771                         status = "disabled";
 772                 };
 773
 774                 uart0: serial@1c28000 {
 775                         compatible = "snps,dw-apb-uart";
 776                         reg = <0x01c28000 0x400>;
 777                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
 778                         reg-shift = <2>;
 779                         reg-io-width = <4>;
 780                         clocks = <&ccu CLK_BUS_UART0>;
 781                         resets = <&ccu RST_BUS_UART0>;
 782                         status = "disabled";
 783                 };
 784
 785                 uart1: serial@1c28400 {
 786                         compatible = "snps,dw-apb-uart";
 787                         reg = <0x01c28400 0x400>;
 788                         interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 789                         reg-shift = <2>;
 790                         reg-io-width = <4>;
 791                         clocks = <&ccu CLK_BUS_UART1>;
 792                         resets = <&ccu RST_BUS_UART1>;
 793                         status = "disabled";
 794                 };
 795
 796                 i2c0: i2c@1c2ac00 {
 797                         compatible = "allwinner,sun8i-a83t-i2c",
 798                                      "allwinner,sun6i-a31-i2c";
 799                         reg = <0x01c2ac00 0x400>;
 800                         interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
 801                         clocks = <&ccu CLK_BUS_I2C0>;
 802                         resets = <&ccu RST_BUS_I2C0>;
 803                         pinctrl-names = "default";
 804                         pinctrl-0 = <&i2c0_pins>;
 805                         status = "disabled";
 806                         #address-cells = <1>;
 807                         #size-cells = <0>;
 808                 };
 809
 810                 i2c1: i2c@1c2b000 {
 811                         compatible = "allwinner,sun8i-a83t-i2c",
 812                                      "allwinner,sun6i-a31-i2c";
 813                         reg = <0x01c2b000 0x400>;
 814                         interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
 815                         clocks = <&ccu CLK_BUS_I2C1>;
 816                         resets = <&ccu RST_BUS_I2C1>;
 817                         pinctrl-names = "default";
 818                         pinctrl-0 = <&i2c1_pins>;
 819                         status = "disabled";
 820                         #address-cells = <1>;
 821                         #size-cells = <0>;
 822                 };
 823
 824                 i2c2: i2c@1c2b400 {
 825                         compatible = "allwinner,sun8i-a83t-i2c",
 826                                      "allwinner,sun6i-a31-i2c";
 827                         reg = <0x01c2b400 0x400>;
 828                         interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
 829                         clocks = <&ccu CLK_BUS_I2C2>;
 830                         resets = <&ccu RST_BUS_I2C2>;
 831                         status = "disabled";
 832                         #address-cells = <1>;
 833                         #size-cells = <0>;
 834                 };
 835
 836                 emac: ethernet@1c30000 {
 837                         compatible = "allwinner,sun8i-a83t-emac";
 838                         syscon = <&syscon>;
 839                         reg = <0x01c30000 0x104>;
 840                         interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
 841                         interrupt-names = "macirq";
 842                         resets = <&ccu 13>;
 843                         reset-names = "stmmaceth";
 844                         clocks = <&ccu 27>;
 845                         clock-names = "stmmaceth";
 846                         #address-cells = <1>;
 847                         #size-cells = <0>;
 848                         status = "disabled";
 849
 850                         mdio: mdio {
 851                                 compatible = "snps,dwmac-mdio";
 852                                 #address-cells = <1>;
 853                                 #size-cells = <0>;
 854                         };
 855                 };
 856
 857                 gic: interrupt-controller@1c81000 {
 858                         compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
 859                         reg = <0x01c81000 0x1000>,
 860                               <0x01c82000 0x2000>,
 861                               <0x01c84000 0x2000>,
 862                               <0x01c86000 0x2000>;
 863                         interrupt-controller;
 864                         #interrupt-cells = <3>;
 865                         interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
 866                 };
 867
 868                 hdmi: hdmi@1ee0000 {
 869                         compatible = "allwinner,sun8i-a83t-dw-hdmi";
 870                         reg = <0x01ee0000 0x10000>;
 871                         reg-io-width = <1>;
 872                         interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
 873                         clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_SLOW>,
 874                                  <&ccu CLK_HDMI>;
 875                         clock-names = "iahb", "isfr", "tmds";
 876                         resets = <&ccu RST_BUS_HDMI1>;
 877                         reset-names = "ctrl";
 878                         phys = <&hdmi_phy>;
 879                         phy-names = "hdmi-phy";
 880                         pinctrl-names = "default";
 881                         pinctrl-0 = <&hdmi_pins>;
 882                         status = "disabled";
 883
 884                         ports {
 885                                 #address-cells = <1>;
 886                                 #size-cells = <0>;
 887
 888                                 hdmi_in: port@0 {
 889                                         reg = <0>;
 890
 891                                         hdmi_in_tcon1: endpoint {
 892                                                 remote-endpoint = <&tcon1_out_hdmi>;
 893                                         };
 894                                 };
 895
 896                                 hdmi_out: port@1 {
 897                                         reg = <1>;
 898                                 };
 899                         };
 900                 };
 901
 902                 hdmi_phy: hdmi-phy@1ef0000 {
 903                         compatible = "allwinner,sun8i-a83t-hdmi-phy";
 904                         reg = <0x01ef0000 0x10000>;
 905                         clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_SLOW>;
 906                         clock-names = "bus", "mod";
 907                         resets = <&ccu RST_BUS_HDMI0>;
 908                         reset-names = "phy";
 909                         #phy-cells = <0>;
 910                 };
 911
 912                 r_intc: interrupt-controller@1f00c00 {
 913                         compatible = "allwinner,sun8i-a83t-r-intc",
 914                                      "allwinner,sun6i-a31-r-intc";
 915                         interrupt-controller;
 916                         #interrupt-cells = <2>;
 917                         reg = <0x01f00c00 0x400>;
 918                         interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 919                 };
 920
 921                 r_ccu: clock@1f01400 {
 922                         compatible = "allwinner,sun8i-a83t-r-ccu";
 923                         reg = <0x01f01400 0x400>;
 924                         clocks = <&osc24M>, <&osc16Md512>, <&osc16M>,
 925                                  <&ccu 6>;
 926                         clock-names = "hosc", "losc", "iosc", "pll-periph";
 927                         #clock-cells = <1>;
 928                         #reset-cells = <1>;
 929                 };
 930
 931                 r_pio: pinctrl@1f02c00 {
 932                         compatible = "allwinner,sun8i-a83t-r-pinctrl";
 933                         reg = <0x01f02c00 0x400>;
 934                         interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
 935                         clocks = <&r_ccu CLK_APB0_PIO>, <&osc24M>,
 936                                  <&osc16Md512>;
 937                         clock-names = "apb", "hosc", "losc";
 938                         gpio-controller;
 939                         #gpio-cells = <3>;
 940                         interrupt-controller;
 941                         #interrupt-cells = <3>;
 942
 943                         r_rsb_pins: r-rsb-pins {
 944                                 pins = "PL0", "PL1";
 945                                 function = "s_rsb";
 946                                 drive-strength = <20>;
 947                                 bias-pull-up;
 948                         };
 949                 };
 950
 951                 r_rsb: rsb@1f03400 {
 952                         compatible = "allwinner,sun8i-a83t-rsb",
 953                                      "allwinner,sun8i-a23-rsb";
 954                         reg = <0x01f03400 0x400>;
 955                         interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
 956                         clocks = <&r_ccu CLK_APB0_RSB>;
 957                         clock-frequency = <3000000>;
 958                         resets = <&r_ccu RST_APB0_RSB>;
 959                         pinctrl-names = "default";
 960                         pinctrl-0 = <&r_rsb_pins>;
 961                         status = "disabled";
 962                         #address-cells = <1>;
 963                         #size-cells = <0>;
 964                 };
 965         };
 966 };