2 * Copyright 2015 Vishnu Patekar
4 * Vishnu Patekar <vishnupatekar0510@gmail.com>
6 * This file is dual-licensed: you can use it either under the terms
7 * of the GPL or the X11 license, at your option. Note that this dual
8 * licensing only applies to this file, and not this project as a
11 * a) This file is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of the
14 * License, or (at your option) any later version.
16 * This file is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
23 * b) Permission is hereby granted, free of charge, to any person
24 * obtaining a copy of this software and associated documentation
25 * files (the "Software"), to deal in the Software without
26 * restriction, including without limitation the rights to use,
27 * copy, modify, merge, publish, distribute, sublicense, and/or
28 * sell copies of the Software, and to permit persons to whom the
29 * Software is furnished to do so, subject to the following
32 * The above copyright notice and this permission notice shall be
33 * included in all copies or substantial portions of the Software.
35 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
36 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
37 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
38 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
39 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
40 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
41 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
42 * OTHER DEALINGS IN THE SOFTWARE.
45 #include <dt-bindings/interrupt-controller/arm-gic.h>
47 #include <dt-bindings/clock/sun8i-a83t-ccu.h>
48 #include <dt-bindings/clock/sun8i-r-ccu.h>
49 #include <dt-bindings/reset/sun8i-a83t-ccu.h>
50 #include <dt-bindings/reset/sun8i-r-ccu.h>
53 interrupt-parent = <&gic>;
62 compatible = "arm,cortex-a7";
68 compatible = "arm,cortex-a7";
74 compatible = "arm,cortex-a7";
80 compatible = "arm,cortex-a7";
86 compatible = "arm,cortex-a7";
92 compatible = "arm,cortex-a7";
98 compatible = "arm,cortex-a7";
104 compatible = "arm,cortex-a7";
111 compatible = "arm,armv7-timer";
112 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
113 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
114 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
115 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
119 #address-cells = <1>;
123 /* TODO: PRCM block has a mux for this. */
126 compatible = "fixed-clock";
127 clock-frequency = <24000000>;
128 clock-accuracy = <50000>;
129 clock-output-names = "osc24M";
133 * This is called "internal OSC" in some places.
134 * It is an internal RC-based oscillator.
135 * TODO: Its controls are in the PRCM block.
139 compatible = "fixed-clock";
140 clock-frequency = <16000000>;
141 clock-output-names = "osc16M";
144 osc16Md512: osc16Md512_clk {
146 compatible = "fixed-factor-clock";
150 clock-output-names = "osc16M-d512";
155 reg = <0x40000000 0x80000000>;
156 device_type = "memory";
160 compatible = "simple-bus";
161 #address-cells = <1>;
165 syscon: syscon@1c00000 {
166 compatible = "allwinner,sun8i-a83t-system-controller",
168 reg = <0x01c00000 0x1000>;
171 dma: dma-controller@1c02000 {
172 compatible = "allwinner,sun8i-a83t-dma";
173 reg = <0x01c02000 0x1000>;
174 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
175 clocks = <&ccu CLK_BUS_DMA>;
176 resets = <&ccu RST_BUS_DMA>;
181 compatible = "allwinner,sun8i-a83t-mmc",
182 "allwinner,sun7i-a20-mmc";
183 reg = <0x01c0f000 0x1000>;
184 clocks = <&ccu CLK_BUS_MMC0>,
186 <&ccu CLK_MMC0_OUTPUT>,
187 <&ccu CLK_MMC0_SAMPLE>;
192 resets = <&ccu RST_BUS_MMC0>;
194 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
196 #address-cells = <1>;
201 compatible = "allwinner,sun8i-a83t-mmc",
202 "allwinner,sun7i-a20-mmc";
203 reg = <0x01c10000 0x1000>;
204 clocks = <&ccu CLK_BUS_MMC1>,
206 <&ccu CLK_MMC1_OUTPUT>,
207 <&ccu CLK_MMC1_SAMPLE>;
212 resets = <&ccu RST_BUS_MMC1>;
214 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
215 pinctrl-names = "default";
216 pinctrl-0 = <&mmc1_pins>;
218 #address-cells = <1>;
223 compatible = "allwinner,sun8i-a83t-emmc";
224 reg = <0x01c11000 0x1000>;
225 clocks = <&ccu CLK_BUS_MMC2>,
227 <&ccu CLK_MMC2_OUTPUT>,
228 <&ccu CLK_MMC2_SAMPLE>;
233 resets = <&ccu RST_BUS_MMC2>;
235 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
237 #address-cells = <1>;
241 usb_otg: usb@1c19000 {
242 compatible = "allwinner,sun8i-a83t-musb",
243 "allwinner,sun8i-a33-musb";
244 reg = <0x01c19000 0x0400>;
245 clocks = <&ccu CLK_BUS_OTG>;
246 resets = <&ccu RST_BUS_OTG>;
247 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
248 interrupt-names = "mc";
251 extcon = <&usbphy 0>;
255 usbphy: phy@1c19400 {
256 compatible = "allwinner,sun8i-a83t-usb-phy";
257 reg = <0x01c19400 0x10>,
260 reg-names = "phy_ctrl",
263 clocks = <&ccu CLK_USB_PHY0>,
266 <&ccu CLK_USB_HSIC_12M>;
267 clock-names = "usb0_phy",
271 resets = <&ccu RST_USB_PHY0>,
274 reset-names = "usb0_reset",
282 compatible = "allwinner,sun8i-a83t-ehci",
284 reg = <0x01c1a000 0x100>;
285 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
286 clocks = <&ccu CLK_BUS_EHCI0>;
287 resets = <&ccu RST_BUS_EHCI0>;
294 compatible = "allwinner,sun8i-a83t-ohci",
296 reg = <0x01c1a400 0x100>;
297 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
298 clocks = <&ccu CLK_BUS_OHCI0>, <&ccu CLK_USB_OHCI0>;
299 resets = <&ccu RST_BUS_OHCI0>;
306 compatible = "allwinner,sun8i-a83t-ehci",
308 reg = <0x01c1b000 0x100>;
309 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
310 clocks = <&ccu CLK_BUS_EHCI1>;
311 resets = <&ccu RST_BUS_EHCI1>;
318 compatible = "allwinner,sun8i-a83t-ccu";
319 reg = <0x01c20000 0x400>;
320 clocks = <&osc24M>, <&osc16Md512>;
321 clock-names = "hosc", "losc";
326 pio: pinctrl@1c20800 {
327 compatible = "allwinner,sun8i-a83t-pinctrl";
328 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
329 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
330 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
331 reg = <0x01c20800 0x400>;
332 clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&osc16Md512>;
333 clock-names = "apb", "hosc", "losc";
335 interrupt-controller;
336 #interrupt-cells = <3>;
339 mmc0_pins: mmc0-pins {
340 pins = "PF0", "PF1", "PF2",
343 drive-strength = <30>;
347 mmc1_pins: mmc1-pins {
348 pins = "PG0", "PG1", "PG2",
351 drive-strength = <30>;
355 mmc2_8bit_emmc_pins: mmc2-8bit-emmc-pins {
356 pins = "PC5", "PC6", "PC8", "PC9",
357 "PC10", "PC11", "PC12", "PC13",
358 "PC14", "PC15", "PC16";
360 drive-strength = <30>;
364 spdif_tx_pin: spdif-tx-pin {
369 uart0_pb_pins: uart0-pb-pins {
370 pins = "PB9", "PB10";
374 uart0_pf_pins: uart0-pf-pins {
379 uart1_pins: uart1-pins {
384 uart1_rts_cts_pins: uart1-rts-cts-pins {
391 compatible = "allwinner,sun4i-a10-timer";
392 reg = <0x01c20c00 0xa0>;
393 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
394 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
399 compatible = "allwinner,sun6i-a31-wdt";
400 reg = <0x01c20ca0 0x20>;
401 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
405 spdif: spdif@1c21000 {
406 #sound-dai-cells = <0>;
407 compatible = "allwinner,sun8i-a83t-spdif",
408 "allwinner,sun8i-h3-spdif";
409 reg = <0x01c21000 0x400>;
410 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
411 clocks = <&ccu CLK_BUS_SPDIF>, <&ccu CLK_SPDIF>;
412 resets = <&ccu RST_BUS_SPDIF>;
413 clock-names = "apb", "spdif";
416 pinctrl-names = "default";
417 pinctrl-0 = <&spdif_tx_pin>;
421 uart0: serial@1c28000 {
422 compatible = "snps,dw-apb-uart";
423 reg = <0x01c28000 0x400>;
424 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
427 clocks = <&ccu CLK_BUS_UART0>;
428 resets = <&ccu RST_BUS_UART0>;
432 uart1: serial@1c28400 {
433 compatible = "snps,dw-apb-uart";
434 reg = <0x01c28400 0x400>;
435 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
438 clocks = <&ccu CLK_BUS_UART1>;
439 resets = <&ccu RST_BUS_UART1>;
443 gic: interrupt-controller@1c81000 {
444 compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
445 reg = <0x01c81000 0x1000>,
449 interrupt-controller;
450 #interrupt-cells = <3>;
451 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
454 r_intc: interrupt-controller@1f00c00 {
455 compatible = "allwinner,sun8i-a83t-r-intc",
456 "allwinner,sun6i-a31-r-intc";
457 interrupt-controller;
458 #interrupt-cells = <2>;
459 reg = <0x01f00c00 0x400>;
460 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
463 r_ccu: clock@1f01400 {
464 compatible = "allwinner,sun8i-a83t-r-ccu";
465 reg = <0x01f01400 0x400>;
466 clocks = <&osc24M>, <&osc16Md512>, <&osc16M>,
468 clock-names = "hosc", "losc", "iosc", "pll-periph";
473 r_pio: pinctrl@1f02c00 {
474 compatible = "allwinner,sun8i-a83t-r-pinctrl";
475 reg = <0x01f02c00 0x400>;
476 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
477 clocks = <&r_ccu CLK_APB0_PIO>, <&osc24M>,
479 clock-names = "apb", "hosc", "losc";
482 interrupt-controller;
483 #interrupt-cells = <3>;
485 r_rsb_pins: r-rsb-pins {
488 drive-strength = <20>;
494 compatible = "allwinner,sun8i-a83t-rsb",
495 "allwinner,sun8i-a23-rsb";
496 reg = <0x01f03400 0x400>;
497 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
498 clocks = <&r_ccu CLK_APB0_RSB>;
499 clock-frequency = <3000000>;
500 resets = <&r_ccu RST_APB0_RSB>;
501 pinctrl-names = "default";
502 pinctrl-0 = <&r_rsb_pins>;
504 #address-cells = <1>;