sys/gnu/dts/arm/sun8i-r40.dtsi

   1 /*
   2  * Copyright 2017 Chen-Yu Tsai <wens@csie.org>
   3  * Copyright 2017 Icenowy Zheng <icenowy@aosc.io>
   4  *
   5  * This file is dual-licensed: you can use it either under the terms
   6  * of the GPL or the X11 license, at your option. Note that this dual
   7  * licensing only applies to this file, and not this project as a
   8  * whole.
   9  *
  10  *  a) This file is free software; you can redistribute it and/or
  11  *     modify it under the terms of the GNU General Public License as
  12  *     published by the Free Software Foundation; either version 2 of the
  13  *     License, or (at your option) any later version.
  14  *
  15  *     This file is distributed in the hope that it will be useful,
  16  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  17  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18  *     GNU General Public License for more details.
  19  *
  20  * Or, alternatively,
  21  *
  22  *  b) Permission is hereby granted, free of charge, to any person
  23  *     obtaining a copy of this software and associated documentation
  24  *     files (the "Software"), to deal in the Software without
  25  *     restriction, including without limitation the rights to use,
  26  *     copy, modify, merge, publish, distribute, sublicense, and/or
  27  *     sell copies of the Software, and to permit persons to whom the
  28  *     Software is furnished to do so, subject to the following
  29  *     conditions:
  30  *
  31  *     The above copyright notice and this permission notice shall be
  32  *     included in all copies or substantial portions of the Software.
  33  *
  34  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  35  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  36  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  37  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  38  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  39  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  40  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  41  *     OTHER DEALINGS IN THE SOFTWARE.
  42  */
  43
  44 #include <dt-bindings/interrupt-controller/arm-gic.h>
  45 #include <dt-bindings/clock/sun8i-de2.h>
  46 #include <dt-bindings/clock/sun8i-r40-ccu.h>
  47 #include <dt-bindings/clock/sun8i-tcon-top.h>
  48 #include <dt-bindings/reset/sun8i-r40-ccu.h>
  49 #include <dt-bindings/reset/sun8i-de2.h>
  50
  51 / {
  52         #address-cells = <1>;
  53         #size-cells = <1>;
  54         interrupt-parent = <&gic>;
  55
  56         clocks {
  57                 #address-cells = <1>;
  58                 #size-cells = <1>;
  59                 ranges;
  60
  61                 osc24M: osc24M {
  62                         #clock-cells = <0>;
  63                         compatible = "fixed-clock";
  64                         clock-frequency = <24000000>;
  65                         clock-accuracy = <50000>;
  66                         clock-output-names = "osc24M";
  67                 };
  68
  69                 osc32k: osc32k {
  70                         #clock-cells = <0>;
  71                         compatible = "fixed-clock";
  72                         clock-frequency = <32768>;
  73                         clock-accuracy = <20000>;
  74                         clock-output-names = "ext-osc32k";
  75                 };
  76         };
  77
  78         cpus {
  79                 #address-cells = <1>;
  80                 #size-cells = <0>;
  81
  82                 cpu0: cpu@0 {
  83                         compatible = "arm,cortex-a7";
  84                         device_type = "cpu";
  85                         reg = <0>;
  86                 };
  87
  88                 cpu1: cpu@1 {
  89                         compatible = "arm,cortex-a7";
  90                         device_type = "cpu";
  91                         reg = <1>;
  92                 };
  93
  94                 cpu2: cpu@2 {
  95                         compatible = "arm,cortex-a7";
  96                         device_type = "cpu";
  97                         reg = <2>;
  98                 };
  99
 100                 cpu3: cpu@3 {
 101                         compatible = "arm,cortex-a7";
 102                         device_type = "cpu";
 103                         reg = <3>;
 104                 };
 105         };
 106
 107         de: display-engine {
 108                 compatible = "allwinner,sun8i-r40-display-engine";
 109                 allwinner,pipelines = <&mixer0>, <&mixer1>;
 110                 status = "disabled";
 111         };
 112
 113         soc {
 114                 compatible = "simple-bus";
 115                 #address-cells = <1>;
 116                 #size-cells = <1>;
 117                 ranges;
 118
 119                 display_clocks: clock@1000000 {
 120                         compatible = "allwinner,sun8i-r40-de2-clk",
 121                                      "allwinner,sun8i-h3-de2-clk";
 122                         reg = <0x01000000 0x100000>;
 123                         clocks = <&ccu CLK_BUS_DE>,
 124                                  <&ccu CLK_DE>;
 125                         clock-names = "bus",
 126                                       "mod";
 127                         resets = <&ccu RST_BUS_DE>;
 128                         #clock-cells = <1>;
 129                         #reset-cells = <1>;
 130                 };
 131
 132                 mixer0: mixer@1100000 {
 133                         compatible = "allwinner,sun8i-r40-de2-mixer-0";
 134                         reg = <0x01100000 0x100000>;
 135                         clocks = <&display_clocks CLK_BUS_MIXER0>,
 136                                  <&display_clocks CLK_MIXER0>;
 137                         clock-names = "bus",
 138                                       "mod";
 139                         resets = <&display_clocks RST_MIXER0>;
 140
 141                         ports {
 142                                 #address-cells = <1>;
 143                                 #size-cells = <0>;
 144
 145                                 mixer0_out: port@1 {
 146                                         reg = <1>;
 147                                         mixer0_out_tcon_top: endpoint {
 148                                                 remote-endpoint = <&tcon_top_mixer0_in_mixer0>;
 149                                         };
 150                                 };
 151                         };
 152                 };
 153
 154                 mixer1: mixer@1200000 {
 155                         compatible = "allwinner,sun8i-r40-de2-mixer-1";
 156                         reg = <0x01200000 0x100000>;
 157                         clocks = <&display_clocks CLK_BUS_MIXER1>,
 158                                  <&display_clocks CLK_MIXER1>;
 159                         clock-names = "bus",
 160                                       "mod";
 161                         resets = <&display_clocks RST_WB>;
 162
 163                         ports {
 164                                 #address-cells = <1>;
 165                                 #size-cells = <0>;
 166
 167                                 mixer1_out: port@1 {
 168                                         reg = <1>;
 169                                         mixer1_out_tcon_top: endpoint {
 170                                                 remote-endpoint = <&tcon_top_mixer1_in_mixer1>;
 171                                         };
 172                                 };
 173                         };
 174                 };
 175
 176                 nmi_intc: interrupt-controller@1c00030 {
 177                         compatible = "allwinner,sun7i-a20-sc-nmi";
 178                         interrupt-controller;
 179                         #interrupt-cells = <2>;
 180                         reg = <0x01c00030 0x0c>;
 181                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
 182                 };
 183
 184                 spi0: spi@1c05000 {
 185                         compatible = "allwinner,sun8i-r40-spi",
 186                                      "allwinner,sun8i-h3-spi";
 187                         reg = <0x01c05000 0x1000>;
 188                         interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 189                         clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>;
 190                         clock-names = "ahb", "mod";
 191                         resets = <&ccu RST_BUS_SPI0>;
 192                         status = "disabled";
 193                         #address-cells = <1>;
 194                         #size-cells = <0>;
 195                 };
 196
 197                 spi1: spi@1c06000 {
 198                         compatible = "allwinner,sun8i-r40-spi",
 199                                      "allwinner,sun8i-h3-spi";
 200                         reg = <0x01c06000 0x1000>;
 201                         interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
 202                         clocks = <&ccu CLK_BUS_SPI1>, <&ccu CLK_SPI1>;
 203                         clock-names = "ahb", "mod";
 204                         resets = <&ccu RST_BUS_SPI1>;
 205                         status = "disabled";
 206                         #address-cells = <1>;
 207                         #size-cells = <0>;
 208                 };
 209
 210                 csi0: csi@1c09000 {
 211                         compatible = "allwinner,sun8i-r40-csi0",
 212                                      "allwinner,sun7i-a20-csi0";
 213                         reg = <0x01c09000 0x1000>;
 214                         interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
 215                         clocks = <&ccu CLK_BUS_CSI0>, <&ccu CLK_CSI_SCLK>,
 216                                  <&ccu CLK_DRAM_CSI0>;
 217                         clock-names = "bus", "isp", "ram";
 218                         resets = <&ccu RST_BUS_CSI0>;
 219                         interconnects = <&mbus 5>;
 220                         interconnect-names = "dma-mem";
 221                         status = "disabled";
 222                 };
 223
 224                 mmc0: mmc@1c0f000 {
 225                         compatible = "allwinner,sun8i-r40-mmc",
 226                                      "allwinner,sun50i-a64-mmc";
 227                         reg = <0x01c0f000 0x1000>;
 228                         clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>;
 229                         clock-names = "ahb", "mmc";
 230                         resets = <&ccu RST_BUS_MMC0>;
 231                         reset-names = "ahb";
 232                         pinctrl-0 = <&mmc0_pins>;
 233                         pinctrl-names = "default";
 234                         interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 235                         status = "disabled";
 236                         #address-cells = <1>;
 237                         #size-cells = <0>;
 238                 };
 239
 240                 mmc1: mmc@1c10000 {
 241                         compatible = "allwinner,sun8i-r40-mmc",
 242                                      "allwinner,sun50i-a64-mmc";
 243                         reg = <0x01c10000 0x1000>;
 244                         clocks = <&ccu CLK_BUS_MMC1>, <&ccu CLK_MMC1>;
 245                         clock-names = "ahb", "mmc";
 246                         resets = <&ccu RST_BUS_MMC1>;
 247                         reset-names = "ahb";
 248                         interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
 249                         status = "disabled";
 250                         #address-cells = <1>;
 251                         #size-cells = <0>;
 252                 };
 253
 254                 mmc2: mmc@1c11000 {
 255                         compatible = "allwinner,sun8i-r40-emmc",
 256                                      "allwinner,sun50i-a64-emmc";
 257                         reg = <0x01c11000 0x1000>;
 258                         clocks = <&ccu CLK_BUS_MMC2>, <&ccu CLK_MMC2>;
 259                         clock-names = "ahb", "mmc";
 260                         resets = <&ccu RST_BUS_MMC2>;
 261                         reset-names = "ahb";
 262                         pinctrl-0 = <&mmc2_pins>;
 263                         pinctrl-names = "default";
 264                         interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
 265                         status = "disabled";
 266                         #address-cells = <1>;
 267                         #size-cells = <0>;
 268                 };
 269
 270                 mmc3: mmc@1c12000 {
 271                         compatible = "allwinner,sun8i-r40-mmc",
 272                                      "allwinner,sun50i-a64-mmc";
 273                         reg = <0x01c12000 0x1000>;
 274                         clocks = <&ccu CLK_BUS_MMC3>, <&ccu CLK_MMC3>;
 275                         clock-names = "ahb", "mmc";
 276                         resets = <&ccu RST_BUS_MMC3>;
 277                         reset-names = "ahb";
 278                         interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 279                         status = "disabled";
 280                         #address-cells = <1>;
 281                         #size-cells = <0>;
 282                 };
 283
 284                 usbphy: phy@1c13400 {
 285                         compatible = "allwinner,sun8i-r40-usb-phy";
 286                         reg = <0x01c13400 0x14>,
 287                               <0x01c14800 0x4>,
 288                               <0x01c19800 0x4>,
 289                               <0x01c1c800 0x4>;
 290                         reg-names = "phy_ctrl",
 291                                     "pmu0",
 292                                     "pmu1",
 293                                     "pmu2";
 294                         clocks = <&ccu CLK_USB_PHY0>,
 295                                  <&ccu CLK_USB_PHY1>,
 296                                  <&ccu CLK_USB_PHY2>;
 297                         clock-names = "usb0_phy",
 298                                       "usb1_phy",
 299                                       "usb2_phy";
 300                         resets = <&ccu RST_USB_PHY0>,
 301                                  <&ccu RST_USB_PHY1>,
 302                                  <&ccu RST_USB_PHY2>;
 303                         reset-names = "usb0_reset",
 304                                       "usb1_reset",
 305                                       "usb2_reset";
 306                         status = "disabled";
 307                         #phy-cells = <1>;
 308                 };
 309
 310                 crypto: crypto@1c15000 {
 311                         compatible = "allwinner,sun8i-r40-crypto";
 312                         reg = <0x01c15000 0x1000>;
 313                         interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
 314                         clocks = <&ccu CLK_BUS_CE>, <&ccu CLK_CE>;
 315                         clock-names = "bus", "mod";
 316                         resets = <&ccu RST_BUS_CE>;
 317                 };
 318
 319                 spi2: spi@1c17000 {
 320                         compatible = "allwinner,sun8i-r40-spi",
 321                                      "allwinner,sun8i-h3-spi";
 322                         reg = <0x01c17000 0x1000>;
 323                         interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
 324                         clocks = <&ccu CLK_BUS_SPI2>, <&ccu CLK_SPI2>;
 325                         clock-names = "ahb", "mod";
 326                         resets = <&ccu RST_BUS_SPI2>;
 327                         status = "disabled";
 328                         #address-cells = <1>;
 329                         #size-cells = <0>;
 330                 };
 331
 332                 ahci: sata@1c18000 {
 333                         compatible = "allwinner,sun8i-r40-ahci";
 334                         reg = <0x01c18000 0x1000>;
 335                         interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
 336                         clocks = <&ccu CLK_BUS_SATA>, <&ccu CLK_SATA>;
 337                         resets = <&ccu RST_BUS_SATA>;
 338                         reset-names = "ahci";
 339                         status = "disabled";
 340                 };
 341
 342                 ehci1: usb@1c19000 {
 343                         compatible = "allwinner,sun8i-r40-ehci", "generic-ehci";
 344                         reg = <0x01c19000 0x100>;
 345                         interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
 346                         clocks = <&ccu CLK_BUS_EHCI1>;
 347                         resets = <&ccu RST_BUS_EHCI1>;
 348                         phys = <&usbphy 1>;
 349                         phy-names = "usb";
 350                         status = "disabled";
 351                 };
 352
 353                 ohci1: usb@1c19400 {
 354                         compatible = "allwinner,sun8i-r40-ohci", "generic-ohci";
 355                         reg = <0x01c19400 0x100>;
 356                         interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
 357                         clocks = <&ccu CLK_BUS_OHCI1>,
 358                                  <&ccu CLK_USB_OHCI1>;
 359                         resets = <&ccu RST_BUS_OHCI1>;
 360                         phys = <&usbphy 1>;
 361                         phy-names = "usb";
 362                         status = "disabled";
 363                 };
 364
 365                 ehci2: usb@1c1c000 {
 366                         compatible = "allwinner,sun8i-r40-ehci", "generic-ehci";
 367                         reg = <0x01c1c000 0x100>;
 368                         interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
 369                         clocks = <&ccu CLK_BUS_EHCI2>;
 370                         resets = <&ccu RST_BUS_EHCI2>;
 371                         phys = <&usbphy 2>;
 372                         phy-names = "usb";
 373                         status = "disabled";
 374                 };
 375
 376                 ohci2: usb@1c1c400 {
 377                         compatible = "allwinner,sun8i-r40-ohci", "generic-ohci";
 378                         reg = <0x01c1c400 0x100>;
 379                         interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
 380                         clocks = <&ccu CLK_BUS_OHCI2>,
 381                                  <&ccu CLK_USB_OHCI2>;
 382                         resets = <&ccu RST_BUS_OHCI2>;
 383                         phys = <&usbphy 2>;
 384                         phy-names = "usb";
 385                         status = "disabled";
 386                 };
 387
 388                 spi3: spi@1c1f000 {
 389                         compatible = "allwinner,sun8i-r40-spi",
 390                                      "allwinner,sun8i-h3-spi";
 391                         reg = <0x01c1f000 0x1000>;
 392                         interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
 393                         clocks = <&ccu CLK_BUS_SPI3>, <&ccu CLK_SPI3>;
 394                         clock-names = "ahb", "mod";
 395                         resets = <&ccu RST_BUS_SPI3>;
 396                         status = "disabled";
 397                         #address-cells = <1>;
 398                         #size-cells = <0>;
 399                 };
 400
 401                 ccu: clock@1c20000 {
 402                         compatible = "allwinner,sun8i-r40-ccu";
 403                         reg = <0x01c20000 0x400>;
 404                         clocks = <&osc24M>, <&rtc 0>;
 405                         clock-names = "hosc", "losc";
 406                         #clock-cells = <1>;
 407                         #reset-cells = <1>;
 408                 };
 409
 410                 rtc: rtc@1c20400 {
 411                         compatible = "allwinner,sun8i-r40-rtc";
 412                         reg = <0x01c20400 0x400>;
 413                         interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
 414                         clock-output-names = "osc32k", "osc32k-out";
 415                         clocks = <&osc32k>;
 416                         #clock-cells = <1>;
 417                 };
 418
 419                 pio: pinctrl@1c20800 {
 420                         compatible = "allwinner,sun8i-r40-pinctrl";
 421                         reg = <0x01c20800 0x400>;
 422                         interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
 423                         clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&rtc 0>;
 424                         clock-names = "apb", "hosc", "losc";
 425                         gpio-controller;
 426                         interrupt-controller;
 427                         #interrupt-cells = <3>;
 428                         #gpio-cells = <3>;
 429
 430                         clk_out_a_pin: clk-out-a-pin {
 431                                 pins = "PI12";
 432                                 function = "clk_out_a";
 433                         };
 434
 435                         /omit-if-no-ref/
 436                         csi0_8bits_pins: csi0-8bits-pins {
 437                                 pins = "PE0", "PE2", "PE3", "PE4", "PE5",
 438                                        "PE6", "PE7", "PE8", "PE9", "PE10",
 439                                        "PE11";
 440                                 function = "csi0";
 441                         };
 442
 443                         /omit-if-no-ref/
 444                         csi0_mclk_pin: csi0-mclk-pin {
 445                                 pins = "PE1";
 446                                 function = "csi0";
 447                         };
 448
 449                         gmac_rgmii_pins: gmac-rgmii-pins {
 450                                 pins = "PA0", "PA1", "PA2", "PA3",
 451                                        "PA4", "PA5", "PA6", "PA7",
 452                                        "PA8", "PA10", "PA11", "PA12",
 453                                        "PA13", "PA15", "PA16";
 454                                 function = "gmac";
 455                                 /*
 456                                  * data lines in RGMII mode use DDR mode
 457                                  * and need a higher signal drive strength
 458                                  */
 459                                 drive-strength = <40>;
 460                         };
 461
 462                         i2c0_pins: i2c0-pins {
 463                                 pins = "PB0", "PB1";
 464                                 function = "i2c0";
 465                         };
 466
 467                         i2c1_pins: i2c1-pins {
 468                                 pins = "PB18", "PB19";
 469                                 function = "i2c1";
 470                         };
 471
 472                         i2c2_pins: i2c2-pins {
 473                                 pins = "PB20", "PB21";
 474                                 function = "i2c2";
 475                         };
 476
 477                         i2c3_pins: i2c3-pins {
 478                                 pins = "PI0", "PI1";
 479                                 function = "i2c3";
 480                         };
 481
 482                         i2c4_pins: i2c4-pins {
 483                                 pins = "PI2", "PI3";
 484                                 function = "i2c4";
 485                         };
 486
 487                         mmc0_pins: mmc0-pins {
 488                                 pins = "PF0", "PF1", "PF2",
 489                                        "PF3", "PF4", "PF5";
 490                                 function = "mmc0";
 491                                 drive-strength = <30>;
 492                                 bias-pull-up;
 493                         };
 494
 495                         mmc1_pg_pins: mmc1-pg-pins {
 496                                 pins = "PG0", "PG1", "PG2",
 497                                        "PG3", "PG4", "PG5";
 498                                 function = "mmc1";
 499                                 drive-strength = <30>;
 500                                 bias-pull-up;
 501                         };
 502
 503                         mmc2_pins: mmc2-pins {
 504                                 pins = "PC5", "PC6", "PC7", "PC8", "PC9",
 505                                        "PC10", "PC11", "PC12", "PC13", "PC14",
 506                                        "PC15", "PC24";
 507                                 function = "mmc2";
 508                                 drive-strength = <30>;
 509                                 bias-pull-up;
 510                         };
 511
 512                         /omit-if-no-ref/
 513                         spi0_pc_pins: spi0-pc-pins {
 514                                 pins = "PC0", "PC1", "PC2";
 515                                 function = "spi0";
 516                         };
 517
 518                         /omit-if-no-ref/
 519                         spi0_cs0_pc_pin: spi0-cs0-pc-pin {
 520                                 pins = "PC23";
 521                                 function = "spi0";
 522                         };
 523
 524                         /omit-if-no-ref/
 525                         spi1_pi_pins: spi1-pi-pins {
 526                                 pins = "PI17", "PI18", "PI19";
 527                                 function = "spi1";
 528                         };
 529
 530                         /omit-if-no-ref/
 531                         spi1_cs0_pi_pin: spi1-cs0-pi-pin {
 532                                 pins = "PI16";
 533                                 function = "spi1";
 534                         };
 535
 536                         /omit-if-no-ref/
 537                         spi1_cs1_pi_pin: spi1-cs1-pi-pin {
 538                                 pins = "PI15";
 539                                 function = "spi1";
 540                         };
 541
 542                         uart0_pb_pins: uart0-pb-pins {
 543                                 pins = "PB22", "PB23";
 544                                 function = "uart0";
 545                         };
 546
 547                         uart3_pg_pins: uart3-pg-pins {
 548                                 pins = "PG6", "PG7";
 549                                 function = "uart3";
 550                         };
 551
 552                         uart3_rts_cts_pg_pins: uart3-rts-cts-pg-pins {
 553                                 pins = "PG8", "PG9";
 554                                 function = "uart3";
 555                         };
 556                 };
 557
 558                 wdt: watchdog@1c20c90 {
 559                         compatible = "allwinner,sun4i-a10-wdt";
 560                         reg = <0x01c20c90 0x10>;
 561                         interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
 562                         clocks = <&osc24M>;
 563                 };
 564
 565                 uart0: serial@1c28000 {
 566                         compatible = "snps,dw-apb-uart";
 567                         reg = <0x01c28000 0x400>;
 568                         interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 569                         reg-shift = <2>;
 570                         reg-io-width = <4>;
 571                         clocks = <&ccu CLK_BUS_UART0>;
 572                         resets = <&ccu RST_BUS_UART0>;
 573                         status = "disabled";
 574                 };
 575
 576                 uart1: serial@1c28400 {
 577                         compatible = "snps,dw-apb-uart";
 578                         reg = <0x01c28400 0x400>;
 579                         interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
 580                         reg-shift = <2>;
 581                         reg-io-width = <4>;
 582                         clocks = <&ccu CLK_BUS_UART1>;
 583                         resets = <&ccu RST_BUS_UART1>;
 584                         status = "disabled";
 585                 };
 586
 587                 uart2: serial@1c28800 {
 588                         compatible = "snps,dw-apb-uart";
 589                         reg = <0x01c28800 0x400>;
 590                         interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
 591                         reg-shift = <2>;
 592                         reg-io-width = <4>;
 593                         clocks = <&ccu CLK_BUS_UART2>;
 594                         resets = <&ccu RST_BUS_UART2>;
 595                         status = "disabled";
 596                 };
 597
 598                 uart3: serial@1c28c00 {
 599                         compatible = "snps,dw-apb-uart";
 600                         reg = <0x01c28c00 0x400>;
 601                         interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
 602                         reg-shift = <2>;
 603                         reg-io-width = <4>;
 604                         clocks = <&ccu CLK_BUS_UART3>;
 605                         resets = <&ccu RST_BUS_UART3>;
 606                         status = "disabled";
 607                 };
 608
 609                 uart4: serial@1c29000 {
 610                         compatible = "snps,dw-apb-uart";
 611                         reg = <0x01c29000 0x400>;
 612                         interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
 613                         reg-shift = <2>;
 614                         reg-io-width = <4>;
 615                         clocks = <&ccu CLK_BUS_UART4>;
 616                         resets = <&ccu RST_BUS_UART4>;
 617                         status = "disabled";
 618                 };
 619
 620                 uart5: serial@1c29400 {
 621                         compatible = "snps,dw-apb-uart";
 622                         reg = <0x01c29400 0x400>;
 623                         interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
 624                         reg-shift = <2>;
 625                         reg-io-width = <4>;
 626                         clocks = <&ccu CLK_BUS_UART5>;
 627                         resets = <&ccu RST_BUS_UART5>;
 628                         status = "disabled";
 629                 };
 630
 631                 uart6: serial@1c29800 {
 632                         compatible = "snps,dw-apb-uart";
 633                         reg = <0x01c29800 0x400>;
 634                         interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
 635                         reg-shift = <2>;
 636                         reg-io-width = <4>;
 637                         clocks = <&ccu CLK_BUS_UART6>;
 638                         resets = <&ccu RST_BUS_UART6>;
 639                         status = "disabled";
 640                 };
 641
 642                 uart7: serial@1c29c00 {
 643                         compatible = "snps,dw-apb-uart";
 644                         reg = <0x01c29c00 0x400>;
 645                         interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
 646                         reg-shift = <2>;
 647                         reg-io-width = <4>;
 648                         clocks = <&ccu CLK_BUS_UART7>;
 649                         resets = <&ccu RST_BUS_UART7>;
 650                         status = "disabled";
 651                 };
 652
 653                 i2c0: i2c@1c2ac00 {
 654                         compatible = "allwinner,sun6i-a31-i2c";
 655                         reg = <0x01c2ac00 0x400>;
 656                         interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
 657                         clocks = <&ccu CLK_BUS_I2C0>;
 658                         resets = <&ccu RST_BUS_I2C0>;
 659                         pinctrl-0 = <&i2c0_pins>;
 660                         pinctrl-names = "default";
 661                         status = "disabled";
 662                         #address-cells = <1>;
 663                         #size-cells = <0>;
 664                 };
 665
 666                 i2c1: i2c@1c2b000 {
 667                         compatible = "allwinner,sun6i-a31-i2c";
 668                         reg = <0x01c2b000 0x400>;
 669                         interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
 670                         clocks = <&ccu CLK_BUS_I2C1>;
 671                         resets = <&ccu RST_BUS_I2C1>;
 672                         pinctrl-0 = <&i2c1_pins>;
 673                         pinctrl-names = "default";
 674                         status = "disabled";
 675                         #address-cells = <1>;
 676                         #size-cells = <0>;
 677                 };
 678
 679                 i2c2: i2c@1c2b400 {
 680                         compatible = "allwinner,sun6i-a31-i2c";
 681                         reg = <0x01c2b400 0x400>;
 682                         interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
 683                         clocks = <&ccu CLK_BUS_I2C2>;
 684                         resets = <&ccu RST_BUS_I2C2>;
 685                         pinctrl-0 = <&i2c2_pins>;
 686                         pinctrl-names = "default";
 687                         status = "disabled";
 688                         #address-cells = <1>;
 689                         #size-cells = <0>;
 690                 };
 691
 692                 i2c3: i2c@1c2b800 {
 693                         compatible = "allwinner,sun6i-a31-i2c";
 694                         reg = <0x01c2b800 0x400>;
 695                         interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
 696                         clocks = <&ccu CLK_BUS_I2C3>;
 697                         resets = <&ccu RST_BUS_I2C3>;
 698                         pinctrl-0 = <&i2c3_pins>;
 699                         pinctrl-names = "default";
 700                         status = "disabled";
 701                         #address-cells = <1>;
 702                         #size-cells = <0>;
 703                 };
 704
 705                 i2c4: i2c@1c2c000 {
 706                         compatible = "allwinner,sun6i-a31-i2c";
 707                         reg = <0x01c2c000 0x400>;
 708                         interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
 709                         clocks = <&ccu CLK_BUS_I2C4>;
 710                         resets = <&ccu RST_BUS_I2C4>;
 711                         pinctrl-0 = <&i2c4_pins>;
 712                         pinctrl-names = "default";
 713                         status = "disabled";
 714                         #address-cells = <1>;
 715                         #size-cells = <0>;
 716                 };
 717
 718                 gmac: ethernet@1c50000 {
 719                         compatible = "allwinner,sun8i-r40-gmac";
 720                         syscon = <&ccu>;
 721                         reg = <0x01c50000 0x10000>;
 722                         interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
 723                         interrupt-names = "macirq";
 724                         resets = <&ccu RST_BUS_GMAC>;
 725                         reset-names = "stmmaceth";
 726                         clocks = <&ccu CLK_BUS_GMAC>;
 727                         clock-names = "stmmaceth";
 728                         status = "disabled";
 729
 730                         gmac_mdio: mdio {
 731                                 compatible = "snps,dwmac-mdio";
 732                                 #address-cells = <1>;
 733                                 #size-cells = <0>;
 734                         };
 735                 };
 736
 737                 mbus: dram-controller@1c62000 {
 738                         compatible = "allwinner,sun8i-r40-mbus";
 739                         reg = <0x01c62000 0x1000>;
 740                         clocks = <&ccu 155>;
 741                         dma-ranges = <0x00000000 0x40000000 0x80000000>;
 742                         #interconnect-cells = <1>;
 743                 };
 744
 745                 tcon_top: tcon-top@1c70000 {
 746                         compatible = "allwinner,sun8i-r40-tcon-top";
 747                         reg = <0x01c70000 0x1000>;
 748                         clocks = <&ccu CLK_BUS_TCON_TOP>,
 749                                  <&ccu CLK_TCON_TV0>,
 750                                  <&ccu CLK_TVE0>,
 751                                  <&ccu CLK_TCON_TV1>,
 752                                  <&ccu CLK_TVE1>,
 753                                  <&ccu CLK_DSI_DPHY>;
 754                         clock-names = "bus",
 755                                       "tcon-tv0",
 756                                       "tve0",
 757                                       "tcon-tv1",
 758                                       "tve1",
 759                                       "dsi";
 760                         clock-output-names = "tcon-top-tv0",
 761                                              "tcon-top-tv1",
 762                                              "tcon-top-dsi";
 763                         resets = <&ccu RST_BUS_TCON_TOP>;
 764                         #clock-cells = <1>;
 765
 766                         ports {
 767                                 #address-cells = <1>;
 768                                 #size-cells = <0>;
 769
 770                                 tcon_top_mixer0_in: port@0 {
 771                                         reg = <0>;
 772
 773                                         tcon_top_mixer0_in_mixer0: endpoint {
 774                                                 remote-endpoint = <&mixer0_out_tcon_top>;
 775                                         };
 776                                 };
 777
 778                                 tcon_top_mixer0_out: port@1 {
 779                                         #address-cells = <1>;
 780                                         #size-cells = <0>;
 781                                         reg = <1>;
 782
 783                                         tcon_top_mixer0_out_tcon_lcd0: endpoint@0 {
 784                                                 reg = <0>;
 785                                         };
 786
 787                                         tcon_top_mixer0_out_tcon_lcd1: endpoint@1 {
 788                                                 reg = <1>;
 789                                         };
 790
 791                                         tcon_top_mixer0_out_tcon_tv0: endpoint@2 {
 792                                                 reg = <2>;
 793                                                 remote-endpoint = <&tcon_tv0_in_tcon_top_mixer0>;
 794                                         };
 795
 796                                         tcon_top_mixer0_out_tcon_tv1: endpoint@3 {
 797                                                 reg = <3>;
 798                                                 remote-endpoint = <&tcon_tv1_in_tcon_top_mixer0>;
 799                                         };
 800                                 };
 801
 802                                 tcon_top_mixer1_in: port@2 {
 803                                         #address-cells = <1>;
 804                                         #size-cells = <0>;
 805                                         reg = <2>;
 806
 807                                         tcon_top_mixer1_in_mixer1: endpoint@1 {
 808                                                 reg = <1>;
 809                                                 remote-endpoint = <&mixer1_out_tcon_top>;
 810                                         };
 811                                 };
 812
 813                                 tcon_top_mixer1_out: port@3 {
 814                                         #address-cells = <1>;
 815                                         #size-cells = <0>;
 816                                         reg = <3>;
 817
 818                                         tcon_top_mixer1_out_tcon_lcd0: endpoint@0 {
 819                                                 reg = <0>;
 820                                         };
 821
 822                                         tcon_top_mixer1_out_tcon_lcd1: endpoint@1 {
 823                                                 reg = <1>;
 824                                         };
 825
 826                                         tcon_top_mixer1_out_tcon_tv0: endpoint@2 {
 827                                                 reg = <2>;
 828                                                 remote-endpoint = <&tcon_tv0_in_tcon_top_mixer1>;
 829                                         };
 830
 831                                         tcon_top_mixer1_out_tcon_tv1: endpoint@3 {
 832                                                 reg = <3>;
 833                                                 remote-endpoint = <&tcon_tv1_in_tcon_top_mixer1>;
 834                                         };
 835                                 };
 836
 837                                 tcon_top_hdmi_in: port@4 {
 838                                         #address-cells = <1>;
 839                                         #size-cells = <0>;
 840                                         reg = <4>;
 841
 842                                         tcon_top_hdmi_in_tcon_tv0: endpoint@0 {
 843                                                 reg = <0>;
 844                                                 remote-endpoint = <&tcon_tv0_out_tcon_top>;
 845                                         };
 846
 847                                         tcon_top_hdmi_in_tcon_tv1: endpoint@1 {
 848                                                 reg = <1>;
 849                                                 remote-endpoint = <&tcon_tv1_out_tcon_top>;
 850                                         };
 851                                 };
 852
 853                                 tcon_top_hdmi_out: port@5 {
 854                                         reg = <5>;
 855
 856                                         tcon_top_hdmi_out_hdmi: endpoint {
 857                                                 remote-endpoint = <&hdmi_in_tcon_top>;
 858                                         };
 859                                 };
 860                         };
 861                 };
 862
 863                 tcon_tv0: lcd-controller@1c73000 {
 864                         compatible = "allwinner,sun8i-r40-tcon-tv";
 865                         reg = <0x01c73000 0x1000>;
 866                         interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
 867                         clocks = <&ccu CLK_BUS_TCON_TV0>, <&tcon_top CLK_TCON_TOP_TV0>;
 868                         clock-names = "ahb", "tcon-ch1";
 869                         resets = <&ccu RST_BUS_TCON_TV0>;
 870                         reset-names = "lcd";
 871                         status = "disabled";
 872
 873                         ports {
 874                                 #address-cells = <1>;
 875                                 #size-cells = <0>;
 876
 877                                 tcon_tv0_in: port@0 {
 878                                         #address-cells = <1>;
 879                                         #size-cells = <0>;
 880                                         reg = <0>;
 881
 882                                         tcon_tv0_in_tcon_top_mixer0: endpoint@0 {
 883                                                 reg = <0>;
 884                                                 remote-endpoint = <&tcon_top_mixer0_out_tcon_tv0>;
 885                                         };
 886
 887                                         tcon_tv0_in_tcon_top_mixer1: endpoint@1 {
 888                                                 reg = <1>;
 889                                                 remote-endpoint = <&tcon_top_mixer1_out_tcon_tv0>;
 890                                         };
 891                                 };
 892
 893                                 tcon_tv0_out: port@1 {
 894                                         #address-cells = <1>;
 895                                         #size-cells = <0>;
 896                                         reg = <1>;
 897
 898                                         tcon_tv0_out_tcon_top: endpoint@1 {
 899                                                 reg = <1>;
 900                                                 remote-endpoint = <&tcon_top_hdmi_in_tcon_tv0>;
 901                                         };
 902                                 };
 903                         };
 904                 };
 905
 906                 tcon_tv1: lcd-controller@1c74000 {
 907                         compatible = "allwinner,sun8i-r40-tcon-tv";
 908                         reg = <0x01c74000 0x1000>;
 909                         interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
 910                         clocks = <&ccu CLK_BUS_TCON_TV1>, <&tcon_top CLK_TCON_TOP_TV1>;
 911                         clock-names = "ahb", "tcon-ch1";
 912                         resets = <&ccu RST_BUS_TCON_TV1>;
 913                         reset-names = "lcd";
 914                         status = "disabled";
 915
 916                         ports {
 917                                 #address-cells = <1>;
 918                                 #size-cells = <0>;
 919
 920                                 tcon_tv1_in: port@0 {
 921                                         #address-cells = <1>;
 922                                         #size-cells = <0>;
 923                                         reg = <0>;
 924
 925                                         tcon_tv1_in_tcon_top_mixer0: endpoint@0 {
 926                                                 reg = <0>;
 927                                                 remote-endpoint = <&tcon_top_mixer0_out_tcon_tv1>;
 928                                         };
 929
 930                                         tcon_tv1_in_tcon_top_mixer1: endpoint@1 {
 931                                                 reg = <1>;
 932                                                 remote-endpoint = <&tcon_top_mixer1_out_tcon_tv1>;
 933                                         };
 934                                 };
 935
 936                                 tcon_tv1_out: port@1 {
 937                                         #address-cells = <1>;
 938                                         #size-cells = <0>;
 939                                         reg = <1>;
 940
 941                                         tcon_tv1_out_tcon_top: endpoint@1 {
 942                                                 reg = <1>;
 943                                                 remote-endpoint = <&tcon_top_hdmi_in_tcon_tv1>;
 944                                         };
 945                                 };
 946                         };
 947                 };
 948
 949                 gic: interrupt-controller@1c81000 {
 950                         compatible = "arm,gic-400";
 951                         reg = <0x01c81000 0x1000>,
 952                               <0x01c82000 0x2000>,
 953                               <0x01c84000 0x2000>,
 954                               <0x01c86000 0x2000>;
 955                         interrupt-controller;
 956                         #interrupt-cells = <3>;
 957                         interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 958                 };
 959
 960                 hdmi: hdmi@1ee0000 {
 961                         compatible = "allwinner,sun8i-r40-dw-hdmi",
 962                                      "allwinner,sun8i-a83t-dw-hdmi";
 963                         reg = <0x01ee0000 0x10000>;
 964                         reg-io-width = <1>;
 965                         interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
 966                         clocks = <&ccu CLK_BUS_HDMI0>, <&ccu CLK_HDMI_SLOW>,
 967                                  <&ccu CLK_HDMI>;
 968                         clock-names = "iahb", "isfr", "tmds";
 969                         resets = <&ccu RST_BUS_HDMI1>;
 970                         reset-names = "ctrl";
 971                         phys = <&hdmi_phy>;
 972                         phy-names = "phy";
 973                         status = "disabled";
 974
 975                         ports {
 976                                 #address-cells = <1>;
 977                                 #size-cells = <0>;
 978
 979                                 hdmi_in: port@0 {
 980                                         reg = <0>;
 981
 982                                         hdmi_in_tcon_top: endpoint {
 983                                                 remote-endpoint = <&tcon_top_hdmi_out_hdmi>;
 984                                         };
 985                                 };
 986
 987                                 hdmi_out: port@1 {
 988                                         reg = <1>;
 989                                 };
 990                         };
 991                 };
 992
 993                 hdmi_phy: hdmi-phy@1ef0000 {
 994                         compatible = "allwinner,sun8i-r40-hdmi-phy";
 995                         reg = <0x01ef0000 0x10000>;
 996                         clocks = <&ccu CLK_BUS_HDMI1>, <&ccu CLK_HDMI_SLOW>,
 997                                  <&ccu CLK_PLL_VIDEO0>, <&ccu CLK_PLL_VIDEO1>;
 998                         clock-names = "bus", "mod", "pll-0", "pll-1";
 999                         resets = <&ccu RST_BUS_HDMI0>;
1000                         reset-names = "phy";
1001                         #phy-cells = <0>;
1002                 };
1003         };
1004
1005         pmu {
1006                 compatible = "arm,cortex-a7-pmu";
1007                 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
1008                              <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
1009                              <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
1010                              <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
1011                 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
1012         };
1013
1014         timer {
1015                 compatible = "arm,armv7-timer";
1016                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
1017                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
1018                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
1019                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
1020         };
1021 };