sys/gnu/dts/arm/sun8i-v3s.dtsi

   1 /*
   2  * Copyright (C) 2016 Icenowy Zheng <icenowy@aosc.xyz>
   3  *
   4  * This file is dual-licensed: you can use it either under the terms
   5  * of the GPL or the X11 license, at your option. Note that this dual
   6  * licensing only applies to this file, and not this project as a
   7  * whole.
   8  *
   9  *  a) This file is free software; you can redistribute it and/or
  10  *     modify it under the terms of the GNU General Public License as
  11  *     published by the Free Software Foundation; either version 2 of the
  12  *     License, or (at your option) any later version.
  13  *
  14  *     This file is distributed in the hope that it will be useful,
  15  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  *     GNU General Public License for more details.
  18  *
  19  * Or, alternatively,
  20  *
  21  *  b) Permission is hereby granted, free of charge, to any person
  22  *     obtaining a copy of this software and associated documentation
  23  *     files (the "Software"), to deal in the Software without
  24  *     restriction, including without limitation the rights to use,
  25  *     copy, modify, merge, publish, distribute, sublicense, and/or
  26  *     sell copies of the Software, and to permit persons to whom the
  27  *     Software is furnished to do so, subject to the following
  28  *     conditions:
  29  *
  30  *     The above copyright notice and this permission notice shall be
  31  *     included in all copies or substantial portions of the Software.
  32  *
  33  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  34  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  35  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  36  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  37  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  38  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  39  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  40  *     OTHER DEALINGS IN THE SOFTWARE.
  41  */
  42
  43 #include <dt-bindings/interrupt-controller/arm-gic.h>
  44
  45 / {
  46         #address-cells = <1>;
  47         #size-cells = <1>;
  48         interrupt-parent = <&gic>;
  49
  50         cpus {
  51                 #address-cells = <1>;
  52                 #size-cells = <0>;
  53
  54                 cpu@0 {
  55                         compatible = "arm,cortex-a7";
  56                         device_type = "cpu";
  57                         reg = <0>;
  58                         clocks = <&ccu 14>;
  59                 };
  60         };
  61
  62         timer {
  63                 compatible = "arm,armv7-timer";
  64                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
  65                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
  66                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
  67                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
  68         };
  69
  70         clocks {
  71                 #address-cells = <1>;
  72                 #size-cells = <1>;
  73                 ranges;
  74
  75                 osc24M: osc24M_clk {
  76                         #clock-cells = <0>;
  77                         compatible = "fixed-clock";
  78                         clock-frequency = <24000000>;
  79                         clock-output-names = "osc24M";
  80                 };
  81
  82                 osc32k: osc32k_clk {
  83                         #clock-cells = <0>;
  84                         compatible = "fixed-clock";
  85                         clock-frequency = <32768>;
  86                         clock-output-names = "osc32k";
  87                 };
  88         };
  89
  90         soc {
  91                 compatible = "simple-bus";
  92                 #address-cells = <1>;
  93                 #size-cells = <1>;
  94                 ranges;
  95
  96                 mmc0: mmc@01c0f000 {
  97                         compatible = "allwinner,sun7i-a20-mmc";
  98                         reg = <0x01c0f000 0x1000>;
  99                         clocks = <&ccu 22>,
 100                                  <&ccu 45>,
 101                                  <&ccu 47>,
 102                                  <&ccu 46>;
 103                         clock-names = "ahb",
 104                                       "mmc",
 105                                       "output",
 106                                       "sample";
 107                         resets = <&ccu 7>;
 108                         reset-names = "ahb";
 109                         interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
 110                         status = "disabled";
 111                         #address-cells = <1>;
 112                         #size-cells = <0>;
 113                 };
 114
 115                 mmc1: mmc@01c10000 {
 116                         compatible = "allwinner,sun7i-a20-mmc";
 117                         reg = <0x01c10000 0x1000>;
 118                         clocks = <&ccu 23>,
 119                                  <&ccu 48>,
 120                                  <&ccu 50>,
 121                                  <&ccu 49>;
 122                         clock-names = "ahb",
 123                                       "mmc",
 124                                       "output",
 125                                       "sample";
 126                         resets = <&ccu 8>;
 127                         reset-names = "ahb";
 128                         interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
 129                         status = "disabled";
 130                         #address-cells = <1>;
 131                         #size-cells = <0>;
 132                 };
 133
 134                 mmc2: mmc@01c11000 {
 135                         compatible = "allwinner,sun7i-a20-mmc";
 136                         reg = <0x01c11000 0x1000>;
 137                         clocks = <&ccu 24>,
 138                                  <&ccu 51>,
 139                                  <&ccu 53>,
 140                                  <&ccu 52>;
 141                         clock-names = "ahb",
 142                                       "mmc",
 143                                       "output",
 144                                       "sample";
 145                         resets = <&ccu 9>;
 146                         reset-names = "ahb";
 147                         interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
 148                         status = "disabled";
 149                         #address-cells = <1>;
 150                         #size-cells = <0>;
 151                 };
 152
 153                 usb_otg: usb@01c19000 {
 154                         compatible = "allwinner,sun8i-h3-musb";
 155                         reg = <0x01c19000 0x0400>;
 156                         clocks = <&ccu 29>;
 157                         resets = <&ccu 17>;
 158                         interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
 159                         interrupt-names = "mc";
 160                         phys = <&usbphy 0>;
 161                         phy-names = "usb";
 162                         extcon = <&usbphy 0>;
 163                         status = "disabled";
 164                 };
 165
 166                 usbphy: phy@01c19400 {
 167                         compatible = "allwinner,sun8i-v3s-usb-phy";
 168                         reg = <0x01c19400 0x2c>,
 169                               <0x01c1a800 0x4>;
 170                         reg-names = "phy_ctrl",
 171                                     "pmu0";
 172                         clocks = <&ccu 56>;
 173                         clock-names = "usb0_phy";
 174                         resets = <&ccu 0>;
 175                         reset-names = "usb0_reset";
 176                         status = "disabled";
 177                         #phy-cells = <1>;
 178                 };
 179
 180                 ccu: clock@01c20000 {
 181                         compatible = "allwinner,sun8i-v3s-ccu";
 182                         reg = <0x01c20000 0x400>;
 183                         clocks = <&osc24M>, <&osc32k>;
 184                         clock-names = "hosc", "losc";
 185                         #clock-cells = <1>;
 186                         #reset-cells = <1>;
 187                 };
 188
 189                 rtc: rtc@01c20400 {
 190                         compatible = "allwinner,sun6i-a31-rtc";
 191                         reg = <0x01c20400 0x54>;
 192                         interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
 193                                      <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
 194                 };
 195
 196                 pio: pinctrl@01c20800 {
 197                         compatible = "allwinner,sun8i-v3s-pinctrl";
 198                         reg = <0x01c20800 0x400>;
 199                         interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
 200                                      <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
 201                         clocks = <&ccu 37>, <&osc24M>, <&osc32k>;
 202                         clock-names = "apb", "hosc", "losc";
 203                         gpio-controller;
 204                         #gpio-cells = <3>;
 205                         interrupt-controller;
 206                         #interrupt-cells = <3>;
 207
 208                         i2c0_pins: i2c0 {
 209                                 pins = "PB6", "PB7";
 210                                 function = "i2c0";
 211                         };
 212
 213                         uart0_pins_a: uart0@0 {
 214                                 pins = "PB8", "PB9";
 215                                 function = "uart0";
 216                         };
 217
 218                         mmc0_pins_a: mmc0@0 {
 219                                 pins = "PF0", "PF1", "PF2", "PF3",
 220                                        "PF4", "PF5";
 221                                 function = "mmc0";
 222                                 drive-strength = <30>;
 223                                 bias-pull-up;
 224                         };
 225                 };
 226
 227                 timer@01c20c00 {
 228                         compatible = "allwinner,sun4i-a10-timer";
 229                         reg = <0x01c20c00 0xa0>;
 230                         interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
 231                                      <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
 232                         clocks = <&osc24M>;
 233                 };
 234
 235                 wdt0: watchdog@01c20ca0 {
 236                         compatible = "allwinner,sun6i-a31-wdt";
 237                         reg = <0x01c20ca0 0x20>;
 238                         interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
 239                 };
 240
 241                 uart0: serial@01c28000 {
 242                         compatible = "snps,dw-apb-uart";
 243                         reg = <0x01c28000 0x400>;
 244                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
 245                         reg-shift = <2>;
 246                         reg-io-width = <4>;
 247                         clocks = <&ccu 40>;
 248                         resets = <&ccu 49>;
 249                         status = "disabled";
 250                 };
 251
 252                 uart1: serial@01c28400 {
 253                         compatible = "snps,dw-apb-uart";
 254                         reg = <0x01c28400 0x400>;
 255                         interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 256                         reg-shift = <2>;
 257                         reg-io-width = <4>;
 258                         clocks = <&ccu 41>;
 259                         resets = <&ccu 50>;
 260                         status = "disabled";
 261                 };
 262
 263                 uart2: serial@01c28800 {
 264                         compatible = "snps,dw-apb-uart";
 265                         reg = <0x01c28800 0x400>;
 266                         interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
 267                         reg-shift = <2>;
 268                         reg-io-width = <4>;
 269                         clocks = <&ccu 42>;
 270                         resets = <&ccu 51>;
 271                         status = "disabled";
 272                 };
 273
 274                 i2c0: i2c@01c2ac00 {
 275                         compatible = "allwinner,sun6i-a31-i2c";
 276                         reg = <0x01c2ac00 0x400>;
 277                         interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
 278                         clocks = <&ccu 38>;
 279                         resets = <&ccu 46>;
 280                         pinctrl-names = "default";
 281                         pinctrl-0 = <&i2c0_pins>;
 282                         status = "disabled";
 283                         #address-cells = <1>;
 284                         #size-cells = <0>;
 285                 };
 286
 287                 i2c1: i2c@01c2b000 {
 288                         compatible = "allwinner,sun6i-a31-i2c";
 289                         reg = <0x01c2b000 0x400>;
 290                         interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
 291                         clocks = <&ccu 39>;
 292                         resets = <&ccu 47>;
 293                         status = "disabled";
 294                         #address-cells = <1>;
 295                         #size-cells = <0>;
 296                 };
 297
 298                 gic: interrupt-controller@01c81000 {
 299                         compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
 300                         reg = <0x01c81000 0x1000>,
 301                               <0x01c82000 0x1000>,
 302                               <0x01c84000 0x2000>,
 303                               <0x01c86000 0x2000>;
 304                         interrupt-controller;
 305                         #interrupt-cells = <3>;
 306                         interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 307                 };
 308         };
 309 };